2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/blend.h"
29 #include "main/context.h"
30 #include "main/condrender.h"
31 #include "main/samplerobj.h"
32 #include "main/state.h"
33 #include "main/enums.h"
34 #include "main/macros.h"
35 #include "main/transformfeedback.h"
36 #include "main/framebuffer.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "drivers/common/meta.h"
42 #include "util/bitscan.h"
43 #include "util/bitset.h"
45 #include "brw_blorp.h"
47 #include "brw_defines.h"
48 #include "compiler/brw_eu_defines.h"
49 #include "brw_context.h"
50 #include "brw_state.h"
52 #include "intel_batchbuffer.h"
53 #include "intel_buffers.h"
54 #include "intel_fbo.h"
55 #include "intel_mipmap_tree.h"
56 #include "intel_buffer_objects.h"
58 #define FILE_DEBUG_FLAG DEBUG_PRIMS
61 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
62 [GL_POINTS
] = GL_POINTS
,
63 [GL_LINES
] = GL_LINES
,
64 [GL_LINE_LOOP
] = GL_LINES
,
65 [GL_LINE_STRIP
] = GL_LINES
,
66 [GL_TRIANGLES
] = GL_TRIANGLES
,
67 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
68 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
69 [GL_QUADS
] = GL_TRIANGLES
,
70 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
71 [GL_POLYGON
] = GL_TRIANGLES
74 /* When the primitive changes, set a state bit and re-validate. Not
75 * the nicest and would rather deal with this by having all the
76 * programs be immune to the active primitive (ie. cope with all
77 * possibilities). That may not be realistic however.
80 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
82 struct gl_context
*ctx
= &brw
->ctx
;
83 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
85 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
87 /* Slight optimization to avoid the GS program when not needed:
89 if (prim
->mode
== GL_QUAD_STRIP
&&
90 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
91 ctx
->Polygon
.FrontMode
== GL_FILL
&&
92 ctx
->Polygon
.BackMode
== GL_FILL
)
93 hw_prim
= _3DPRIM_TRISTRIP
;
95 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
96 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
97 ctx
->Polygon
.FrontMode
== GL_FILL
&&
98 ctx
->Polygon
.BackMode
== GL_FILL
) {
99 hw_prim
= _3DPRIM_TRIFAN
;
102 if (hw_prim
!= brw
->primitive
) {
103 brw
->primitive
= hw_prim
;
104 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
106 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
107 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
108 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
114 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
116 const struct gl_context
*ctx
= &brw
->ctx
;
119 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
121 if (prim
->mode
== GL_PATCHES
) {
122 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
124 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
127 if (hw_prim
!= brw
->primitive
) {
128 brw
->primitive
= hw_prim
;
129 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
130 if (prim
->mode
== GL_PATCHES
)
131 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
137 * The hardware is capable of removing dangling vertices on its own; however,
138 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
139 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
140 * This function manually trims dangling vertices from a draw call involving
141 * quads so that those dangling vertices won't get drawn when we convert to
145 trim(GLenum prim
, GLuint length
)
147 if (prim
== GL_QUAD_STRIP
)
148 return length
> 3 ? (length
- length
% 2) : 0;
149 else if (prim
== GL_QUADS
)
150 return length
- length
% 4;
157 brw_emit_prim(struct brw_context
*brw
,
158 const struct _mesa_prim
*prim
,
160 struct brw_transform_feedback_object
*xfb_obj
,
163 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
164 int verts_per_instance
;
165 int vertex_access_type
;
168 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
169 prim
->start
, prim
->count
);
171 int start_vertex_location
= prim
->start
;
172 int base_vertex_location
= prim
->basevertex
;
175 vertex_access_type
= devinfo
->gen
>= 7 ?
176 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
177 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
178 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
179 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
181 vertex_access_type
= devinfo
->gen
>= 7 ?
182 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
183 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
184 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
187 /* We only need to trim the primitive count on pre-Gen6. */
188 if (devinfo
->gen
< 6)
189 verts_per_instance
= trim(prim
->mode
, prim
->count
);
191 verts_per_instance
= prim
->count
;
193 /* If nothing to emit, just return. */
194 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
197 /* If we're set to always flush, do it before and after the primitive emit.
198 * We want to catch both missed flushes that hurt instruction/state cache
199 * and missed flushes of the render cache as it heads to other parts of
200 * the besides the draw code.
202 if (brw
->always_flush_cache
)
203 brw_emit_mi_flush(brw
);
205 /* If indirect, emit a bunch of loads from the indirect BO. */
207 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
209 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
210 xfb_obj
->prim_count_bo
,
211 stream
* sizeof(uint32_t));
213 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
214 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
215 OUT_BATCH(prim
->num_instances
);
216 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
218 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
220 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
223 } else if (prim
->is_indirect
) {
224 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
225 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
226 intel_buffer_object(indirect_buffer
),
227 prim
->indirect_offset
, 5 * sizeof(GLuint
), false);
229 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
231 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
232 prim
->indirect_offset
+ 0);
233 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
234 prim
->indirect_offset
+ 4);
236 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
237 prim
->indirect_offset
+ 8);
239 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
240 prim
->indirect_offset
+ 12);
241 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
242 prim
->indirect_offset
+ 16);
244 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
245 prim
->indirect_offset
+ 12);
246 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
252 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
254 if (devinfo
->gen
>= 7) {
255 const int predicate_enable
=
256 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
257 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
259 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
260 OUT_BATCH(hw_prim
| vertex_access_type
);
262 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
263 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
266 OUT_BATCH(verts_per_instance
);
267 OUT_BATCH(start_vertex_location
);
268 OUT_BATCH(prim
->num_instances
);
269 OUT_BATCH(prim
->base_instance
);
270 OUT_BATCH(base_vertex_location
);
273 if (brw
->always_flush_cache
)
274 brw_emit_mi_flush(brw
);
279 brw_merge_inputs(struct brw_context
*brw
,
280 const struct gl_vertex_array
*arrays
[])
282 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
283 const struct gl_context
*ctx
= &brw
->ctx
;
286 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
287 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
288 brw
->vb
.buffers
[i
].bo
= NULL
;
290 brw
->vb
.nr_buffers
= 0;
292 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
293 brw
->vb
.inputs
[i
].buffer
= -1;
294 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
297 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
298 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
299 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
300 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
303 uint8_t wa_flags
= 0;
305 i
= u_bit_scan64(&mask
);
307 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
310 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
313 case GL_INT_2_10_10_10_REV
:
314 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
317 case GL_UNSIGNED_INT_2_10_10_10_REV
:
318 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
319 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
321 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
322 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
323 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
324 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
329 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
330 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
331 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
337 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
338 * or shader image. This causes a self-dependency, where both rendering
339 * and sampling may concurrently read or write the CCS buffer, causing
343 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
344 struct intel_mipmap_tree
*tex_mt
,
345 unsigned min_level
, unsigned num_levels
,
348 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
351 /* We only need to worry about color compression and fast clears. */
352 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
353 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
356 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
357 const struct intel_renderbuffer
*irb
=
358 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
360 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
361 irb
->mt_level
>= min_level
&&
362 irb
->mt_level
< min_level
+ num_levels
) {
363 found
= brw
->draw_aux_buffer_disabled
[i
] = true;
368 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
376 mark_textures_used_for_txf(BITSET_WORD
*used_for_txf
,
377 const struct gl_program
*prog
)
382 unsigned mask
= prog
->SamplersUsed
& prog
->info
.textures_used_by_txf
;
384 int s
= u_bit_scan(&mask
);
385 BITSET_SET(used_for_txf
, prog
->SamplerUnits
[s
]);
390 * \brief Resolve buffers before drawing.
392 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
393 * enabled depth texture, and flush the render cache for any dirty textures.
396 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
)
398 struct gl_context
*ctx
= &brw
->ctx
;
399 struct intel_texture_object
*tex_obj
;
401 memset(brw
->draw_aux_buffer_disabled
, 0,
402 sizeof(brw
->draw_aux_buffer_disabled
));
404 BITSET_DECLARE(used_for_txf
, MAX_COMBINED_TEXTURE_IMAGE_UNITS
);
405 memset(used_for_txf
, 0, sizeof(used_for_txf
));
407 mark_textures_used_for_txf(used_for_txf
, ctx
->VertexProgram
._Current
);
408 mark_textures_used_for_txf(used_for_txf
, ctx
->TessCtrlProgram
._Current
);
409 mark_textures_used_for_txf(used_for_txf
, ctx
->TessEvalProgram
._Current
);
410 mark_textures_used_for_txf(used_for_txf
, ctx
->GeometryProgram
._Current
);
411 mark_textures_used_for_txf(used_for_txf
, ctx
->FragmentProgram
._Current
);
413 mark_textures_used_for_txf(used_for_txf
, ctx
->ComputeProgram
._Current
);
416 /* Resolve depth buffer and render cache of each enabled texture. */
417 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
418 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
419 if (!ctx
->Texture
.Unit
[i
]._Current
)
421 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
422 if (!tex_obj
|| !tex_obj
->mt
)
425 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
426 enum isl_format view_format
=
427 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
429 unsigned min_level
, min_layer
, num_levels
, num_layers
;
430 if (tex_obj
->base
.Immutable
) {
431 min_level
= tex_obj
->base
.MinLevel
;
432 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
433 min_layer
= tex_obj
->base
.MinLayer
;
434 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
435 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
437 min_level
= tex_obj
->base
.BaseLevel
;
438 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
440 num_layers
= INTEL_REMAINING_LAYERS
;
443 const bool disable_aux
= rendering
&&
444 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
, min_level
, num_levels
,
447 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
448 min_level
, num_levels
,
449 min_layer
, num_layers
,
452 /* If any programs are using it with texelFetch, we may need to also do
453 * a prepare with an sRGB format to ensure texelFetch works "properly".
455 if (BITSET_TEST(used_for_txf
, i
)) {
456 enum isl_format txf_format
=
457 translate_tex_format(brw
, tex_obj
->_Format
, GL_DECODE_EXT
);
458 if (txf_format
!= view_format
) {
459 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, txf_format
,
460 min_level
, num_levels
,
461 min_layer
, num_layers
,
466 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
468 if (tex_obj
->base
.StencilSampling
||
469 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
470 intel_update_r8stencil(brw
, tex_obj
->mt
);
474 /* Resolve color for each active shader image. */
475 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
476 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
478 if (unlikely(prog
&& prog
->info
.num_images
)) {
479 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
480 struct gl_image_unit
*u
=
481 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
482 tex_obj
= intel_texture_object(u
->TexObj
);
484 if (tex_obj
&& tex_obj
->mt
) {
486 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
, 0, ~0,
487 "as a shader image");
490 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
492 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
500 brw_predraw_resolve_framebuffer(struct brw_context
*brw
)
502 struct gl_context
*ctx
= &brw
->ctx
;
503 struct intel_renderbuffer
*depth_irb
;
505 /* Resolve the depth buffer's HiZ buffer. */
506 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
507 if (depth_irb
&& depth_irb
->mt
) {
508 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
511 depth_irb
->layer_count
);
514 /* Resolve color buffers for non-coherent framebuffer fetch. */
515 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
516 ctx
->FragmentProgram
._Current
&&
517 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
518 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
520 /* This is only used for non-coherent framebuffer fetch, so we don't
521 * need to worry about CCS_E and can simply pass 'false' below.
523 assert(brw
->screen
->devinfo
.gen
< 9);
525 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
526 const struct intel_renderbuffer
*irb
=
527 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
530 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
532 irb
->mt_layer
, irb
->layer_count
,
538 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
539 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
540 struct intel_renderbuffer
*irb
=
541 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
543 if (irb
== NULL
|| irb
->mt
== NULL
)
546 mesa_format mesa_format
=
547 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
548 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
549 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
550 enum isl_aux_usage aux_usage
=
551 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
554 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
555 irb
->mt_layer
, irb
->layer_count
,
556 isl_format
, blend_enabled
);
558 brw_cache_flush_for_render(brw
, irb
->mt
->bo
,
559 isl_format
, aux_usage
);
564 * \brief Call this after drawing to mark which buffers need resolving
566 * If the depth buffer was written to and if it has an accompanying HiZ
567 * buffer, then mark that it needs a depth resolve.
569 * If the color buffer is a multisample window system buffer, then
570 * mark that it needs a downsample.
572 * Also mark any render targets which will be textured as needing a render
576 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
578 struct gl_context
*ctx
= &brw
->ctx
;
579 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
581 struct intel_renderbuffer
*front_irb
= NULL
;
582 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
583 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
584 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
585 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
587 if (_mesa_is_front_buffer_drawing(fb
))
588 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
591 front_irb
->need_downsample
= true;
593 back_irb
->need_downsample
= true;
595 bool depth_written
= brw_depth_writes_enabled(brw
);
596 if (depth_att
->Layered
) {
597 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
600 depth_irb
->layer_count
,
603 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
605 depth_irb
->mt_layer
, 1,
609 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
612 if (stencil_irb
&& brw
->stencil_write_enabled
)
613 brw_depth_cache_add_bo(brw
, stencil_irb
->mt
->bo
);
615 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
616 struct intel_renderbuffer
*irb
=
617 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
622 mesa_format mesa_format
=
623 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
624 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
625 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
626 enum isl_aux_usage aux_usage
=
627 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
630 brw_render_cache_add_bo(brw
, irb
->mt
->bo
, isl_format
, aux_usage
);
632 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
633 irb
->mt_layer
, irb
->layer_count
,
634 isl_format
, blend_enabled
);
639 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
640 struct intel_renderbuffer
*irb
)
642 if (irb
->align_wa_mt
== NULL
)
645 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
647 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
649 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
651 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
653 /* Finally restore the x,y to correspond to full miptree. */
654 intel_renderbuffer_set_draw_offset(irb
);
656 /* Make sure render surface state gets re-emitted with updated miptree. */
657 brw
->NewGLState
|= _NEW_BUFFERS
;
661 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
663 struct gl_context
*ctx
= &brw
->ctx
;
664 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
666 struct intel_renderbuffer
*depth_irb
=
667 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
668 struct intel_renderbuffer
*stencil_irb
=
669 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
671 if (depth_irb
&& depth_irb
->align_wa_mt
)
672 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
674 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
675 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
677 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
678 struct intel_renderbuffer
*irb
=
679 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
681 if (!irb
|| irb
->align_wa_mt
== NULL
)
684 intel_renderbuffer_move_temp_back(brw
, irb
);
689 brw_prepare_drawing(struct gl_context
*ctx
,
690 const struct gl_vertex_array
*arrays
[],
691 const struct _mesa_index_buffer
*ib
,
692 bool index_bounds_valid
,
696 struct brw_context
*brw
= brw_context(ctx
);
699 _mesa_update_state(ctx
);
701 /* We have to validate the textures *before* checking for fallbacks;
702 * otherwise, the software fallback won't be able to rely on the
703 * texture state, the firstLevel and lastLevel fields won't be
704 * set in the intel texture object (they'll both be 0), and the
705 * software fallback will segfault if it attempts to access any
706 * texture level other than level 0.
708 brw_validate_textures(brw
);
710 /* Find the highest sampler unit used by each shader program. A bit-count
711 * won't work since ARB programs use the texture unit number as the sampler
714 brw
->wm
.base
.sampler_count
=
715 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
716 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
717 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
718 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
719 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
720 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
721 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
722 brw
->vs
.base
.sampler_count
=
723 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
725 intel_prepare_render(brw
);
727 /* This workaround has to happen outside of brw_upload_render_state()
728 * because it may flush the batchbuffer for a blit, affecting the state
731 brw_workaround_depthstencil_alignment(brw
, 0);
733 /* Resolves must occur after updating renderbuffers, updating context state,
734 * and finalizing textures but before setting up any hardware state for
737 brw_predraw_resolve_inputs(brw
, true);
738 brw_predraw_resolve_framebuffer(brw
);
740 /* Bind all inputs, derive varying and size information:
742 brw_merge_inputs(brw
, arrays
);
745 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
747 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
748 brw
->vb
.min_index
= min_index
;
749 brw
->vb
.max_index
= max_index
;
750 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
754 brw_finish_drawing(struct gl_context
*ctx
)
756 struct brw_context
*brw
= brw_context(ctx
);
758 if (brw
->always_flush_batch
)
759 intel_batchbuffer_flush(brw
);
761 brw_program_cache_check_size(brw
);
762 brw_postdraw_reconcile_align_wa_slices(brw
);
763 brw_postdraw_set_buffers_need_resolve(brw
);
765 if (brw
->draw
.draw_params_count_bo
) {
766 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
767 brw
->draw
.draw_params_count_bo
= NULL
;
771 /* May fail if out of video memory for texture or vbo upload, or on
772 * fallback conditions.
775 brw_draw_single_prim(struct gl_context
*ctx
,
776 const struct gl_vertex_array
*arrays
[],
777 const struct _mesa_prim
*prim
,
779 struct brw_transform_feedback_object
*xfb_obj
,
781 struct gl_buffer_object
*indirect
)
783 struct brw_context
*brw
= brw_context(ctx
);
784 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
785 bool fail_next
= false;
787 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
788 * atoms that happen on every draw call.
790 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
792 /* Flush the batch if the batch/state buffers are nearly full. We can
793 * grow them if needed, but this is not free, so we'd like to avoid it.
795 intel_batchbuffer_require_space(brw
, 1500, RENDER_RING
);
796 brw_require_statebuffer_space(brw
, 2400);
797 intel_batchbuffer_save_state(brw
);
799 if (brw
->num_instances
!= prim
->num_instances
||
800 brw
->basevertex
!= prim
->basevertex
||
801 brw
->baseinstance
!= prim
->base_instance
) {
802 brw
->num_instances
= prim
->num_instances
;
803 brw
->basevertex
= prim
->basevertex
;
804 brw
->baseinstance
= prim
->base_instance
;
805 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
806 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
807 brw_merge_inputs(brw
, arrays
);
811 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
812 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
813 * always flag if the shader uses one of the values. For direct draws,
814 * we only flag if the values change.
816 const int new_basevertex
=
817 prim
->indexed
? prim
->basevertex
: prim
->start
;
818 const int new_baseinstance
= prim
->base_instance
;
819 const struct brw_vs_prog_data
*vs_prog_data
=
820 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
822 const bool uses_draw_parameters
=
823 vs_prog_data
->uses_basevertex
||
824 vs_prog_data
->uses_baseinstance
;
826 if ((uses_draw_parameters
&& prim
->is_indirect
) ||
827 (vs_prog_data
->uses_basevertex
&&
828 brw
->draw
.params
.gl_basevertex
!= new_basevertex
) ||
829 (vs_prog_data
->uses_baseinstance
&&
830 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
831 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
834 brw
->draw
.params
.gl_basevertex
= new_basevertex
;
835 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
836 brw_bo_unreference(brw
->draw
.draw_params_bo
);
838 if (prim
->is_indirect
) {
839 /* Point draw_params_bo at the indirect buffer. */
840 brw
->draw
.draw_params_bo
=
841 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
842 brw_bo_reference(brw
->draw
.draw_params_bo
);
843 brw
->draw
.draw_params_offset
=
844 prim
->indirect_offset
+ (prim
->indexed
? 12 : 8);
846 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
847 * has to upload gl_BaseVertex and such if they're needed.
849 brw
->draw
.draw_params_bo
= NULL
;
850 brw
->draw
.draw_params_offset
= 0;
853 /* gl_DrawID always needs its own vertex buffer since it's not part of
854 * the indirect parameter buffer. If the program uses gl_DrawID we need
855 * to flag BRW_NEW_VERTICES. For the first iteration, we don't have
856 * valid vs_prog_data, but we always flag BRW_NEW_VERTICES before
859 brw
->draw
.gl_drawid
= prim
->draw_id
;
860 brw_bo_unreference(brw
->draw
.draw_id_bo
);
861 brw
->draw
.draw_id_bo
= NULL
;
862 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
863 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
865 if (devinfo
->gen
< 6)
866 brw_set_prim(brw
, prim
);
868 gen6_set_prim(brw
, prim
);
872 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
873 * that the state updated in the loop outside of this block is that in
874 * *_set_prim or intel_batchbuffer_flush(), which only impacts
875 * brw->ctx.NewDriverState.
877 if (brw
->ctx
.NewDriverState
) {
878 brw
->batch
.no_wrap
= true;
879 brw_upload_render_state(brw
);
882 brw_emit_prim(brw
, prim
, brw
->primitive
, xfb_obj
, stream
);
884 brw
->batch
.no_wrap
= false;
886 if (!brw_batch_has_aperture_space(brw
, 0)) {
888 intel_batchbuffer_reset_to_saved(brw
);
889 intel_batchbuffer_flush(brw
);
893 int ret
= intel_batchbuffer_flush(brw
);
894 WARN_ONCE(ret
== -ENOSPC
,
895 "i965: Single primitive emit exceeded "
896 "available aperture space\n");
900 /* Now that we know we haven't run out of aperture space, we can safely
901 * reset the dirty bits.
903 if (brw
->ctx
.NewDriverState
)
904 brw_render_state_finished(brw
);
910 brw_draw_prims(struct gl_context
*ctx
,
911 const struct _mesa_prim
*prims
,
913 const struct _mesa_index_buffer
*ib
,
914 GLboolean index_bounds_valid
,
917 struct gl_transform_feedback_object
*gl_xfb_obj
,
919 struct gl_buffer_object
*indirect
)
922 struct brw_context
*brw
= brw_context(ctx
);
923 const struct gl_vertex_array
**arrays
= ctx
->Array
._DrawArrays
;
924 int predicate_state
= brw
->predicate
.state
;
925 struct brw_transform_feedback_object
*xfb_obj
=
926 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
928 if (!brw_check_conditional_render(brw
))
931 /* Handle primitive restart if needed */
932 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
933 /* The draw was handled, so we can exit now */
937 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
938 * won't support all the extensions we support.
940 if (ctx
->RenderMode
!= GL_RENDER
) {
941 perf_debug("%s render mode not supported in hardware\n",
942 _mesa_enum_to_string(ctx
->RenderMode
));
943 _swsetup_Wakeup(ctx
);
945 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
946 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
950 /* If we're going to have to upload any of the user's vertex arrays, then
951 * get the minimum and maximum of their index buffer so we know what range
954 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
955 perf_debug("Scanning index buffer to compute index buffer bounds. "
956 "Use glDrawRangeElements() to avoid this.\n");
957 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
958 index_bounds_valid
= true;
961 brw_prepare_drawing(ctx
, arrays
, ib
, index_bounds_valid
, min_index
,
963 /* Try drawing with the hardware, but don't do anything else if we can't
964 * manage it. swrast doesn't support our featureset, so we can't fall back
968 for (i
= 0; i
< nr_prims
; i
++) {
969 /* Implementation of ARB_indirect_parameters via predicates */
970 if (brw
->draw
.draw_params_count_bo
) {
971 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
973 /* Upload the current draw count from the draw parameters buffer to
976 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
977 brw
->draw
.draw_params_count_bo
,
978 brw
->draw
.draw_params_count_offset
);
979 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
980 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
981 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
982 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
985 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
986 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
987 MI_PREDICATE_COMBINEOP_SET
|
988 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
990 OUT_BATCH(GEN7_MI_PREDICATE
|
991 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
992 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
996 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
999 brw_draw_single_prim(ctx
, arrays
, &prims
[i
], i
, xfb_obj
, stream
,
1003 brw_finish_drawing(ctx
);
1004 brw
->predicate
.state
= predicate_state
;
1008 brw_draw_indirect_prims(struct gl_context
*ctx
,
1010 struct gl_buffer_object
*indirect_data
,
1011 GLsizeiptr indirect_offset
,
1012 unsigned draw_count
,
1014 struct gl_buffer_object
*indirect_params
,
1015 GLsizeiptr indirect_params_offset
,
1016 const struct _mesa_index_buffer
*ib
)
1018 struct brw_context
*brw
= brw_context(ctx
);
1019 struct _mesa_prim
*prim
;
1022 prim
= calloc(draw_count
, sizeof(*prim
));
1024 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
1025 (draw_count
> 1) ? "Multi" : "",
1026 ib
? "Elements" : "Arrays",
1027 indirect_params
? "CountARB" : "");
1032 prim
[draw_count
- 1].end
= 1;
1033 for (i
= 0; i
< draw_count
; ++i
, indirect_offset
+= stride
) {
1034 prim
[i
].mode
= mode
;
1035 prim
[i
].indexed
= ib
!= NULL
;
1036 prim
[i
].indirect_offset
= indirect_offset
;
1037 prim
[i
].is_indirect
= 1;
1038 prim
[i
].draw_id
= i
;
1041 if (indirect_params
) {
1042 brw
->draw
.draw_params_count_bo
=
1043 intel_buffer_object(indirect_params
)->buffer
;
1044 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
1045 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
1048 brw_draw_prims(ctx
, prim
, draw_count
,
1057 brw_draw_init(struct brw_context
*brw
)
1059 struct gl_context
*ctx
= &brw
->ctx
;
1061 /* Register our drawing function:
1063 vbo_set_draw_func(ctx
, brw_draw_prims
);
1064 vbo_set_indirect_draw_func(ctx
, brw_draw_indirect_prims
);
1066 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1067 brw
->vb
.inputs
[i
].buffer
= -1;
1068 brw
->vb
.nr_buffers
= 0;
1069 brw
->vb
.nr_enabled
= 0;
1073 brw_draw_destroy(struct brw_context
*brw
)
1077 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1078 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1079 brw
->vb
.buffers
[i
].bo
= NULL
;
1081 brw
->vb
.nr_buffers
= 0;
1083 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1084 brw
->vb
.enabled
[i
]->buffer
= -1;
1086 brw
->vb
.nr_enabled
= 0;
1088 brw_bo_unreference(brw
->ib
.bo
);