2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/context.h"
29 #include "main/condrender.h"
30 #include "main/samplerobj.h"
31 #include "main/state.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/transformfeedback.h"
35 #include "main/framebuffer.h"
37 #include "vbo/vbo_context.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "drivers/common/meta.h"
41 #include "util/bitscan.h"
43 #include "brw_blorp.h"
45 #include "brw_defines.h"
46 #include "compiler/brw_eu_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_buffer_objects.h"
56 #define FILE_DEBUG_FLAG DEBUG_PRIMS
59 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
60 [GL_POINTS
] = GL_POINTS
,
61 [GL_LINES
] = GL_LINES
,
62 [GL_LINE_LOOP
] = GL_LINES
,
63 [GL_LINE_STRIP
] = GL_LINES
,
64 [GL_TRIANGLES
] = GL_TRIANGLES
,
65 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
66 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
67 [GL_QUADS
] = GL_TRIANGLES
,
68 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
69 [GL_POLYGON
] = GL_TRIANGLES
72 /* When the primitive changes, set a state bit and re-validate. Not
73 * the nicest and would rather deal with this by having all the
74 * programs be immune to the active primitive (ie. cope with all
75 * possibilities). That may not be realistic however.
78 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
80 struct gl_context
*ctx
= &brw
->ctx
;
81 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
83 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
85 /* Slight optimization to avoid the GS program when not needed:
87 if (prim
->mode
== GL_QUAD_STRIP
&&
88 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
89 ctx
->Polygon
.FrontMode
== GL_FILL
&&
90 ctx
->Polygon
.BackMode
== GL_FILL
)
91 hw_prim
= _3DPRIM_TRISTRIP
;
93 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
94 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
95 ctx
->Polygon
.FrontMode
== GL_FILL
&&
96 ctx
->Polygon
.BackMode
== GL_FILL
) {
97 hw_prim
= _3DPRIM_TRIFAN
;
100 if (hw_prim
!= brw
->primitive
) {
101 brw
->primitive
= hw_prim
;
102 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
104 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
105 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
106 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
112 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
114 const struct gl_context
*ctx
= &brw
->ctx
;
117 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
119 if (prim
->mode
== GL_PATCHES
) {
120 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
122 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
125 if (hw_prim
!= brw
->primitive
) {
126 brw
->primitive
= hw_prim
;
127 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
128 if (prim
->mode
== GL_PATCHES
)
129 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
135 * The hardware is capable of removing dangling vertices on its own; however,
136 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
137 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
138 * This function manually trims dangling vertices from a draw call involving
139 * quads so that those dangling vertices won't get drawn when we convert to
143 trim(GLenum prim
, GLuint length
)
145 if (prim
== GL_QUAD_STRIP
)
146 return length
> 3 ? (length
- length
% 2) : 0;
147 else if (prim
== GL_QUADS
)
148 return length
- length
% 4;
155 brw_emit_prim(struct brw_context
*brw
,
156 const struct _mesa_prim
*prim
,
158 struct brw_transform_feedback_object
*xfb_obj
,
161 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
162 int verts_per_instance
;
163 int vertex_access_type
;
166 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
167 prim
->start
, prim
->count
);
169 int start_vertex_location
= prim
->start
;
170 int base_vertex_location
= prim
->basevertex
;
173 vertex_access_type
= devinfo
->gen
>= 7 ?
174 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
175 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
176 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
177 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
179 vertex_access_type
= devinfo
->gen
>= 7 ?
180 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
181 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
182 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
185 /* We only need to trim the primitive count on pre-Gen6. */
186 if (devinfo
->gen
< 6)
187 verts_per_instance
= trim(prim
->mode
, prim
->count
);
189 verts_per_instance
= prim
->count
;
191 /* If nothing to emit, just return. */
192 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
195 /* If we're set to always flush, do it before and after the primitive emit.
196 * We want to catch both missed flushes that hurt instruction/state cache
197 * and missed flushes of the render cache as it heads to other parts of
198 * the besides the draw code.
200 if (brw
->always_flush_cache
)
201 brw_emit_mi_flush(brw
);
203 /* If indirect, emit a bunch of loads from the indirect BO. */
205 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
207 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
208 xfb_obj
->prim_count_bo
,
209 stream
* sizeof(uint32_t));
211 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
212 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
213 OUT_BATCH(prim
->num_instances
);
214 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
216 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
218 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
221 } else if (prim
->is_indirect
) {
222 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
223 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
224 intel_buffer_object(indirect_buffer
),
225 prim
->indirect_offset
, 5 * sizeof(GLuint
), false);
227 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
229 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
230 prim
->indirect_offset
+ 0);
231 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
232 prim
->indirect_offset
+ 4);
234 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
235 prim
->indirect_offset
+ 8);
237 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
238 prim
->indirect_offset
+ 12);
239 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
240 prim
->indirect_offset
+ 16);
242 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
243 prim
->indirect_offset
+ 12);
245 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
246 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
254 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
256 if (devinfo
->gen
>= 7) {
257 const int predicate_enable
=
258 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
259 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
261 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
262 OUT_BATCH(hw_prim
| vertex_access_type
);
264 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
265 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
268 OUT_BATCH(verts_per_instance
);
269 OUT_BATCH(start_vertex_location
);
270 OUT_BATCH(prim
->num_instances
);
271 OUT_BATCH(prim
->base_instance
);
272 OUT_BATCH(base_vertex_location
);
275 if (brw
->always_flush_cache
)
276 brw_emit_mi_flush(brw
);
281 brw_merge_inputs(struct brw_context
*brw
,
282 const struct gl_vertex_array
*arrays
[])
284 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
285 const struct gl_context
*ctx
= &brw
->ctx
;
288 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
289 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
290 brw
->vb
.buffers
[i
].bo
= NULL
;
292 brw
->vb
.nr_buffers
= 0;
294 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
295 brw
->vb
.inputs
[i
].buffer
= -1;
296 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
299 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
300 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
301 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
302 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
305 uint8_t wa_flags
= 0;
307 i
= u_bit_scan64(&mask
);
309 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
312 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
315 case GL_INT_2_10_10_10_REV
:
316 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
319 case GL_UNSIGNED_INT_2_10_10_10_REV
:
320 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
321 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
323 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
324 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
325 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
326 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
331 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
332 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
333 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
339 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
340 * or shader image. This causes a self-dependency, where both rendering
341 * and sampling may concurrently read or write the CCS buffer, causing
345 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
346 struct intel_mipmap_tree
*tex_mt
,
349 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
352 /* We only need to worry about color compression and fast clears. */
353 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
354 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
357 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
358 const struct intel_renderbuffer
*irb
=
359 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
361 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
) {
362 found
= brw
->draw_aux_buffer_disabled
[i
] = true;
367 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
375 * \brief Resolve buffers before drawing.
377 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
378 * enabled depth texture, and flush the render cache for any dirty textures.
381 brw_predraw_resolve_inputs(struct brw_context
*brw
)
383 struct gl_context
*ctx
= &brw
->ctx
;
384 struct intel_texture_object
*tex_obj
;
386 memset(brw
->draw_aux_buffer_disabled
, 0,
387 sizeof(brw
->draw_aux_buffer_disabled
));
389 /* Resolve depth buffer and render cache of each enabled texture. */
390 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
391 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
392 if (!ctx
->Texture
.Unit
[i
]._Current
)
394 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
395 if (!tex_obj
|| !tex_obj
->mt
)
398 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
399 enum isl_format view_format
=
400 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
402 const bool disable_aux
=
403 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
, "for sampling");
405 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
406 0, INTEL_REMAINING_LEVELS
,
407 0, INTEL_REMAINING_LAYERS
,
410 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->bo
);
412 if (tex_obj
->base
.StencilSampling
||
413 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
414 intel_update_r8stencil(brw
, tex_obj
->mt
);
418 /* Resolve color for each active shader image. */
419 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
420 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
422 if (unlikely(prog
&& prog
->info
.num_images
)) {
423 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
424 struct gl_image_unit
*u
=
425 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
426 tex_obj
= intel_texture_object(u
->TexObj
);
428 if (tex_obj
&& tex_obj
->mt
) {
429 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
,
430 "as a shader image");
432 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
434 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->bo
);
442 brw_predraw_resolve_framebuffer(struct brw_context
*brw
)
444 struct gl_context
*ctx
= &brw
->ctx
;
445 struct intel_renderbuffer
*depth_irb
;
447 /* Resolve the depth buffer's HiZ buffer. */
448 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
449 if (depth_irb
&& depth_irb
->mt
) {
450 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
453 depth_irb
->layer_count
);
456 /* Resolve color buffers for non-coherent framebuffer fetch. */
457 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
458 ctx
->FragmentProgram
._Current
&&
459 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
460 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
462 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
463 const struct intel_renderbuffer
*irb
=
464 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
467 intel_miptree_prepare_fb_fetch(brw
, irb
->mt
, irb
->mt_level
,
468 irb
->mt_layer
, irb
->layer_count
);
473 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
474 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
475 struct intel_renderbuffer
*irb
=
476 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
478 if (irb
== NULL
|| irb
->mt
== NULL
)
481 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
482 irb
->mt_layer
, irb
->layer_count
,
483 ctx
->Color
.sRGBEnabled
,
484 ctx
->Color
.BlendEnabled
& (1 << i
));
489 * \brief Call this after drawing to mark which buffers need resolving
491 * If the depth buffer was written to and if it has an accompanying HiZ
492 * buffer, then mark that it needs a depth resolve.
494 * If the color buffer is a multisample window system buffer, then
495 * mark that it needs a downsample.
497 * Also mark any render targets which will be textured as needing a render
501 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
503 struct gl_context
*ctx
= &brw
->ctx
;
504 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
506 struct intel_renderbuffer
*front_irb
= NULL
;
507 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
508 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
509 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
510 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
512 if (_mesa_is_front_buffer_drawing(fb
))
513 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
516 front_irb
->need_downsample
= true;
518 back_irb
->need_downsample
= true;
520 bool depth_written
= brw_depth_writes_enabled(brw
);
521 if (depth_att
->Layered
) {
522 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
525 depth_irb
->layer_count
,
528 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
530 depth_irb
->mt_layer
, 1,
534 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
537 if (ctx
->Extensions
.ARB_stencil_texturing
&&
538 stencil_irb
&& brw
->stencil_write_enabled
) {
539 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
542 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
543 struct intel_renderbuffer
*irb
=
544 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
549 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
550 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
551 irb
->mt_layer
, irb
->layer_count
,
552 ctx
->Color
.sRGBEnabled
,
553 ctx
->Color
.BlendEnabled
& (1 << i
));
558 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
559 struct intel_renderbuffer
*irb
)
561 if (irb
->align_wa_mt
== NULL
)
564 brw_render_cache_set_check_flush(brw
, irb
->align_wa_mt
->bo
);
566 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
568 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
570 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
572 /* Finally restore the x,y to correspond to full miptree. */
573 intel_renderbuffer_set_draw_offset(irb
);
575 /* Make sure render surface state gets re-emitted with updated miptree. */
576 brw
->NewGLState
|= _NEW_BUFFERS
;
580 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
582 struct gl_context
*ctx
= &brw
->ctx
;
583 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
585 struct intel_renderbuffer
*depth_irb
=
586 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
587 struct intel_renderbuffer
*stencil_irb
=
588 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
590 if (depth_irb
&& depth_irb
->align_wa_mt
)
591 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
593 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
594 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
596 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
597 struct intel_renderbuffer
*irb
=
598 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
600 if (!irb
|| irb
->align_wa_mt
== NULL
)
603 intel_renderbuffer_move_temp_back(brw
, irb
);
608 brw_prepare_drawing(struct gl_context
*ctx
,
609 const struct gl_vertex_array
*arrays
[],
610 const struct _mesa_index_buffer
*ib
,
611 bool index_bounds_valid
,
615 struct brw_context
*brw
= brw_context(ctx
);
618 _mesa_update_state(ctx
);
620 /* We have to validate the textures *before* checking for fallbacks;
621 * otherwise, the software fallback won't be able to rely on the
622 * texture state, the firstLevel and lastLevel fields won't be
623 * set in the intel texture object (they'll both be 0), and the
624 * software fallback will segfault if it attempts to access any
625 * texture level other than level 0.
627 brw_validate_textures(brw
);
629 /* Find the highest sampler unit used by each shader program. A bit-count
630 * won't work since ARB programs use the texture unit number as the sampler
633 brw
->wm
.base
.sampler_count
=
634 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
635 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
636 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
637 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
638 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
639 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
640 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
641 brw
->vs
.base
.sampler_count
=
642 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
644 intel_prepare_render(brw
);
646 /* This workaround has to happen outside of brw_upload_render_state()
647 * because it may flush the batchbuffer for a blit, affecting the state
650 brw_workaround_depthstencil_alignment(brw
, 0);
652 /* Resolves must occur after updating renderbuffers, updating context state,
653 * and finalizing textures but before setting up any hardware state for
656 brw_predraw_resolve_inputs(brw
);
657 brw_predraw_resolve_framebuffer(brw
);
659 /* Bind all inputs, derive varying and size information:
661 brw_merge_inputs(brw
, arrays
);
664 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
666 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
667 brw
->vb
.min_index
= min_index
;
668 brw
->vb
.max_index
= max_index
;
669 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
673 brw_finish_drawing(struct gl_context
*ctx
)
675 struct brw_context
*brw
= brw_context(ctx
);
677 if (brw
->always_flush_batch
)
678 intel_batchbuffer_flush(brw
);
680 brw_program_cache_check_size(brw
);
681 brw_postdraw_reconcile_align_wa_slices(brw
);
682 brw_postdraw_set_buffers_need_resolve(brw
);
684 if (brw
->draw
.draw_params_count_bo
) {
685 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
686 brw
->draw
.draw_params_count_bo
= NULL
;
690 /* May fail if out of video memory for texture or vbo upload, or on
691 * fallback conditions.
694 brw_draw_single_prim(struct gl_context
*ctx
,
695 const struct gl_vertex_array
*arrays
[],
696 const struct _mesa_prim
*prim
,
698 struct brw_transform_feedback_object
*xfb_obj
,
700 struct gl_buffer_object
*indirect
)
702 struct brw_context
*brw
= brw_context(ctx
);
703 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
704 bool fail_next
= false;
706 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
707 * atoms that happen on every draw call.
709 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
711 /* Flush the batch if the batch/state buffers are nearly full. We can
712 * grow them if needed, but this is not free, so we'd like to avoid it.
714 intel_batchbuffer_require_space(brw
, 1500, RENDER_RING
);
715 brw_require_statebuffer_space(brw
, 2400);
716 intel_batchbuffer_save_state(brw
);
718 if (brw
->num_instances
!= prim
->num_instances
||
719 brw
->basevertex
!= prim
->basevertex
||
720 brw
->baseinstance
!= prim
->base_instance
) {
721 brw
->num_instances
= prim
->num_instances
;
722 brw
->basevertex
= prim
->basevertex
;
723 brw
->baseinstance
= prim
->base_instance
;
724 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
725 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
726 brw_merge_inputs(brw
, arrays
);
730 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
731 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
732 * always flag if the shader uses one of the values. For direct draws,
733 * we only flag if the values change.
735 const int new_basevertex
=
736 prim
->indexed
? prim
->basevertex
: prim
->start
;
737 const int new_baseinstance
= prim
->base_instance
;
738 const struct brw_vs_prog_data
*vs_prog_data
=
739 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
741 const bool uses_draw_parameters
=
742 vs_prog_data
->uses_basevertex
||
743 vs_prog_data
->uses_baseinstance
;
745 if ((uses_draw_parameters
&& prim
->is_indirect
) ||
746 (vs_prog_data
->uses_basevertex
&&
747 brw
->draw
.params
.gl_basevertex
!= new_basevertex
) ||
748 (vs_prog_data
->uses_baseinstance
&&
749 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
750 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
753 brw
->draw
.params
.gl_basevertex
= new_basevertex
;
754 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
755 brw_bo_unreference(brw
->draw
.draw_params_bo
);
757 if (prim
->is_indirect
) {
758 /* Point draw_params_bo at the indirect buffer. */
759 brw
->draw
.draw_params_bo
=
760 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
761 brw_bo_reference(brw
->draw
.draw_params_bo
);
762 brw
->draw
.draw_params_offset
=
763 prim
->indirect_offset
+ (prim
->indexed
? 12 : 8);
765 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
766 * has to upload gl_BaseVertex and such if they're needed.
768 brw
->draw
.draw_params_bo
= NULL
;
769 brw
->draw
.draw_params_offset
= 0;
772 /* gl_DrawID always needs its own vertex buffer since it's not part of
773 * the indirect parameter buffer. If the program uses gl_DrawID we need
774 * to flag BRW_NEW_VERTICES. For the first iteration, we don't have
775 * valid vs_prog_data, but we always flag BRW_NEW_VERTICES before
778 brw
->draw
.gl_drawid
= prim
->draw_id
;
779 brw_bo_unreference(brw
->draw
.draw_id_bo
);
780 brw
->draw
.draw_id_bo
= NULL
;
781 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
782 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
784 if (devinfo
->gen
< 6)
785 brw_set_prim(brw
, prim
);
787 gen6_set_prim(brw
, prim
);
791 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
792 * that the state updated in the loop outside of this block is that in
793 * *_set_prim or intel_batchbuffer_flush(), which only impacts
794 * brw->ctx.NewDriverState.
796 if (brw
->ctx
.NewDriverState
) {
797 brw
->batch
.no_wrap
= true;
798 brw_upload_render_state(brw
);
801 brw_emit_prim(brw
, prim
, brw
->primitive
, xfb_obj
, stream
);
803 brw
->batch
.no_wrap
= false;
805 if (!brw_batch_has_aperture_space(brw
, 0)) {
807 intel_batchbuffer_reset_to_saved(brw
);
808 intel_batchbuffer_flush(brw
);
812 int ret
= intel_batchbuffer_flush(brw
);
813 WARN_ONCE(ret
== -ENOSPC
,
814 "i965: Single primitive emit exceeded "
815 "available aperture space\n");
819 /* Now that we know we haven't run out of aperture space, we can safely
820 * reset the dirty bits.
822 if (brw
->ctx
.NewDriverState
)
823 brw_render_state_finished(brw
);
829 brw_draw_prims(struct gl_context
*ctx
,
830 const struct _mesa_prim
*prims
,
832 const struct _mesa_index_buffer
*ib
,
833 GLboolean index_bounds_valid
,
836 struct gl_transform_feedback_object
*gl_xfb_obj
,
838 struct gl_buffer_object
*indirect
)
841 struct brw_context
*brw
= brw_context(ctx
);
842 const struct gl_vertex_array
**arrays
= ctx
->Array
._DrawArrays
;
843 int predicate_state
= brw
->predicate
.state
;
844 int combine_op
= MI_PREDICATE_COMBINEOP_SET
;
845 struct brw_transform_feedback_object
*xfb_obj
=
846 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
848 if (!brw_check_conditional_render(brw
))
851 /* Handle primitive restart if needed */
852 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
853 /* The draw was handled, so we can exit now */
857 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
858 * won't support all the extensions we support.
860 if (ctx
->RenderMode
!= GL_RENDER
) {
861 perf_debug("%s render mode not supported in hardware\n",
862 _mesa_enum_to_string(ctx
->RenderMode
));
863 _swsetup_Wakeup(ctx
);
865 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
866 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
870 /* If we're going to have to upload any of the user's vertex arrays, then
871 * get the minimum and maximum of their index buffer so we know what range
874 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
875 perf_debug("Scanning index buffer to compute index buffer bounds. "
876 "Use glDrawRangeElements() to avoid this.\n");
877 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
878 index_bounds_valid
= true;
881 brw_prepare_drawing(ctx
, arrays
, ib
, index_bounds_valid
, min_index
,
883 /* Try drawing with the hardware, but don't do anything else if we can't
884 * manage it. swrast doesn't support our featureset, so we can't fall back
888 if (brw
->draw
.draw_params_count_bo
&&
889 predicate_state
== BRW_PREDICATE_STATE_USE_BIT
) {
890 /* We need to empty the MI_PREDICATE_DATA register since it might
895 OUT_BATCH(MI_PREDICATE_DATA
);
897 OUT_BATCH(MI_PREDICATE_DATA
+ 4);
901 /* We need to combine the results of both predicates.*/
902 combine_op
= MI_PREDICATE_COMBINEOP_AND
;
905 for (i
= 0; i
< nr_prims
; i
++) {
906 /* Implementation of ARB_indirect_parameters via predicates */
907 if (brw
->draw
.draw_params_count_bo
) {
908 struct brw_bo
*draw_id_bo
= NULL
;
909 uint32_t draw_id_offset
;
911 intel_upload_data(brw
, &prims
[i
].draw_id
, 4, 4, &draw_id_bo
,
914 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
916 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
917 brw
->draw
.draw_params_count_bo
,
918 brw
->draw
.draw_params_count_offset
);
919 brw_load_register_mem(brw
, MI_PREDICATE_SRC1
, draw_id_bo
,
923 OUT_BATCH(GEN7_MI_PREDICATE
|
924 MI_PREDICATE_LOADOP_LOADINV
| combine_op
|
925 MI_PREDICATE_COMPAREOP_DELTAS_EQUAL
);
928 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
930 brw_bo_unreference(draw_id_bo
);
933 brw_draw_single_prim(ctx
, arrays
, &prims
[i
], i
, xfb_obj
, stream
,
937 brw_finish_drawing(ctx
);
938 brw
->predicate
.state
= predicate_state
;
942 brw_draw_indirect_prims(struct gl_context
*ctx
,
944 struct gl_buffer_object
*indirect_data
,
945 GLsizeiptr indirect_offset
,
948 struct gl_buffer_object
*indirect_params
,
949 GLsizeiptr indirect_params_offset
,
950 const struct _mesa_index_buffer
*ib
)
952 struct brw_context
*brw
= brw_context(ctx
);
953 struct _mesa_prim
*prim
;
956 prim
= calloc(draw_count
, sizeof(*prim
));
958 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
959 (draw_count
> 1) ? "Multi" : "",
960 ib
? "Elements" : "Arrays",
961 indirect_params
? "CountARB" : "");
966 prim
[draw_count
- 1].end
= 1;
967 for (i
= 0; i
< draw_count
; ++i
, indirect_offset
+= stride
) {
969 prim
[i
].indexed
= ib
!= NULL
;
970 prim
[i
].indirect_offset
= indirect_offset
;
971 prim
[i
].is_indirect
= 1;
975 if (indirect_params
) {
976 brw
->draw
.draw_params_count_bo
=
977 intel_buffer_object(indirect_params
)->buffer
;
978 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
979 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
982 brw_draw_prims(ctx
, prim
, draw_count
,
991 brw_draw_init(struct brw_context
*brw
)
993 struct gl_context
*ctx
= &brw
->ctx
;
994 struct vbo_context
*vbo
= vbo_context(ctx
);
996 /* Register our drawing function:
998 vbo
->draw_prims
= brw_draw_prims
;
999 vbo
->draw_indirect_prims
= brw_draw_indirect_prims
;
1001 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1002 brw
->vb
.inputs
[i
].buffer
= -1;
1003 brw
->vb
.nr_buffers
= 0;
1004 brw
->vb
.nr_enabled
= 0;
1008 brw_draw_destroy(struct brw_context
*brw
)
1012 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1013 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1014 brw
->vb
.buffers
[i
].bo
= NULL
;
1016 brw
->vb
.nr_buffers
= 0;
1018 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1019 brw
->vb
.enabled
[i
]->buffer
= -1;
1021 brw
->vb
.nr_enabled
= 0;
1023 brw_bo_unreference(brw
->ib
.bo
);