2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/arrayobj.h"
29 #include "main/blend.h"
30 #include "main/context.h"
31 #include "main/condrender.h"
32 #include "main/samplerobj.h"
33 #include "main/state.h"
34 #include "main/enums.h"
35 #include "main/macros.h"
36 #include "main/transformfeedback.h"
37 #include "main/framebuffer.h"
38 #include "main/varray.h"
41 #include "swrast/swrast.h"
42 #include "swrast_setup/swrast_setup.h"
43 #include "drivers/common/meta.h"
44 #include "util/bitscan.h"
45 #include "util/bitset.h"
47 #include "brw_blorp.h"
49 #include "brw_defines.h"
50 #include "compiler/brw_eu_defines.h"
51 #include "brw_context.h"
52 #include "brw_state.h"
54 #include "intel_batchbuffer.h"
55 #include "intel_buffers.h"
56 #include "intel_fbo.h"
57 #include "intel_mipmap_tree.h"
58 #include "intel_buffer_objects.h"
60 #define FILE_DEBUG_FLAG DEBUG_PRIMS
63 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
64 [GL_POINTS
] = GL_POINTS
,
65 [GL_LINES
] = GL_LINES
,
66 [GL_LINE_LOOP
] = GL_LINES
,
67 [GL_LINE_STRIP
] = GL_LINES
,
68 [GL_TRIANGLES
] = GL_TRIANGLES
,
69 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
70 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
71 [GL_QUADS
] = GL_TRIANGLES
,
72 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
73 [GL_POLYGON
] = GL_TRIANGLES
76 /* When the primitive changes, set a state bit and re-validate. Not
77 * the nicest and would rather deal with this by having all the
78 * programs be immune to the active primitive (ie. cope with all
79 * possibilities). That may not be realistic however.
82 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
84 struct gl_context
*ctx
= &brw
->ctx
;
85 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
87 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
89 /* Slight optimization to avoid the GS program when not needed:
91 if (prim
->mode
== GL_QUAD_STRIP
&&
92 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
93 ctx
->Polygon
.FrontMode
== GL_FILL
&&
94 ctx
->Polygon
.BackMode
== GL_FILL
)
95 hw_prim
= _3DPRIM_TRISTRIP
;
97 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
98 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
99 ctx
->Polygon
.FrontMode
== GL_FILL
&&
100 ctx
->Polygon
.BackMode
== GL_FILL
) {
101 hw_prim
= _3DPRIM_TRIFAN
;
104 if (hw_prim
!= brw
->primitive
) {
105 brw
->primitive
= hw_prim
;
106 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
108 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
109 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
110 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
116 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
118 const struct gl_context
*ctx
= &brw
->ctx
;
121 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
123 if (prim
->mode
== GL_PATCHES
) {
124 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
126 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
129 if (hw_prim
!= brw
->primitive
) {
130 brw
->primitive
= hw_prim
;
131 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
132 if (prim
->mode
== GL_PATCHES
)
133 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
139 * The hardware is capable of removing dangling vertices on its own; however,
140 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
141 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
142 * This function manually trims dangling vertices from a draw call involving
143 * quads so that those dangling vertices won't get drawn when we convert to
147 trim(GLenum prim
, GLuint length
)
149 if (prim
== GL_QUAD_STRIP
)
150 return length
> 3 ? (length
- length
% 2) : 0;
151 else if (prim
== GL_QUADS
)
152 return length
- length
% 4;
159 brw_emit_prim(struct brw_context
*brw
,
160 const struct _mesa_prim
*prim
,
162 struct brw_transform_feedback_object
*xfb_obj
,
165 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
166 int verts_per_instance
;
167 int vertex_access_type
;
170 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
171 prim
->start
, prim
->count
);
173 int start_vertex_location
= prim
->start
;
174 int base_vertex_location
= prim
->basevertex
;
177 vertex_access_type
= devinfo
->gen
>= 7 ?
178 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
179 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
180 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
181 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
183 vertex_access_type
= devinfo
->gen
>= 7 ?
184 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
185 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
186 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
189 /* We only need to trim the primitive count on pre-Gen6. */
190 if (devinfo
->gen
< 6)
191 verts_per_instance
= trim(prim
->mode
, prim
->count
);
193 verts_per_instance
= prim
->count
;
195 /* If nothing to emit, just return. */
196 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
199 /* If we're set to always flush, do it before and after the primitive emit.
200 * We want to catch both missed flushes that hurt instruction/state cache
201 * and missed flushes of the render cache as it heads to other parts of
202 * the besides the draw code.
204 if (brw
->always_flush_cache
)
205 brw_emit_mi_flush(brw
);
207 /* If indirect, emit a bunch of loads from the indirect BO. */
209 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
211 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
212 xfb_obj
->prim_count_bo
,
213 stream
* sizeof(uint32_t));
215 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
216 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
217 OUT_BATCH(prim
->num_instances
);
218 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
220 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
222 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
225 } else if (prim
->is_indirect
) {
226 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
227 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
228 intel_buffer_object(indirect_buffer
),
229 prim
->indirect_offset
, 5 * sizeof(GLuint
), false);
231 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
233 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
234 prim
->indirect_offset
+ 0);
235 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
236 prim
->indirect_offset
+ 4);
238 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
239 prim
->indirect_offset
+ 8);
241 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
242 prim
->indirect_offset
+ 12);
243 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
244 prim
->indirect_offset
+ 16);
246 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
247 prim
->indirect_offset
+ 12);
248 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
254 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
256 if (devinfo
->gen
>= 7) {
257 const int predicate_enable
=
258 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
259 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
261 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
262 OUT_BATCH(hw_prim
| vertex_access_type
);
264 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
265 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
268 OUT_BATCH(verts_per_instance
);
269 OUT_BATCH(start_vertex_location
);
270 OUT_BATCH(prim
->num_instances
);
271 OUT_BATCH(prim
->base_instance
);
272 OUT_BATCH(base_vertex_location
);
275 if (brw
->always_flush_cache
)
276 brw_emit_mi_flush(brw
);
281 brw_merge_inputs(struct brw_context
*brw
,
282 const struct gl_vertex_array
*arrays
)
284 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
285 const struct gl_context
*ctx
= &brw
->ctx
;
288 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
289 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
290 brw
->vb
.buffers
[i
].bo
= NULL
;
292 brw
->vb
.nr_buffers
= 0;
294 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
295 brw
->vb
.inputs
[i
].buffer
= -1;
296 brw
->vb
.inputs
[i
].glarray
= &arrays
[i
];
299 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
300 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
301 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
302 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
305 const struct gl_array_attributes
*glattrib
;
306 uint8_t wa_flags
= 0;
308 i
= u_bit_scan64(&mask
);
309 glattrib
= brw
->vb
.inputs
[i
].glarray
->VertexAttrib
;
311 switch (glattrib
->Type
) {
314 wa_flags
= glattrib
->Size
;
317 case GL_INT_2_10_10_10_REV
:
318 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
321 case GL_UNSIGNED_INT_2_10_10_10_REV
:
322 if (glattrib
->Format
== GL_BGRA
)
323 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
325 if (glattrib
->Normalized
)
326 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
327 else if (!glattrib
->Integer
)
328 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
333 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
334 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
335 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
341 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
342 * or shader image. This causes a self-dependency, where both rendering
343 * and sampling may concurrently read or write the CCS buffer, causing
347 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
348 bool *draw_aux_buffer_disabled
,
349 struct intel_mipmap_tree
*tex_mt
,
350 unsigned min_level
, unsigned num_levels
,
353 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
356 /* We only need to worry about color compression and fast clears. */
357 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
358 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
361 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
362 const struct intel_renderbuffer
*irb
=
363 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
365 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
366 irb
->mt_level
>= min_level
&&
367 irb
->mt_level
< min_level
+ num_levels
) {
368 found
= draw_aux_buffer_disabled
[i
] = true;
373 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
381 mark_textures_used_for_txf(BITSET_WORD
*used_for_txf
,
382 const struct gl_program
*prog
)
387 unsigned mask
= prog
->SamplersUsed
& prog
->info
.textures_used_by_txf
;
389 int s
= u_bit_scan(&mask
);
390 BITSET_SET(used_for_txf
, prog
->SamplerUnits
[s
]);
395 * \brief Resolve buffers before drawing.
397 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
398 * enabled depth texture, and flush the render cache for any dirty textures.
401 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
402 bool *draw_aux_buffer_disabled
)
404 struct gl_context
*ctx
= &brw
->ctx
;
405 struct intel_texture_object
*tex_obj
;
407 BITSET_DECLARE(used_for_txf
, MAX_COMBINED_TEXTURE_IMAGE_UNITS
);
408 memset(used_for_txf
, 0, sizeof(used_for_txf
));
410 mark_textures_used_for_txf(used_for_txf
, ctx
->VertexProgram
._Current
);
411 mark_textures_used_for_txf(used_for_txf
, ctx
->TessCtrlProgram
._Current
);
412 mark_textures_used_for_txf(used_for_txf
, ctx
->TessEvalProgram
._Current
);
413 mark_textures_used_for_txf(used_for_txf
, ctx
->GeometryProgram
._Current
);
414 mark_textures_used_for_txf(used_for_txf
, ctx
->FragmentProgram
._Current
);
416 mark_textures_used_for_txf(used_for_txf
, ctx
->ComputeProgram
._Current
);
419 /* Resolve depth buffer and render cache of each enabled texture. */
420 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
421 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
422 if (!ctx
->Texture
.Unit
[i
]._Current
)
424 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
425 if (!tex_obj
|| !tex_obj
->mt
)
428 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
429 enum isl_format view_format
=
430 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
432 unsigned min_level
, min_layer
, num_levels
, num_layers
;
433 if (tex_obj
->base
.Immutable
) {
434 min_level
= tex_obj
->base
.MinLevel
;
435 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
436 min_layer
= tex_obj
->base
.MinLayer
;
437 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
438 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
440 min_level
= tex_obj
->base
.BaseLevel
;
441 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
443 num_layers
= INTEL_REMAINING_LAYERS
;
447 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
448 tex_obj
->mt
, min_level
, num_levels
,
452 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
453 min_level
, num_levels
,
454 min_layer
, num_layers
);
456 /* If any programs are using it with texelFetch, we may need to also do
457 * a prepare with an sRGB format to ensure texelFetch works "properly".
459 if (BITSET_TEST(used_for_txf
, i
)) {
460 enum isl_format txf_format
=
461 translate_tex_format(brw
, tex_obj
->_Format
, GL_DECODE_EXT
);
462 if (txf_format
!= view_format
) {
463 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, txf_format
,
464 min_level
, num_levels
,
465 min_layer
, num_layers
);
469 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
471 if (tex_obj
->base
.StencilSampling
||
472 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
473 intel_update_r8stencil(brw
, tex_obj
->mt
);
477 /* Resolve color for each active shader image. */
478 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
479 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
481 if (unlikely(prog
&& prog
->info
.num_images
)) {
482 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
483 struct gl_image_unit
*u
=
484 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
485 tex_obj
= intel_texture_object(u
->TexObj
);
487 if (tex_obj
&& tex_obj
->mt
) {
489 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
491 "as a shader image");
494 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
496 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
504 brw_predraw_resolve_framebuffer(struct brw_context
*brw
,
505 bool *draw_aux_buffer_disabled
)
507 struct gl_context
*ctx
= &brw
->ctx
;
508 struct intel_renderbuffer
*depth_irb
;
510 /* Resolve the depth buffer's HiZ buffer. */
511 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
512 if (depth_irb
&& depth_irb
->mt
) {
513 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
516 depth_irb
->layer_count
);
519 /* Resolve color buffers for non-coherent framebuffer fetch. */
520 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
&&
521 ctx
->FragmentProgram
._Current
&&
522 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
523 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
525 /* This is only used for non-coherent framebuffer fetch, so we don't
526 * need to worry about CCS_E and can simply pass 'false' below.
528 assert(brw
->screen
->devinfo
.gen
< 9);
530 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
531 const struct intel_renderbuffer
*irb
=
532 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
535 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
537 irb
->mt_layer
, irb
->layer_count
);
542 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
543 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
544 struct intel_renderbuffer
*irb
=
545 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
547 if (irb
== NULL
|| irb
->mt
== NULL
)
550 mesa_format mesa_format
=
551 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
552 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
553 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
554 enum isl_aux_usage aux_usage
=
555 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
557 draw_aux_buffer_disabled
[i
]);
558 if (brw
->draw_aux_usage
[i
] != aux_usage
) {
559 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
560 brw
->draw_aux_usage
[i
] = aux_usage
;
563 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
564 irb
->mt_layer
, irb
->layer_count
,
567 brw_cache_flush_for_render(brw
, irb
->mt
->bo
,
568 isl_format
, aux_usage
);
573 * \brief Call this after drawing to mark which buffers need resolving
575 * If the depth buffer was written to and if it has an accompanying HiZ
576 * buffer, then mark that it needs a depth resolve.
578 * If the color buffer is a multisample window system buffer, then
579 * mark that it needs a downsample.
581 * Also mark any render targets which will be textured as needing a render
585 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
587 struct gl_context
*ctx
= &brw
->ctx
;
588 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
590 struct intel_renderbuffer
*front_irb
= NULL
;
591 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
592 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
593 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
594 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
596 if (_mesa_is_front_buffer_drawing(fb
))
597 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
600 front_irb
->need_downsample
= true;
602 back_irb
->need_downsample
= true;
604 bool depth_written
= brw_depth_writes_enabled(brw
);
605 if (depth_att
->Layered
) {
606 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
609 depth_irb
->layer_count
,
612 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
614 depth_irb
->mt_layer
, 1,
618 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
621 if (stencil_irb
&& brw
->stencil_write_enabled
)
622 brw_depth_cache_add_bo(brw
, stencil_irb
->mt
->bo
);
624 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
625 struct intel_renderbuffer
*irb
=
626 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
631 mesa_format mesa_format
=
632 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
633 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
634 enum isl_aux_usage aux_usage
= brw
->draw_aux_usage
[i
];
636 brw_render_cache_add_bo(brw
, irb
->mt
->bo
, isl_format
, aux_usage
);
638 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
639 irb
->mt_layer
, irb
->layer_count
,
645 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
646 struct intel_renderbuffer
*irb
)
648 if (irb
->align_wa_mt
== NULL
)
651 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
653 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
655 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
657 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
659 /* Finally restore the x,y to correspond to full miptree. */
660 intel_renderbuffer_set_draw_offset(irb
);
662 /* Make sure render surface state gets re-emitted with updated miptree. */
663 brw
->NewGLState
|= _NEW_BUFFERS
;
667 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
669 struct gl_context
*ctx
= &brw
->ctx
;
670 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
672 struct intel_renderbuffer
*depth_irb
=
673 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
674 struct intel_renderbuffer
*stencil_irb
=
675 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
677 if (depth_irb
&& depth_irb
->align_wa_mt
)
678 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
680 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
681 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
683 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
684 struct intel_renderbuffer
*irb
=
685 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
687 if (!irb
|| irb
->align_wa_mt
== NULL
)
690 intel_renderbuffer_move_temp_back(brw
, irb
);
695 brw_prepare_drawing(struct gl_context
*ctx
,
696 const struct gl_vertex_array
*arrays
,
697 const struct _mesa_index_buffer
*ib
,
698 bool index_bounds_valid
,
702 struct brw_context
*brw
= brw_context(ctx
);
705 _mesa_update_state(ctx
);
707 /* We have to validate the textures *before* checking for fallbacks;
708 * otherwise, the software fallback won't be able to rely on the
709 * texture state, the firstLevel and lastLevel fields won't be
710 * set in the intel texture object (they'll both be 0), and the
711 * software fallback will segfault if it attempts to access any
712 * texture level other than level 0.
714 brw_validate_textures(brw
);
716 /* Find the highest sampler unit used by each shader program. A bit-count
717 * won't work since ARB programs use the texture unit number as the sampler
720 brw
->wm
.base
.sampler_count
=
721 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
722 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
723 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
724 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
725 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
726 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
727 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
728 brw
->vs
.base
.sampler_count
=
729 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
731 intel_prepare_render(brw
);
733 /* This workaround has to happen outside of brw_upload_render_state()
734 * because it may flush the batchbuffer for a blit, affecting the state
737 brw_workaround_depthstencil_alignment(brw
, 0);
739 /* Resolves must occur after updating renderbuffers, updating context state,
740 * and finalizing textures but before setting up any hardware state for
743 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
] = { };
744 brw_predraw_resolve_inputs(brw
, true, draw_aux_buffer_disabled
);
745 brw_predraw_resolve_framebuffer(brw
, draw_aux_buffer_disabled
);
747 /* Bind all inputs, derive varying and size information:
749 brw_merge_inputs(brw
, arrays
);
752 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
754 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
755 brw
->vb
.min_index
= min_index
;
756 brw
->vb
.max_index
= max_index
;
757 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
761 brw_finish_drawing(struct gl_context
*ctx
)
763 struct brw_context
*brw
= brw_context(ctx
);
765 if (brw
->always_flush_batch
)
766 intel_batchbuffer_flush(brw
);
768 brw_program_cache_check_size(brw
);
769 brw_postdraw_reconcile_align_wa_slices(brw
);
770 brw_postdraw_set_buffers_need_resolve(brw
);
772 if (brw
->draw
.draw_params_count_bo
) {
773 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
774 brw
->draw
.draw_params_count_bo
= NULL
;
778 /* May fail if out of video memory for texture or vbo upload, or on
779 * fallback conditions.
782 brw_draw_single_prim(struct gl_context
*ctx
,
783 const struct gl_vertex_array
*arrays
,
784 const struct _mesa_prim
*prim
,
786 struct brw_transform_feedback_object
*xfb_obj
,
788 struct gl_buffer_object
*indirect
)
790 struct brw_context
*brw
= brw_context(ctx
);
791 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
792 bool fail_next
= false;
794 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
795 * atoms that happen on every draw call.
797 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
799 /* Flush the batch if the batch/state buffers are nearly full. We can
800 * grow them if needed, but this is not free, so we'd like to avoid it.
802 intel_batchbuffer_require_space(brw
, 1500, RENDER_RING
);
803 brw_require_statebuffer_space(brw
, 2400);
804 intel_batchbuffer_save_state(brw
);
806 if (brw
->num_instances
!= prim
->num_instances
||
807 brw
->basevertex
!= prim
->basevertex
||
808 brw
->baseinstance
!= prim
->base_instance
) {
809 brw
->num_instances
= prim
->num_instances
;
810 brw
->basevertex
= prim
->basevertex
;
811 brw
->baseinstance
= prim
->base_instance
;
812 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
813 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
814 brw_merge_inputs(brw
, arrays
);
818 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
819 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
820 * always flag if the shader uses one of the values. For direct draws,
821 * we only flag if the values change.
823 const int new_firstvertex
=
824 prim
->indexed
? prim
->basevertex
: prim
->start
;
825 const int new_baseinstance
= prim
->base_instance
;
826 const struct brw_vs_prog_data
*vs_prog_data
=
827 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
829 const bool uses_draw_parameters
=
830 vs_prog_data
->uses_firstvertex
||
831 vs_prog_data
->uses_baseinstance
;
833 if ((uses_draw_parameters
&& prim
->is_indirect
) ||
834 (vs_prog_data
->uses_firstvertex
&&
835 brw
->draw
.params
.firstvertex
!= new_firstvertex
) ||
836 (vs_prog_data
->uses_baseinstance
&&
837 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
838 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
841 brw
->draw
.params
.firstvertex
= new_firstvertex
;
842 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
843 brw_bo_unreference(brw
->draw
.draw_params_bo
);
845 if (prim
->is_indirect
) {
846 /* Point draw_params_bo at the indirect buffer. */
847 brw
->draw
.draw_params_bo
=
848 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
849 brw_bo_reference(brw
->draw
.draw_params_bo
);
850 brw
->draw
.draw_params_offset
=
851 prim
->indirect_offset
+ (prim
->indexed
? 12 : 8);
853 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
854 * has to upload gl_BaseVertex and such if they're needed.
856 brw
->draw
.draw_params_bo
= NULL
;
857 brw
->draw
.draw_params_offset
= 0;
860 /* gl_DrawID always needs its own vertex buffer since it's not part of
861 * the indirect parameter buffer. Same for is_indexed_draw, which shares
862 * the buffer with gl_DrawID. If the program uses gl_DrawID, we need to
863 * flag BRW_NEW_VERTICES. For the first iteration, we don't have valid
864 * vs_prog_data, but we always flag BRW_NEW_VERTICES before the loop.
866 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
867 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
869 brw
->draw
.derived_params
.gl_drawid
= prim
->draw_id
;
870 brw
->draw
.derived_params
.is_indexed_draw
= prim
->indexed
? ~0 : 0;
872 brw_bo_unreference(brw
->draw
.derived_draw_params_bo
);
873 brw
->draw
.derived_draw_params_bo
= NULL
;
874 brw
->draw
.derived_draw_params_offset
= 0;
876 if (devinfo
->gen
< 6)
877 brw_set_prim(brw
, prim
);
879 gen6_set_prim(brw
, prim
);
883 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
884 * that the state updated in the loop outside of this block is that in
885 * *_set_prim or intel_batchbuffer_flush(), which only impacts
886 * brw->ctx.NewDriverState.
888 if (brw
->ctx
.NewDriverState
) {
889 brw
->batch
.no_wrap
= true;
890 brw_upload_render_state(brw
);
893 brw_emit_prim(brw
, prim
, brw
->primitive
, xfb_obj
, stream
);
895 brw
->batch
.no_wrap
= false;
897 if (!brw_batch_has_aperture_space(brw
, 0)) {
899 intel_batchbuffer_reset_to_saved(brw
);
900 intel_batchbuffer_flush(brw
);
904 int ret
= intel_batchbuffer_flush(brw
);
905 WARN_ONCE(ret
== -ENOSPC
,
906 "i965: Single primitive emit exceeded "
907 "available aperture space\n");
911 /* Now that we know we haven't run out of aperture space, we can safely
912 * reset the dirty bits.
914 if (brw
->ctx
.NewDriverState
)
915 brw_render_state_finished(brw
);
923 brw_draw_prims(struct gl_context
*ctx
,
924 const struct _mesa_prim
*prims
,
926 const struct _mesa_index_buffer
*ib
,
927 GLboolean index_bounds_valid
,
930 struct gl_transform_feedback_object
*gl_xfb_obj
,
932 struct gl_buffer_object
*indirect
)
935 struct brw_context
*brw
= brw_context(ctx
);
936 const struct gl_vertex_array
*arrays
;
937 int predicate_state
= brw
->predicate
.state
;
938 struct brw_transform_feedback_object
*xfb_obj
=
939 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
941 /* The initial pushdown of the inputs array into the drivers */
942 _mesa_set_drawing_arrays(ctx
, brw
->vb
.draw_arrays
.inputs
);
943 arrays
= ctx
->Array
._DrawArrays
;
944 _vbo_update_inputs(ctx
, &brw
->vb
.draw_arrays
);
946 if (!brw_check_conditional_render(brw
))
949 /* Handle primitive restart if needed */
950 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
951 /* The draw was handled, so we can exit now */
955 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
956 * won't support all the extensions we support.
958 if (ctx
->RenderMode
!= GL_RENDER
) {
959 perf_debug("%s render mode not supported in hardware\n",
960 _mesa_enum_to_string(ctx
->RenderMode
));
961 _swsetup_Wakeup(ctx
);
963 _tnl_draw(ctx
, prims
, nr_prims
, ib
,
964 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
968 /* If we're going to have to upload any of the user's vertex arrays, then
969 * get the minimum and maximum of their index buffer so we know what range
972 if (!index_bounds_valid
&& _mesa_draw_user_array_bits(ctx
) != 0) {
973 perf_debug("Scanning index buffer to compute index buffer bounds. "
974 "Use glDrawRangeElements() to avoid this.\n");
975 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
976 index_bounds_valid
= true;
979 brw_prepare_drawing(ctx
, arrays
, ib
, index_bounds_valid
, min_index
,
981 /* Try drawing with the hardware, but don't do anything else if we can't
982 * manage it. swrast doesn't support our featureset, so we can't fall back
986 for (i
= 0; i
< nr_prims
; i
++) {
987 /* Implementation of ARB_indirect_parameters via predicates */
988 if (brw
->draw
.draw_params_count_bo
) {
989 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
991 /* Upload the current draw count from the draw parameters buffer to
994 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
995 brw
->draw
.draw_params_count_bo
,
996 brw
->draw
.draw_params_count_offset
);
997 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
998 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
999 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
1000 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
1003 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
1004 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
1005 MI_PREDICATE_COMBINEOP_SET
|
1006 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1008 OUT_BATCH(GEN7_MI_PREDICATE
|
1009 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
1010 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1014 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
1017 brw_draw_single_prim(ctx
, arrays
, &prims
[i
], i
, xfb_obj
, stream
,
1021 brw_finish_drawing(ctx
);
1022 brw
->predicate
.state
= predicate_state
;
1026 brw_draw_indirect_prims(struct gl_context
*ctx
,
1028 struct gl_buffer_object
*indirect_data
,
1029 GLsizeiptr indirect_offset
,
1030 unsigned draw_count
,
1032 struct gl_buffer_object
*indirect_params
,
1033 GLsizeiptr indirect_params_offset
,
1034 const struct _mesa_index_buffer
*ib
)
1036 struct brw_context
*brw
= brw_context(ctx
);
1037 struct _mesa_prim
*prim
;
1040 prim
= calloc(draw_count
, sizeof(*prim
));
1042 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
1043 (draw_count
> 1) ? "Multi" : "",
1044 ib
? "Elements" : "Arrays",
1045 indirect_params
? "CountARB" : "");
1050 prim
[draw_count
- 1].end
= 1;
1051 for (i
= 0; i
< draw_count
; ++i
, indirect_offset
+= stride
) {
1052 prim
[i
].mode
= mode
;
1053 prim
[i
].indexed
= ib
!= NULL
;
1054 prim
[i
].indirect_offset
= indirect_offset
;
1055 prim
[i
].is_indirect
= 1;
1056 prim
[i
].draw_id
= i
;
1059 if (indirect_params
) {
1060 brw
->draw
.draw_params_count_bo
=
1061 intel_buffer_object(indirect_params
)->buffer
;
1062 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
1063 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
1066 brw_draw_prims(ctx
, prim
, draw_count
,
1075 brw_init_draw_functions(struct dd_function_table
*functions
)
1077 /* Register our drawing function:
1079 functions
->Draw
= brw_draw_prims
;
1080 functions
->DrawIndirect
= brw_draw_indirect_prims
;
1084 brw_draw_init(struct brw_context
*brw
)
1086 /* Keep our list of gl_vertex_array inputs */
1087 _vbo_init_inputs(&brw
->vb
.draw_arrays
);
1089 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1090 brw
->vb
.inputs
[i
].buffer
= -1;
1091 brw
->vb
.nr_buffers
= 0;
1092 brw
->vb
.nr_enabled
= 0;
1096 brw_draw_destroy(struct brw_context
*brw
)
1100 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1101 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1102 brw
->vb
.buffers
[i
].bo
= NULL
;
1104 brw
->vb
.nr_buffers
= 0;
1106 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1107 brw
->vb
.enabled
[i
]->buffer
= -1;
1109 brw
->vb
.nr_enabled
= 0;
1111 brw_bo_unreference(brw
->ib
.bo
);