src/mesa/drivers/dri/i965/brw_draw.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <sys/errno.h>
  29
  30 #include "main/glheader.h"
  31 #include "main/context.h"
  32 #include "main/condrender.h"
  33 #include "main/samplerobj.h"
  34 #include "main/state.h"
  35 #include "main/enums.h"
  36 #include "main/macros.h"
  37 #include "main/transformfeedback.h"
  38 #include "tnl/tnl.h"
  39 #include "vbo/vbo_context.h"
  40 #include "swrast/swrast.h"
  41 #include "swrast_setup/swrast_setup.h"
  42 #include "drivers/common/meta.h"
  43
  44 #include "brw_blorp.h"
  45 #include "brw_draw.h"
  46 #include "brw_defines.h"
  47 #include "brw_context.h"
  48 #include "brw_state.h"
  49 #include "brw_vs.h"
  50
  51 #include "intel_batchbuffer.h"
  52 #include "intel_buffers.h"
  53 #include "intel_fbo.h"
  54 #include "intel_mipmap_tree.h"
  55 #include "intel_buffer_objects.h"
  56
  57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
  58
  59 static const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1] = {
  60    _3DPRIM_POINTLIST,
  61    _3DPRIM_LINELIST,
  62    _3DPRIM_LINELOOP,
  63    _3DPRIM_LINESTRIP,
  64    _3DPRIM_TRILIST,
  65    _3DPRIM_TRISTRIP,
  66    _3DPRIM_TRIFAN,
  67    _3DPRIM_QUADLIST,
  68    _3DPRIM_QUADSTRIP,
  69    _3DPRIM_POLYGON,
  70    _3DPRIM_LINELIST_ADJ,
  71    _3DPRIM_LINESTRIP_ADJ,
  72    _3DPRIM_TRILIST_ADJ,
  73    _3DPRIM_TRISTRIP_ADJ,
  74 };
  75
  76
  77 static const GLenum reduced_prim[GL_POLYGON+1] = {
  78    GL_POINTS,
  79    GL_LINES,
  80    GL_LINES,
  81    GL_LINES,
  82    GL_TRIANGLES,
  83    GL_TRIANGLES,
  84    GL_TRIANGLES,
  85    GL_TRIANGLES,
  86    GL_TRIANGLES,
  87    GL_TRIANGLES
  88 };
  89
  90 uint32_t
  91 get_hw_prim_for_gl_prim(int mode)
  92 {
  93    if (mode >= BRW_PRIM_OFFSET)
  94       return mode - BRW_PRIM_OFFSET;
  95    else
  96       return prim_to_hw_prim[mode];
  97 }
  98
  99
 100 /* When the primitive changes, set a state bit and re-validate.  Not
 101  * the nicest and would rather deal with this by having all the
 102  * programs be immune to the active primitive (ie. cope with all
 103  * possibilities).  That may not be realistic however.
 104  */
 105 static void brw_set_prim(struct brw_context *brw,
 106                          const struct _mesa_prim *prim)
 107 {
 108    struct gl_context *ctx = &brw->ctx;
 109    uint32_t hw_prim = get_hw_prim_for_gl_prim(prim->mode);
 110
 111    DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim->mode));
 112
 113    /* Slight optimization to avoid the GS program when not needed:
 114     */
 115    if (prim->mode == GL_QUAD_STRIP &&
 116        ctx->Light.ShadeModel != GL_FLAT &&
 117        ctx->Polygon.FrontMode == GL_FILL &&
 118        ctx->Polygon.BackMode == GL_FILL)
 119       hw_prim = _3DPRIM_TRISTRIP;
 120
 121    if (prim->mode == GL_QUADS && prim->count == 4 &&
 122        ctx->Light.ShadeModel != GL_FLAT &&
 123        ctx->Polygon.FrontMode == GL_FILL &&
 124        ctx->Polygon.BackMode == GL_FILL) {
 125       hw_prim = _3DPRIM_TRIFAN;
 126    }
 127
 128    if (hw_prim != brw->primitive) {
 129       brw->primitive = hw_prim;
 130       brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
 131
 132       if (reduced_prim[prim->mode] != brw->reduced_primitive) {
 133          brw->reduced_primitive = reduced_prim[prim->mode];
 134          brw->state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE;
 135       }
 136    }
 137 }
 138
 139 static void gen6_set_prim(struct brw_context *brw,
 140                           const struct _mesa_prim *prim)
 141 {
 142    uint32_t hw_prim;
 143
 144    DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim->mode));
 145
 146    hw_prim = get_hw_prim_for_gl_prim(prim->mode);
 147
 148    if (hw_prim != brw->primitive) {
 149       brw->primitive = hw_prim;
 150       brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
 151    }
 152 }
 153
 154
 155 /**
 156  * The hardware is capable of removing dangling vertices on its own; however,
 157  * prior to Gen6, we sometimes convert quads into trifans (and quad strips
 158  * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
 159  * This function manually trims dangling vertices from a draw call involving
 160  * quads so that those dangling vertices won't get drawn when we convert to
 161  * trifans/tristrips.
 162  */
 163 static GLuint trim(GLenum prim, GLuint length)
 164 {
 165    if (prim == GL_QUAD_STRIP)
 166       return length > 3 ? (length - length % 2) : 0;
 167    else if (prim == GL_QUADS)
 168       return length - length % 4;
 169    else
 170       return length;
 171 }
 172
 173
 174 static void brw_emit_prim(struct brw_context *brw,
 175                           const struct _mesa_prim *prim,
 176                           uint32_t hw_prim)
 177 {
 178    int verts_per_instance;
 179    int vertex_access_type;
 180    int indirect_flag;
 181
 182    DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
 183        prim->start, prim->count);
 184
 185    int start_vertex_location = prim->start;
 186    int base_vertex_location = prim->basevertex;
 187
 188    if (prim->indexed) {
 189       vertex_access_type = brw->gen >= 7 ?
 190          GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
 191          GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
 192       start_vertex_location += brw->ib.start_vertex_offset;
 193       base_vertex_location += brw->vb.start_vertex_bias;
 194    } else {
 195       vertex_access_type = brw->gen >= 7 ?
 196          GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL :
 197          GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
 198       start_vertex_location += brw->vb.start_vertex_bias;
 199    }
 200
 201    /* We only need to trim the primitive count on pre-Gen6. */
 202    if (brw->gen < 6)
 203       verts_per_instance = trim(prim->mode, prim->count);
 204    else
 205       verts_per_instance = prim->count;
 206
 207    /* If nothing to emit, just return. */
 208    if (verts_per_instance == 0 && !prim->is_indirect)
 209       return;
 210
 211    /* If we're set to always flush, do it before and after the primitive emit.
 212     * We want to catch both missed flushes that hurt instruction/state cache
 213     * and missed flushes of the render cache as it heads to other parts of
 214     * the besides the draw code.
 215     */
 216    if (brw->always_flush_cache) {
 217       intel_batchbuffer_emit_mi_flush(brw);
 218    }
 219
 220    /* If indirect, emit a bunch of loads from the indirect BO. */
 221    if (prim->is_indirect) {
 222       struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
 223       drm_intel_bo *bo = intel_bufferobj_buffer(brw,
 224             intel_buffer_object(indirect_buffer),
 225             prim->indirect_offset, 5 * sizeof(GLuint));
 226
 227       indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
 228
 229       brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
 230                             I915_GEM_DOMAIN_VERTEX, 0,
 231                             prim->indirect_offset + 0);
 232       brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
 233                             I915_GEM_DOMAIN_VERTEX, 0,
 234                             prim->indirect_offset + 4);
 235
 236       brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
 237                             I915_GEM_DOMAIN_VERTEX, 0,
 238                             prim->indirect_offset + 8);
 239       if (prim->indexed) {
 240          brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
 241                                I915_GEM_DOMAIN_VERTEX, 0,
 242                                prim->indirect_offset + 12);
 243          brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
 244                                I915_GEM_DOMAIN_VERTEX, 0,
 245                                prim->indirect_offset + 16);
 246       } else {
 247          brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
 248                                I915_GEM_DOMAIN_VERTEX, 0,
 249                                prim->indirect_offset + 12);
 250          BEGIN_BATCH(3);
 251          OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 252          OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
 253          OUT_BATCH(0);
 254          ADVANCE_BATCH();
 255       }
 256    }
 257    else {
 258       indirect_flag = 0;
 259    }
 260
 261
 262    if (brw->gen >= 7) {
 263       BEGIN_BATCH(7);
 264       OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2) | indirect_flag);
 265       OUT_BATCH(hw_prim | vertex_access_type);
 266    } else {
 267       BEGIN_BATCH(6);
 268       OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
 269                 hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
 270                 vertex_access_type);
 271    }
 272    OUT_BATCH(verts_per_instance);
 273    OUT_BATCH(start_vertex_location);
 274    OUT_BATCH(prim->num_instances);
 275    OUT_BATCH(prim->base_instance);
 276    OUT_BATCH(base_vertex_location);
 277    ADVANCE_BATCH();
 278
 279    if (brw->always_flush_cache) {
 280       intel_batchbuffer_emit_mi_flush(brw);
 281    }
 282 }
 283
 284
 285 static void brw_merge_inputs( struct brw_context *brw,
 286                        const struct gl_client_array *arrays[])
 287 {
 288    const struct gl_context *ctx = &brw->ctx;
 289    GLuint i;
 290
 291    for (i = 0; i < brw->vb.nr_buffers; i++) {
 292       drm_intel_bo_unreference(brw->vb.buffers[i].bo);
 293       brw->vb.buffers[i].bo = NULL;
 294    }
 295    brw->vb.nr_buffers = 0;
 296
 297    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 298       brw->vb.inputs[i].buffer = -1;
 299       brw->vb.inputs[i].glarray = arrays[i];
 300    }
 301
 302    if (brw->gen < 8 && !brw->is_haswell) {
 303       struct gl_program *vp = &ctx->VertexProgram._Current->Base;
 304       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
 305        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
 306        */
 307       for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 308          if (!(vp->InputsRead & BITFIELD64_BIT(i)))
 309             continue;
 310
 311          uint8_t wa_flags = 0;
 312
 313          switch (brw->vb.inputs[i].glarray->Type) {
 314
 315          case GL_FIXED:
 316             wa_flags = brw->vb.inputs[i].glarray->Size;
 317             break;
 318
 319          case GL_INT_2_10_10_10_REV:
 320             wa_flags |= BRW_ATTRIB_WA_SIGN;
 321             /* fallthough */
 322
 323          case GL_UNSIGNED_INT_2_10_10_10_REV:
 324             if (brw->vb.inputs[i].glarray->Format == GL_BGRA)
 325                wa_flags |= BRW_ATTRIB_WA_BGRA;
 326
 327             if (brw->vb.inputs[i].glarray->Normalized)
 328                wa_flags |= BRW_ATTRIB_WA_NORMALIZE;
 329             else if (!brw->vb.inputs[i].glarray->Integer)
 330                wa_flags |= BRW_ATTRIB_WA_SCALE;
 331
 332             break;
 333          }
 334
 335          if (brw->vb.attrib_wa_flags[i] != wa_flags) {
 336             brw->vb.attrib_wa_flags[i] = wa_flags;
 337             brw->state.dirty.brw |= BRW_NEW_VS_ATTRIB_WORKAROUNDS;
 338          }
 339       }
 340    }
 341 }
 342
 343 /**
 344  * \brief Call this after drawing to mark which buffers need resolving
 345  *
 346  * If the depth buffer was written to and if it has an accompanying HiZ
 347  * buffer, then mark that it needs a depth resolve.
 348  *
 349  * If the color buffer is a multisample window system buffer, then
 350  * mark that it needs a downsample.
 351  *
 352  * Also mark any render targets which will be textured as needing a render
 353  * cache flush.
 354  */
 355 static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
 356 {
 357    struct gl_context *ctx = &brw->ctx;
 358    struct gl_framebuffer *fb = ctx->DrawBuffer;
 359
 360    struct intel_renderbuffer *front_irb = NULL;
 361    struct intel_renderbuffer *back_irb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
 362    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 363    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 364    struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 365
 366    if (brw_is_front_buffer_drawing(fb))
 367       front_irb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
 368
 369    if (front_irb)
 370       front_irb->need_downsample = true;
 371    if (back_irb)
 372       back_irb->need_downsample = true;
 373    if (depth_irb && ctx->Depth.Mask) {
 374       intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
 375       brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
 376    }
 377
 378    if (ctx->Extensions.ARB_stencil_texturing &&
 379        stencil_irb && ctx->Stencil._WriteEnabled) {
 380       brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
 381    }
 382
 383    for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
 384       struct intel_renderbuffer *irb =
 385          intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 386
 387       if (irb)
 388          brw_render_cache_set_add_bo(brw, irb->mt->bo);
 389    }
 390 }
 391
 392 /* May fail if out of video memory for texture or vbo upload, or on
 393  * fallback conditions.
 394  */
 395 static void brw_try_draw_prims( struct gl_context *ctx,
 396                                      const struct gl_client_array *arrays[],
 397                                      const struct _mesa_prim *prims,
 398                                      GLuint nr_prims,
 399                                      const struct _mesa_index_buffer *ib,
 400                                      GLuint min_index,
 401                                      GLuint max_index,
 402                                      struct gl_buffer_object *indirect)
 403 {
 404    struct brw_context *brw = brw_context(ctx);
 405    GLuint i;
 406    bool fail_next = false;
 407
 408    if (ctx->NewState)
 409       _mesa_update_state( ctx );
 410
 411    /* Find the highest sampler unit used by each shader program.  A bit-count
 412     * won't work since ARB programs use the texture unit number as the sampler
 413     * index.
 414     */
 415    brw->wm.base.sampler_count =
 416       _mesa_fls(ctx->FragmentProgram._Current->Base.SamplersUsed);
 417    brw->gs.base.sampler_count = ctx->GeometryProgram._Current ?
 418       _mesa_fls(ctx->GeometryProgram._Current->Base.SamplersUsed) : 0;
 419    brw->vs.base.sampler_count =
 420       _mesa_fls(ctx->VertexProgram._Current->Base.SamplersUsed);
 421
 422    /* We have to validate the textures *before* checking for fallbacks;
 423     * otherwise, the software fallback won't be able to rely on the
 424     * texture state, the firstLevel and lastLevel fields won't be
 425     * set in the intel texture object (they'll both be 0), and the
 426     * software fallback will segfault if it attempts to access any
 427     * texture level other than level 0.
 428     */
 429    brw_validate_textures( brw );
 430
 431    intel_prepare_render(brw);
 432
 433    /* This workaround has to happen outside of brw_upload_render_state()
 434     * because it may flush the batchbuffer for a blit, affecting the state
 435     * flags.
 436     */
 437    brw_workaround_depthstencil_alignment(brw, 0);
 438
 439    /* Bind all inputs, derive varying and size information:
 440     */
 441    brw_merge_inputs( brw, arrays );
 442
 443    brw->ib.ib = ib;
 444    brw->state.dirty.brw |= BRW_NEW_INDICES;
 445
 446    brw->vb.min_index = min_index;
 447    brw->vb.max_index = max_index;
 448    brw->state.dirty.brw |= BRW_NEW_VERTICES;
 449
 450    for (i = 0; i < nr_prims; i++) {
 451       int estimated_max_prim_size;
 452       const int sampler_state_size = 16;
 453
 454       estimated_max_prim_size = 512; /* batchbuffer commands */
 455       estimated_max_prim_size += BRW_MAX_TEX_UNIT *
 456          (sampler_state_size + sizeof(struct gen5_sampler_default_color));
 457       estimated_max_prim_size += 1024; /* gen6 VS push constants */
 458       estimated_max_prim_size += 1024; /* gen6 WM push constants */
 459       estimated_max_prim_size += 512; /* misc. pad */
 460
 461       /* Flush the batch if it's approaching full, so that we don't wrap while
 462        * we've got validated state that needs to be in the same batch as the
 463        * primitives.
 464        */
 465       intel_batchbuffer_require_space(brw, estimated_max_prim_size, RENDER_RING);
 466       intel_batchbuffer_save_state(brw);
 467
 468       if (brw->num_instances != prims[i].num_instances ||
 469           brw->basevertex != prims[i].basevertex) {
 470          brw->num_instances = prims[i].num_instances;
 471          brw->basevertex = prims[i].basevertex;
 472          if (i > 0) { /* For i == 0 we just did this before the loop */
 473             brw->state.dirty.brw |= BRW_NEW_VERTICES;
 474             brw_merge_inputs(brw, arrays);
 475          }
 476       }
 477
 478       brw->draw.gl_basevertex =
 479          prims[i].indexed ? prims[i].basevertex : prims[i].start;
 480
 481       drm_intel_bo_unreference(brw->draw.draw_params_bo);
 482
 483       if (prims[i].is_indirect) {
 484          /* Point draw_params_bo at the indirect buffer. */
 485          brw->draw.draw_params_bo =
 486             intel_buffer_object(ctx->DrawIndirectBuffer)->buffer;
 487          drm_intel_bo_reference(brw->draw.draw_params_bo);
 488          brw->draw.draw_params_offset =
 489             prims[i].indirect_offset + (prims[i].indexed ? 12 : 8);
 490       } else {
 491          /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
 492           * has to upload gl_BaseVertex and such if they're needed.
 493           */
 494          brw->draw.draw_params_bo = NULL;
 495          brw->draw.draw_params_offset = 0;
 496       }
 497
 498       if (brw->gen < 6)
 499          brw_set_prim(brw, &prims[i]);
 500       else
 501          gen6_set_prim(brw, &prims[i]);
 502
 503 retry:
 504
 505       /* Note that before the loop, brw->state.dirty.brw was set to != 0, and
 506        * that the state updated in the loop outside of this block is that in
 507        * *_set_prim or intel_batchbuffer_flush(), which only impacts
 508        * brw->state.dirty.brw.
 509        */
 510       if (brw->state.dirty.brw) {
 511          brw->no_batch_wrap = true;
 512          brw_upload_render_state(brw);
 513       }
 514
 515       brw_emit_prim(brw, &prims[i], brw->primitive);
 516
 517       brw->no_batch_wrap = false;
 518
 519       if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 520          if (!fail_next) {
 521             intel_batchbuffer_reset_to_saved(brw);
 522             intel_batchbuffer_flush(brw);
 523             fail_next = true;
 524             goto retry;
 525          } else {
 526             int ret = intel_batchbuffer_flush(brw);
 527             WARN_ONCE(ret == -ENOSPC,
 528                       "i965: Single primitive emit exceeded "
 529                       "available aperture space\n");
 530          }
 531       }
 532
 533       /* Now that we know we haven't run out of aperture space, we can safely
 534        * reset the dirty bits.
 535        */
 536       if (brw->state.dirty.brw)
 537          brw_clear_dirty_bits(brw);
 538    }
 539
 540    if (brw->always_flush_batch)
 541       intel_batchbuffer_flush(brw);
 542
 543    brw_state_cache_check_size(brw);
 544    brw_postdraw_set_buffers_need_resolve(brw);
 545
 546    return;
 547 }
 548
 549 void brw_draw_prims( struct gl_context *ctx,
 550                      const struct _mesa_prim *prims,
 551                      GLuint nr_prims,
 552                      const struct _mesa_index_buffer *ib,
 553                      GLboolean index_bounds_valid,
 554                      GLuint min_index,
 555                      GLuint max_index,
 556                      struct gl_transform_feedback_object *unused_tfb_object,
 557                      struct gl_buffer_object *indirect )
 558 {
 559    struct brw_context *brw = brw_context(ctx);
 560    const struct gl_client_array **arrays = ctx->Array._DrawArrays;
 561
 562    assert(unused_tfb_object == NULL);
 563
 564    if (ctx->Query.CondRenderQuery) {
 565       perf_debug("Conditional rendering is implemented in software and may "
 566                  "stall.  This should be fixed in the driver.\n");
 567    }
 568
 569    if (!_mesa_check_conditional_render(ctx))
 570       return;
 571
 572    /* Handle primitive restart if needed */
 573    if (brw_handle_primitive_restart(ctx, prims, nr_prims, ib, indirect)) {
 574       /* The draw was handled, so we can exit now */
 575       return;
 576    }
 577
 578    /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
 579     * won't support all the extensions we support.
 580     */
 581    if (ctx->RenderMode != GL_RENDER) {
 582       perf_debug("%s render mode not supported in hardware\n",
 583                  _mesa_lookup_enum_by_nr(ctx->RenderMode));
 584       _swsetup_Wakeup(ctx);
 585       _tnl_wakeup(ctx);
 586       _tnl_draw_prims(ctx, prims, nr_prims, ib,
 587                       index_bounds_valid, min_index, max_index, NULL, NULL);
 588       return;
 589    }
 590
 591    /* If we're going to have to upload any of the user's vertex arrays, then
 592     * get the minimum and maximum of their index buffer so we know what range
 593     * to upload.
 594     */
 595    if (!index_bounds_valid && !vbo_all_varyings_in_vbos(arrays)) {
 596       perf_debug("Scanning index buffer to compute index buffer bounds.  "
 597                  "Use glDrawRangeElements() to avoid this.\n");
 598       vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index, nr_prims);
 599    }
 600
 601    /* Try drawing with the hardware, but don't do anything else if we can't
 602     * manage it.  swrast doesn't support our featureset, so we can't fall back
 603     * to it.
 604     */
 605    brw_try_draw_prims(ctx, arrays, prims, nr_prims, ib, min_index, max_index, indirect);
 606 }
 607
 608 void brw_draw_init( struct brw_context *brw )
 609 {
 610    struct gl_context *ctx = &brw->ctx;
 611    struct vbo_context *vbo = vbo_context(ctx);
 612    int i;
 613
 614    /* Register our drawing function:
 615     */
 616    vbo->draw_prims = brw_draw_prims;
 617
 618    for (i = 0; i < VERT_ATTRIB_MAX; i++)
 619       brw->vb.inputs[i].buffer = -1;
 620    brw->vb.nr_buffers = 0;
 621    brw->vb.nr_enabled = 0;
 622 }
 623
 624 void brw_draw_destroy( struct brw_context *brw )
 625 {
 626    int i;
 627
 628    for (i = 0; i < brw->vb.nr_buffers; i++) {
 629       drm_intel_bo_unreference(brw->vb.buffers[i].bo);
 630       brw->vb.buffers[i].bo = NULL;
 631    }
 632    brw->vb.nr_buffers = 0;
 633
 634    for (i = 0; i < brw->vb.nr_enabled; i++) {
 635       brw->vb.enabled[i]->buffer = -1;
 636    }
 637    brw->vb.nr_enabled = 0;
 638
 639    drm_intel_bo_unreference(brw->ib.bo);
 640    brw->ib.bo = NULL;
 641 }