src/mesa/drivers/dri/i965/brw_draw.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <sys/errno.h>
  29
  30 #include "main/glheader.h"
  31 #include "main/context.h"
  32 #include "main/condrender.h"
  33 #include "main/samplerobj.h"
  34 #include "main/state.h"
  35 #include "main/enums.h"
  36 #include "main/macros.h"
  37 #include "main/transformfeedback.h"
  38 #include "tnl/tnl.h"
  39 #include "vbo/vbo_context.h"
  40 #include "swrast/swrast.h"
  41 #include "swrast_setup/swrast_setup.h"
  42 #include "drivers/common/meta.h"
  43
  44 #include "brw_blorp.h"
  45 #include "brw_draw.h"
  46 #include "brw_defines.h"
  47 #include "brw_context.h"
  48 #include "brw_state.h"
  49 #include "brw_vs.h"
  50
  51 #include "intel_batchbuffer.h"
  52 #include "intel_buffers.h"
  53 #include "intel_fbo.h"
  54 #include "intel_mipmap_tree.h"
  55 #include "intel_buffer_objects.h"
  56
  57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
  58
  59 static const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1] = {
  60    _3DPRIM_POINTLIST,
  61    _3DPRIM_LINELIST,
  62    _3DPRIM_LINELOOP,
  63    _3DPRIM_LINESTRIP,
  64    _3DPRIM_TRILIST,
  65    _3DPRIM_TRISTRIP,
  66    _3DPRIM_TRIFAN,
  67    _3DPRIM_QUADLIST,
  68    _3DPRIM_QUADSTRIP,
  69    _3DPRIM_POLYGON,
  70    _3DPRIM_LINELIST_ADJ,
  71    _3DPRIM_LINESTRIP_ADJ,
  72    _3DPRIM_TRILIST_ADJ,
  73    _3DPRIM_TRISTRIP_ADJ,
  74 };
  75
  76
  77 static const GLenum reduced_prim[GL_POLYGON+1] = {
  78    GL_POINTS,
  79    GL_LINES,
  80    GL_LINES,
  81    GL_LINES,
  82    GL_TRIANGLES,
  83    GL_TRIANGLES,
  84    GL_TRIANGLES,
  85    GL_TRIANGLES,
  86    GL_TRIANGLES,
  87    GL_TRIANGLES
  88 };
  89
  90 uint32_t
  91 get_hw_prim_for_gl_prim(int mode)
  92 {
  93    if (mode >= BRW_PRIM_OFFSET)
  94       return mode - BRW_PRIM_OFFSET;
  95    else {
  96       assert(mode < ARRAY_SIZE(prim_to_hw_prim));
  97       return prim_to_hw_prim[mode];
  98    }
  99 }
 100
 101
 102 /* When the primitive changes, set a state bit and re-validate.  Not
 103  * the nicest and would rather deal with this by having all the
 104  * programs be immune to the active primitive (ie. cope with all
 105  * possibilities).  That may not be realistic however.
 106  */
 107 static void brw_set_prim(struct brw_context *brw,
 108                          const struct _mesa_prim *prim)
 109 {
 110    struct gl_context *ctx = &brw->ctx;
 111    uint32_t hw_prim = get_hw_prim_for_gl_prim(prim->mode);
 112
 113    DBG("PRIM: %s\n", _mesa_enum_to_string(prim->mode));
 114
 115    /* Slight optimization to avoid the GS program when not needed:
 116     */
 117    if (prim->mode == GL_QUAD_STRIP &&
 118        ctx->Light.ShadeModel != GL_FLAT &&
 119        ctx->Polygon.FrontMode == GL_FILL &&
 120        ctx->Polygon.BackMode == GL_FILL)
 121       hw_prim = _3DPRIM_TRISTRIP;
 122
 123    if (prim->mode == GL_QUADS && prim->count == 4 &&
 124        ctx->Light.ShadeModel != GL_FLAT &&
 125        ctx->Polygon.FrontMode == GL_FILL &&
 126        ctx->Polygon.BackMode == GL_FILL) {
 127       hw_prim = _3DPRIM_TRIFAN;
 128    }
 129
 130    if (hw_prim != brw->primitive) {
 131       brw->primitive = hw_prim;
 132       brw->ctx.NewDriverState |= BRW_NEW_PRIMITIVE;
 133
 134       if (reduced_prim[prim->mode] != brw->reduced_primitive) {
 135          brw->reduced_primitive = reduced_prim[prim->mode];
 136          brw->ctx.NewDriverState |= BRW_NEW_REDUCED_PRIMITIVE;
 137       }
 138    }
 139 }
 140
 141 static void gen6_set_prim(struct brw_context *brw,
 142                           const struct _mesa_prim *prim)
 143 {
 144    uint32_t hw_prim;
 145
 146    DBG("PRIM: %s\n", _mesa_enum_to_string(prim->mode));
 147
 148    hw_prim = get_hw_prim_for_gl_prim(prim->mode);
 149
 150    if (hw_prim != brw->primitive) {
 151       brw->primitive = hw_prim;
 152       brw->ctx.NewDriverState |= BRW_NEW_PRIMITIVE;
 153    }
 154 }
 155
 156
 157 /**
 158  * The hardware is capable of removing dangling vertices on its own; however,
 159  * prior to Gen6, we sometimes convert quads into trifans (and quad strips
 160  * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
 161  * This function manually trims dangling vertices from a draw call involving
 162  * quads so that those dangling vertices won't get drawn when we convert to
 163  * trifans/tristrips.
 164  */
 165 static GLuint trim(GLenum prim, GLuint length)
 166 {
 167    if (prim == GL_QUAD_STRIP)
 168       return length > 3 ? (length - length % 2) : 0;
 169    else if (prim == GL_QUADS)
 170       return length - length % 4;
 171    else
 172       return length;
 173 }
 174
 175
 176 static void brw_emit_prim(struct brw_context *brw,
 177                           const struct _mesa_prim *prim,
 178                           uint32_t hw_prim)
 179 {
 180    int verts_per_instance;
 181    int vertex_access_type;
 182    int indirect_flag;
 183    int predicate_enable;
 184
 185    DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim->mode),
 186        prim->start, prim->count);
 187
 188    int start_vertex_location = prim->start;
 189    int base_vertex_location = prim->basevertex;
 190
 191    if (prim->indexed) {
 192       vertex_access_type = brw->gen >= 7 ?
 193          GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM :
 194          GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
 195       start_vertex_location += brw->ib.start_vertex_offset;
 196       base_vertex_location += brw->vb.start_vertex_bias;
 197    } else {
 198       vertex_access_type = brw->gen >= 7 ?
 199          GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL :
 200          GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
 201       start_vertex_location += brw->vb.start_vertex_bias;
 202    }
 203
 204    /* We only need to trim the primitive count on pre-Gen6. */
 205    if (brw->gen < 6)
 206       verts_per_instance = trim(prim->mode, prim->count);
 207    else
 208       verts_per_instance = prim->count;
 209
 210    /* If nothing to emit, just return. */
 211    if (verts_per_instance == 0 && !prim->is_indirect)
 212       return;
 213
 214    /* If we're set to always flush, do it before and after the primitive emit.
 215     * We want to catch both missed flushes that hurt instruction/state cache
 216     * and missed flushes of the render cache as it heads to other parts of
 217     * the besides the draw code.
 218     */
 219    if (brw->always_flush_cache) {
 220       brw_emit_mi_flush(brw);
 221    }
 222
 223    /* If indirect, emit a bunch of loads from the indirect BO. */
 224    if (prim->is_indirect) {
 225       struct gl_buffer_object *indirect_buffer = brw->ctx.DrawIndirectBuffer;
 226       drm_intel_bo *bo = intel_bufferobj_buffer(brw,
 227             intel_buffer_object(indirect_buffer),
 228             prim->indirect_offset, 5 * sizeof(GLuint));
 229
 230       indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
 231
 232       brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
 233                             I915_GEM_DOMAIN_VERTEX, 0,
 234                             prim->indirect_offset + 0);
 235       brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
 236                             I915_GEM_DOMAIN_VERTEX, 0,
 237                             prim->indirect_offset + 4);
 238
 239       brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
 240                             I915_GEM_DOMAIN_VERTEX, 0,
 241                             prim->indirect_offset + 8);
 242       if (prim->indexed) {
 243          brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
 244                                I915_GEM_DOMAIN_VERTEX, 0,
 245                                prim->indirect_offset + 12);
 246          brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
 247                                I915_GEM_DOMAIN_VERTEX, 0,
 248                                prim->indirect_offset + 16);
 249       } else {
 250          brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
 251                                I915_GEM_DOMAIN_VERTEX, 0,
 252                                prim->indirect_offset + 12);
 253          BEGIN_BATCH(3);
 254          OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 255          OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
 256          OUT_BATCH(0);
 257          ADVANCE_BATCH();
 258       }
 259    }
 260    else {
 261       indirect_flag = 0;
 262    }
 263
 264    BEGIN_BATCH(brw->gen >= 7 ? 7 : 6);
 265
 266    if (brw->gen >= 7) {
 267       if (brw->predicate.state == BRW_PREDICATE_STATE_USE_BIT)
 268          predicate_enable = GEN7_3DPRIM_PREDICATE_ENABLE;
 269       else
 270          predicate_enable = 0;
 271
 272       OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2) | indirect_flag | predicate_enable);
 273       OUT_BATCH(hw_prim | vertex_access_type);
 274    } else {
 275       OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
 276                 hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
 277                 vertex_access_type);
 278    }
 279    OUT_BATCH(verts_per_instance);
 280    OUT_BATCH(start_vertex_location);
 281    OUT_BATCH(prim->num_instances);
 282    OUT_BATCH(prim->base_instance);
 283    OUT_BATCH(base_vertex_location);
 284    ADVANCE_BATCH();
 285
 286    if (brw->always_flush_cache) {
 287       brw_emit_mi_flush(brw);
 288    }
 289 }
 290
 291
 292 static void brw_merge_inputs( struct brw_context *brw,
 293                        const struct gl_client_array *arrays[])
 294 {
 295    const struct gl_context *ctx = &brw->ctx;
 296    GLuint i;
 297
 298    for (i = 0; i < brw->vb.nr_buffers; i++) {
 299       drm_intel_bo_unreference(brw->vb.buffers[i].bo);
 300       brw->vb.buffers[i].bo = NULL;
 301    }
 302    brw->vb.nr_buffers = 0;
 303
 304    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 305       brw->vb.inputs[i].buffer = -1;
 306       brw->vb.inputs[i].glarray = arrays[i];
 307    }
 308
 309    if (brw->gen < 8 && !brw->is_haswell) {
 310       struct gl_program *vp = &ctx->VertexProgram._Current->Base;
 311       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
 312        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
 313        */
 314       for (i = 0; i < VERT_ATTRIB_MAX; i++) {
 315          if (!(vp->InputsRead & BITFIELD64_BIT(i)))
 316             continue;
 317
 318          uint8_t wa_flags = 0;
 319
 320          switch (brw->vb.inputs[i].glarray->Type) {
 321
 322          case GL_FIXED:
 323             wa_flags = brw->vb.inputs[i].glarray->Size;
 324             break;
 325
 326          case GL_INT_2_10_10_10_REV:
 327             wa_flags |= BRW_ATTRIB_WA_SIGN;
 328             /* fallthough */
 329
 330          case GL_UNSIGNED_INT_2_10_10_10_REV:
 331             if (brw->vb.inputs[i].glarray->Format == GL_BGRA)
 332                wa_flags |= BRW_ATTRIB_WA_BGRA;
 333
 334             if (brw->vb.inputs[i].glarray->Normalized)
 335                wa_flags |= BRW_ATTRIB_WA_NORMALIZE;
 336             else if (!brw->vb.inputs[i].glarray->Integer)
 337                wa_flags |= BRW_ATTRIB_WA_SCALE;
 338
 339             break;
 340          }
 341
 342          if (brw->vb.attrib_wa_flags[i] != wa_flags) {
 343             brw->vb.attrib_wa_flags[i] = wa_flags;
 344             brw->ctx.NewDriverState |= BRW_NEW_VS_ATTRIB_WORKAROUNDS;
 345          }
 346       }
 347    }
 348 }
 349
 350 /**
 351  * \brief Call this after drawing to mark which buffers need resolving
 352  *
 353  * If the depth buffer was written to and if it has an accompanying HiZ
 354  * buffer, then mark that it needs a depth resolve.
 355  *
 356  * If the color buffer is a multisample window system buffer, then
 357  * mark that it needs a downsample.
 358  *
 359  * Also mark any render targets which will be textured as needing a render
 360  * cache flush.
 361  */
 362 static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
 363 {
 364    struct gl_context *ctx = &brw->ctx;
 365    struct gl_framebuffer *fb = ctx->DrawBuffer;
 366
 367    struct intel_renderbuffer *front_irb = NULL;
 368    struct intel_renderbuffer *back_irb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
 369    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 370    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 371    struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 372
 373    if (brw_is_front_buffer_drawing(fb))
 374       front_irb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
 375
 376    if (front_irb)
 377       front_irb->need_downsample = true;
 378    if (back_irb)
 379       back_irb->need_downsample = true;
 380    if (depth_irb && ctx->Depth.Mask) {
 381       intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
 382       brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
 383    }
 384
 385    if (ctx->Extensions.ARB_stencil_texturing &&
 386        stencil_irb && ctx->Stencil._WriteEnabled) {
 387       brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
 388    }
 389
 390    for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
 391       struct intel_renderbuffer *irb =
 392          intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 393
 394       if (irb)
 395          brw_render_cache_set_add_bo(brw, irb->mt->bo);
 396    }
 397 }
 398
 399 /* May fail if out of video memory for texture or vbo upload, or on
 400  * fallback conditions.
 401  */
 402 static void brw_try_draw_prims( struct gl_context *ctx,
 403                                      const struct gl_client_array *arrays[],
 404                                      const struct _mesa_prim *prims,
 405                                      GLuint nr_prims,
 406                                      const struct _mesa_index_buffer *ib,
 407                                      GLuint min_index,
 408                                      GLuint max_index,
 409                                      struct gl_buffer_object *indirect)
 410 {
 411    struct brw_context *brw = brw_context(ctx);
 412    GLuint i;
 413    bool fail_next = false;
 414
 415    if (ctx->NewState)
 416       _mesa_update_state( ctx );
 417
 418    /* Find the highest sampler unit used by each shader program.  A bit-count
 419     * won't work since ARB programs use the texture unit number as the sampler
 420     * index.
 421     */
 422    brw->wm.base.sampler_count =
 423       _mesa_fls(ctx->FragmentProgram._Current->Base.SamplersUsed);
 424    brw->gs.base.sampler_count = ctx->GeometryProgram._Current ?
 425       _mesa_fls(ctx->GeometryProgram._Current->Base.SamplersUsed) : 0;
 426    brw->vs.base.sampler_count =
 427       _mesa_fls(ctx->VertexProgram._Current->Base.SamplersUsed);
 428
 429    /* We have to validate the textures *before* checking for fallbacks;
 430     * otherwise, the software fallback won't be able to rely on the
 431     * texture state, the firstLevel and lastLevel fields won't be
 432     * set in the intel texture object (they'll both be 0), and the
 433     * software fallback will segfault if it attempts to access any
 434     * texture level other than level 0.
 435     */
 436    brw_validate_textures( brw );
 437
 438    intel_prepare_render(brw);
 439
 440    /* This workaround has to happen outside of brw_upload_render_state()
 441     * because it may flush the batchbuffer for a blit, affecting the state
 442     * flags.
 443     */
 444    brw_workaround_depthstencil_alignment(brw, 0);
 445
 446    /* Bind all inputs, derive varying and size information:
 447     */
 448    brw_merge_inputs( brw, arrays );
 449
 450    brw->ib.ib = ib;
 451    brw->ctx.NewDriverState |= BRW_NEW_INDICES;
 452
 453    brw->vb.min_index = min_index;
 454    brw->vb.max_index = max_index;
 455    brw->ctx.NewDriverState |= BRW_NEW_VERTICES;
 456
 457    for (i = 0; i < nr_prims; i++) {
 458       int estimated_max_prim_size;
 459       const int sampler_state_size = 16;
 460
 461       estimated_max_prim_size = 512; /* batchbuffer commands */
 462       estimated_max_prim_size += BRW_MAX_TEX_UNIT *
 463          (sampler_state_size + sizeof(struct gen5_sampler_default_color));
 464       estimated_max_prim_size += 1024; /* gen6 VS push constants */
 465       estimated_max_prim_size += 1024; /* gen6 WM push constants */
 466       estimated_max_prim_size += 512; /* misc. pad */
 467
 468       /* Flush the batch if it's approaching full, so that we don't wrap while
 469        * we've got validated state that needs to be in the same batch as the
 470        * primitives.
 471        */
 472       intel_batchbuffer_require_space(brw, estimated_max_prim_size, RENDER_RING);
 473       intel_batchbuffer_save_state(brw);
 474
 475       if (brw->num_instances != prims[i].num_instances ||
 476           brw->basevertex != prims[i].basevertex) {
 477          brw->num_instances = prims[i].num_instances;
 478          brw->basevertex = prims[i].basevertex;
 479          if (i > 0) { /* For i == 0 we just did this before the loop */
 480             brw->ctx.NewDriverState |= BRW_NEW_VERTICES;
 481             brw_merge_inputs(brw, arrays);
 482          }
 483       }
 484
 485       brw->draw.gl_basevertex =
 486          prims[i].indexed ? prims[i].basevertex : prims[i].start;
 487
 488       drm_intel_bo_unreference(brw->draw.draw_params_bo);
 489
 490       if (prims[i].is_indirect) {
 491          /* Point draw_params_bo at the indirect buffer. */
 492          brw->draw.draw_params_bo =
 493             intel_buffer_object(ctx->DrawIndirectBuffer)->buffer;
 494          drm_intel_bo_reference(brw->draw.draw_params_bo);
 495          brw->draw.draw_params_offset =
 496             prims[i].indirect_offset + (prims[i].indexed ? 12 : 8);
 497       } else {
 498          /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
 499           * has to upload gl_BaseVertex and such if they're needed.
 500           */
 501          brw->draw.draw_params_bo = NULL;
 502          brw->draw.draw_params_offset = 0;
 503       }
 504
 505       if (brw->gen < 6)
 506          brw_set_prim(brw, &prims[i]);
 507       else
 508          gen6_set_prim(brw, &prims[i]);
 509
 510 retry:
 511
 512       /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
 513        * that the state updated in the loop outside of this block is that in
 514        * *_set_prim or intel_batchbuffer_flush(), which only impacts
 515        * brw->ctx.NewDriverState.
 516        */
 517       if (brw->ctx.NewDriverState) {
 518          brw->no_batch_wrap = true;
 519          brw_upload_render_state(brw);
 520       }
 521
 522       brw_emit_prim(brw, &prims[i], brw->primitive);
 523
 524       brw->no_batch_wrap = false;
 525
 526       if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
 527          if (!fail_next) {
 528             intel_batchbuffer_reset_to_saved(brw);
 529             intel_batchbuffer_flush(brw);
 530             fail_next = true;
 531             goto retry;
 532          } else {
 533             int ret = intel_batchbuffer_flush(brw);
 534             WARN_ONCE(ret == -ENOSPC,
 535                       "i965: Single primitive emit exceeded "
 536                       "available aperture space\n");
 537          }
 538       }
 539
 540       /* Now that we know we haven't run out of aperture space, we can safely
 541        * reset the dirty bits.
 542        */
 543       if (brw->ctx.NewDriverState)
 544          brw_render_state_finished(brw);
 545    }
 546
 547    if (brw->always_flush_batch)
 548       intel_batchbuffer_flush(brw);
 549
 550    brw_state_cache_check_size(brw);
 551    brw_postdraw_set_buffers_need_resolve(brw);
 552
 553    return;
 554 }
 555
 556 void brw_draw_prims( struct gl_context *ctx,
 557                      const struct _mesa_prim *prims,
 558                      GLuint nr_prims,
 559                      const struct _mesa_index_buffer *ib,
 560                      GLboolean index_bounds_valid,
 561                      GLuint min_index,
 562                      GLuint max_index,
 563                      struct gl_transform_feedback_object *unused_tfb_object,
 564                      struct gl_buffer_object *indirect )
 565 {
 566    struct brw_context *brw = brw_context(ctx);
 567    const struct gl_client_array **arrays = ctx->Array._DrawArrays;
 568
 569    assert(unused_tfb_object == NULL);
 570
 571    if (!brw_check_conditional_render(brw))
 572       return;
 573
 574    /* Handle primitive restart if needed */
 575    if (brw_handle_primitive_restart(ctx, prims, nr_prims, ib, indirect)) {
 576       /* The draw was handled, so we can exit now */
 577       return;
 578    }
 579
 580    /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
 581     * won't support all the extensions we support.
 582     */
 583    if (ctx->RenderMode != GL_RENDER) {
 584       perf_debug("%s render mode not supported in hardware\n",
 585                  _mesa_enum_to_string(ctx->RenderMode));
 586       _swsetup_Wakeup(ctx);
 587       _tnl_wakeup(ctx);
 588       _tnl_draw_prims(ctx, prims, nr_prims, ib,
 589                       index_bounds_valid, min_index, max_index, NULL, NULL);
 590       return;
 591    }
 592
 593    /* If we're going to have to upload any of the user's vertex arrays, then
 594     * get the minimum and maximum of their index buffer so we know what range
 595     * to upload.
 596     */
 597    if (!index_bounds_valid && !vbo_all_varyings_in_vbos(arrays)) {
 598       perf_debug("Scanning index buffer to compute index buffer bounds.  "
 599                  "Use glDrawRangeElements() to avoid this.\n");
 600       vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index, nr_prims);
 601    }
 602
 603    /* Try drawing with the hardware, but don't do anything else if we can't
 604     * manage it.  swrast doesn't support our featureset, so we can't fall back
 605     * to it.
 606     */
 607    brw_try_draw_prims(ctx, arrays, prims, nr_prims, ib, min_index, max_index, indirect);
 608 }
 609
 610 void brw_draw_init( struct brw_context *brw )
 611 {
 612    struct gl_context *ctx = &brw->ctx;
 613    struct vbo_context *vbo = vbo_context(ctx);
 614    int i;
 615
 616    /* Register our drawing function:
 617     */
 618    vbo->draw_prims = brw_draw_prims;
 619
 620    for (i = 0; i < VERT_ATTRIB_MAX; i++)
 621       brw->vb.inputs[i].buffer = -1;
 622    brw->vb.nr_buffers = 0;
 623    brw->vb.nr_enabled = 0;
 624 }
 625
 626 void brw_draw_destroy( struct brw_context *brw )
 627 {
 628    int i;
 629
 630    for (i = 0; i < brw->vb.nr_buffers; i++) {
 631       drm_intel_bo_unreference(brw->vb.buffers[i].bo);
 632       brw->vb.buffers[i].bo = NULL;
 633    }
 634    brw->vb.nr_buffers = 0;
 635
 636    for (i = 0; i < brw->vb.nr_enabled; i++) {
 637       brw->vb.enabled[i]->buffer = -1;
 638    }
 639    brw->vb.nr_enabled = 0;
 640
 641    drm_intel_bo_unreference(brw->ib.bo);
 642    brw->ib.bo = NULL;
 643 }