2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/blend.h"
29 #include "main/context.h"
30 #include "main/condrender.h"
31 #include "main/samplerobj.h"
32 #include "main/state.h"
33 #include "main/enums.h"
34 #include "main/macros.h"
35 #include "main/transformfeedback.h"
36 #include "main/framebuffer.h"
38 #include "vbo/vbo_context.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "drivers/common/meta.h"
42 #include "util/bitscan.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "compiler/brw_eu_defines.h"
48 #include "brw_context.h"
49 #include "brw_state.h"
51 #include "intel_batchbuffer.h"
52 #include "intel_buffers.h"
53 #include "intel_fbo.h"
54 #include "intel_mipmap_tree.h"
55 #include "intel_buffer_objects.h"
57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
60 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
61 [GL_POINTS
] = GL_POINTS
,
62 [GL_LINES
] = GL_LINES
,
63 [GL_LINE_LOOP
] = GL_LINES
,
64 [GL_LINE_STRIP
] = GL_LINES
,
65 [GL_TRIANGLES
] = GL_TRIANGLES
,
66 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
67 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
68 [GL_QUADS
] = GL_TRIANGLES
,
69 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
70 [GL_POLYGON
] = GL_TRIANGLES
73 /* When the primitive changes, set a state bit and re-validate. Not
74 * the nicest and would rather deal with this by having all the
75 * programs be immune to the active primitive (ie. cope with all
76 * possibilities). That may not be realistic however.
79 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
81 struct gl_context
*ctx
= &brw
->ctx
;
82 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
84 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
86 /* Slight optimization to avoid the GS program when not needed:
88 if (prim
->mode
== GL_QUAD_STRIP
&&
89 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
90 ctx
->Polygon
.FrontMode
== GL_FILL
&&
91 ctx
->Polygon
.BackMode
== GL_FILL
)
92 hw_prim
= _3DPRIM_TRISTRIP
;
94 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
95 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
96 ctx
->Polygon
.FrontMode
== GL_FILL
&&
97 ctx
->Polygon
.BackMode
== GL_FILL
) {
98 hw_prim
= _3DPRIM_TRIFAN
;
101 if (hw_prim
!= brw
->primitive
) {
102 brw
->primitive
= hw_prim
;
103 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
105 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
106 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
107 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
113 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
115 const struct gl_context
*ctx
= &brw
->ctx
;
118 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
120 if (prim
->mode
== GL_PATCHES
) {
121 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
123 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
126 if (hw_prim
!= brw
->primitive
) {
127 brw
->primitive
= hw_prim
;
128 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
129 if (prim
->mode
== GL_PATCHES
)
130 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
136 * The hardware is capable of removing dangling vertices on its own; however,
137 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
138 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
139 * This function manually trims dangling vertices from a draw call involving
140 * quads so that those dangling vertices won't get drawn when we convert to
144 trim(GLenum prim
, GLuint length
)
146 if (prim
== GL_QUAD_STRIP
)
147 return length
> 3 ? (length
- length
% 2) : 0;
148 else if (prim
== GL_QUADS
)
149 return length
- length
% 4;
156 brw_emit_prim(struct brw_context
*brw
,
157 const struct _mesa_prim
*prim
,
159 struct brw_transform_feedback_object
*xfb_obj
,
162 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
163 int verts_per_instance
;
164 int vertex_access_type
;
167 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
168 prim
->start
, prim
->count
);
170 int start_vertex_location
= prim
->start
;
171 int base_vertex_location
= prim
->basevertex
;
174 vertex_access_type
= devinfo
->gen
>= 7 ?
175 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
176 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
177 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
178 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
180 vertex_access_type
= devinfo
->gen
>= 7 ?
181 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
182 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
183 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
186 /* We only need to trim the primitive count on pre-Gen6. */
187 if (devinfo
->gen
< 6)
188 verts_per_instance
= trim(prim
->mode
, prim
->count
);
190 verts_per_instance
= prim
->count
;
192 /* If nothing to emit, just return. */
193 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
196 /* If we're set to always flush, do it before and after the primitive emit.
197 * We want to catch both missed flushes that hurt instruction/state cache
198 * and missed flushes of the render cache as it heads to other parts of
199 * the besides the draw code.
201 if (brw
->always_flush_cache
)
202 brw_emit_mi_flush(brw
);
204 /* If indirect, emit a bunch of loads from the indirect BO. */
206 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
208 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
209 xfb_obj
->prim_count_bo
,
210 stream
* sizeof(uint32_t));
212 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
213 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
214 OUT_BATCH(prim
->num_instances
);
215 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
217 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
219 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
222 } else if (prim
->is_indirect
) {
223 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
224 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
225 intel_buffer_object(indirect_buffer
),
226 prim
->indirect_offset
, 5 * sizeof(GLuint
), false);
228 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
230 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
231 prim
->indirect_offset
+ 0);
232 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
233 prim
->indirect_offset
+ 4);
235 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
236 prim
->indirect_offset
+ 8);
238 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
239 prim
->indirect_offset
+ 12);
240 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
241 prim
->indirect_offset
+ 16);
243 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
244 prim
->indirect_offset
+ 12);
245 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
251 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
253 if (devinfo
->gen
>= 7) {
254 const int predicate_enable
=
255 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
256 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
258 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
259 OUT_BATCH(hw_prim
| vertex_access_type
);
261 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
262 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
265 OUT_BATCH(verts_per_instance
);
266 OUT_BATCH(start_vertex_location
);
267 OUT_BATCH(prim
->num_instances
);
268 OUT_BATCH(prim
->base_instance
);
269 OUT_BATCH(base_vertex_location
);
272 if (brw
->always_flush_cache
)
273 brw_emit_mi_flush(brw
);
278 brw_merge_inputs(struct brw_context
*brw
,
279 const struct gl_vertex_array
*arrays
[])
281 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
282 const struct gl_context
*ctx
= &brw
->ctx
;
285 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
286 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
287 brw
->vb
.buffers
[i
].bo
= NULL
;
289 brw
->vb
.nr_buffers
= 0;
291 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
292 brw
->vb
.inputs
[i
].buffer
= -1;
293 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
296 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
297 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
298 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
299 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
302 uint8_t wa_flags
= 0;
304 i
= u_bit_scan64(&mask
);
306 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
309 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
312 case GL_INT_2_10_10_10_REV
:
313 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
316 case GL_UNSIGNED_INT_2_10_10_10_REV
:
317 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
318 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
320 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
321 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
322 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
323 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
328 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
329 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
330 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
336 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
337 * or shader image. This causes a self-dependency, where both rendering
338 * and sampling may concurrently read or write the CCS buffer, causing
342 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
343 struct intel_mipmap_tree
*tex_mt
,
344 unsigned min_level
, unsigned num_levels
,
347 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
350 /* We only need to worry about color compression and fast clears. */
351 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
352 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
355 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
356 const struct intel_renderbuffer
*irb
=
357 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
359 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
360 irb
->mt_level
>= min_level
&&
361 irb
->mt_level
< min_level
+ num_levels
) {
362 found
= brw
->draw_aux_buffer_disabled
[i
] = true;
367 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
375 * \brief Resolve buffers before drawing.
377 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
378 * enabled depth texture, and flush the render cache for any dirty textures.
381 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
)
383 struct gl_context
*ctx
= &brw
->ctx
;
384 struct intel_texture_object
*tex_obj
;
386 memset(brw
->draw_aux_buffer_disabled
, 0,
387 sizeof(brw
->draw_aux_buffer_disabled
));
389 /* Resolve depth buffer and render cache of each enabled texture. */
390 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
391 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
392 if (!ctx
->Texture
.Unit
[i
]._Current
)
394 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
395 if (!tex_obj
|| !tex_obj
->mt
)
398 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
399 enum isl_format view_format
=
400 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
402 unsigned min_level
, min_layer
, num_levels
, num_layers
;
403 if (tex_obj
->base
.Immutable
) {
404 min_level
= tex_obj
->base
.MinLevel
;
405 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
406 min_layer
= tex_obj
->base
.MinLayer
;
407 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
408 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
410 min_level
= tex_obj
->base
.BaseLevel
;
411 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
413 num_layers
= INTEL_REMAINING_LAYERS
;
416 const bool disable_aux
= rendering
&&
417 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
, min_level
, num_levels
,
420 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
421 min_level
, num_levels
,
422 min_layer
, num_layers
,
425 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
427 if (tex_obj
->base
.StencilSampling
||
428 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
429 intel_update_r8stencil(brw
, tex_obj
->mt
);
433 /* Resolve color for each active shader image. */
434 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
435 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
437 if (unlikely(prog
&& prog
->info
.num_images
)) {
438 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
439 struct gl_image_unit
*u
=
440 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
441 tex_obj
= intel_texture_object(u
->TexObj
);
443 if (tex_obj
&& tex_obj
->mt
) {
444 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
, 0, ~0,
445 "as a shader image");
447 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
449 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
457 brw_predraw_resolve_framebuffer(struct brw_context
*brw
)
459 struct gl_context
*ctx
= &brw
->ctx
;
460 struct intel_renderbuffer
*depth_irb
;
462 /* Resolve the depth buffer's HiZ buffer. */
463 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
464 if (depth_irb
&& depth_irb
->mt
) {
465 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
468 depth_irb
->layer_count
);
471 /* Resolve color buffers for non-coherent framebuffer fetch. */
472 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
473 ctx
->FragmentProgram
._Current
&&
474 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
475 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
477 /* This is only used for non-coherent framebuffer fetch, so we don't
478 * need to worry about CCS_E and can simply pass 'false' below.
480 assert(brw
->screen
->devinfo
.gen
< 9);
482 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
483 const struct intel_renderbuffer
*irb
=
484 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
487 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
489 irb
->mt_layer
, irb
->layer_count
,
495 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
496 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
497 struct intel_renderbuffer
*irb
=
498 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
500 if (irb
== NULL
|| irb
->mt
== NULL
)
503 mesa_format mesa_format
=
504 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
505 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
507 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
508 irb
->mt_layer
, irb
->layer_count
,
510 ctx
->Color
.BlendEnabled
& (1 << i
));
512 brw_cache_flush_for_render(brw
, irb
->mt
->bo
);
517 * \brief Call this after drawing to mark which buffers need resolving
519 * If the depth buffer was written to and if it has an accompanying HiZ
520 * buffer, then mark that it needs a depth resolve.
522 * If the color buffer is a multisample window system buffer, then
523 * mark that it needs a downsample.
525 * Also mark any render targets which will be textured as needing a render
529 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
531 struct gl_context
*ctx
= &brw
->ctx
;
532 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
534 struct intel_renderbuffer
*front_irb
= NULL
;
535 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
536 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
537 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
538 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
540 if (_mesa_is_front_buffer_drawing(fb
))
541 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
544 front_irb
->need_downsample
= true;
546 back_irb
->need_downsample
= true;
548 bool depth_written
= brw_depth_writes_enabled(brw
);
549 if (depth_att
->Layered
) {
550 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
553 depth_irb
->layer_count
,
556 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
558 depth_irb
->mt_layer
, 1,
562 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
565 if (stencil_irb
&& brw
->stencil_write_enabled
)
566 brw_depth_cache_add_bo(brw
, stencil_irb
->mt
->bo
);
568 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
569 struct intel_renderbuffer
*irb
=
570 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
575 mesa_format mesa_format
=
576 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
577 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
579 brw_render_cache_add_bo(brw
, irb
->mt
->bo
);
580 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
581 irb
->mt_layer
, irb
->layer_count
,
583 ctx
->Color
.BlendEnabled
& (1 << i
));
588 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
589 struct intel_renderbuffer
*irb
)
591 if (irb
->align_wa_mt
== NULL
)
594 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
596 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
598 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
600 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
602 /* Finally restore the x,y to correspond to full miptree. */
603 intel_renderbuffer_set_draw_offset(irb
);
605 /* Make sure render surface state gets re-emitted with updated miptree. */
606 brw
->NewGLState
|= _NEW_BUFFERS
;
610 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
612 struct gl_context
*ctx
= &brw
->ctx
;
613 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
615 struct intel_renderbuffer
*depth_irb
=
616 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
617 struct intel_renderbuffer
*stencil_irb
=
618 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
620 if (depth_irb
&& depth_irb
->align_wa_mt
)
621 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
623 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
624 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
626 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
627 struct intel_renderbuffer
*irb
=
628 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
630 if (!irb
|| irb
->align_wa_mt
== NULL
)
633 intel_renderbuffer_move_temp_back(brw
, irb
);
638 brw_prepare_drawing(struct gl_context
*ctx
,
639 const struct gl_vertex_array
*arrays
[],
640 const struct _mesa_index_buffer
*ib
,
641 bool index_bounds_valid
,
645 struct brw_context
*brw
= brw_context(ctx
);
648 _mesa_update_state(ctx
);
650 /* We have to validate the textures *before* checking for fallbacks;
651 * otherwise, the software fallback won't be able to rely on the
652 * texture state, the firstLevel and lastLevel fields won't be
653 * set in the intel texture object (they'll both be 0), and the
654 * software fallback will segfault if it attempts to access any
655 * texture level other than level 0.
657 brw_validate_textures(brw
);
659 /* Find the highest sampler unit used by each shader program. A bit-count
660 * won't work since ARB programs use the texture unit number as the sampler
663 brw
->wm
.base
.sampler_count
=
664 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
665 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
666 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
667 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
668 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
669 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
670 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
671 brw
->vs
.base
.sampler_count
=
672 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
674 intel_prepare_render(brw
);
676 /* This workaround has to happen outside of brw_upload_render_state()
677 * because it may flush the batchbuffer for a blit, affecting the state
680 brw_workaround_depthstencil_alignment(brw
, 0);
682 /* Resolves must occur after updating renderbuffers, updating context state,
683 * and finalizing textures but before setting up any hardware state for
686 brw_predraw_resolve_inputs(brw
, true);
687 brw_predraw_resolve_framebuffer(brw
);
689 /* Bind all inputs, derive varying and size information:
691 brw_merge_inputs(brw
, arrays
);
694 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
696 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
697 brw
->vb
.min_index
= min_index
;
698 brw
->vb
.max_index
= max_index
;
699 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
703 brw_finish_drawing(struct gl_context
*ctx
)
705 struct brw_context
*brw
= brw_context(ctx
);
707 if (brw
->always_flush_batch
)
708 intel_batchbuffer_flush(brw
);
710 brw_program_cache_check_size(brw
);
711 brw_postdraw_reconcile_align_wa_slices(brw
);
712 brw_postdraw_set_buffers_need_resolve(brw
);
714 if (brw
->draw
.draw_params_count_bo
) {
715 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
716 brw
->draw
.draw_params_count_bo
= NULL
;
720 /* May fail if out of video memory for texture or vbo upload, or on
721 * fallback conditions.
724 brw_draw_single_prim(struct gl_context
*ctx
,
725 const struct gl_vertex_array
*arrays
[],
726 const struct _mesa_prim
*prim
,
728 struct brw_transform_feedback_object
*xfb_obj
,
730 struct gl_buffer_object
*indirect
)
732 struct brw_context
*brw
= brw_context(ctx
);
733 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
734 bool fail_next
= false;
736 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
737 * atoms that happen on every draw call.
739 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
741 /* Flush the batch if the batch/state buffers are nearly full. We can
742 * grow them if needed, but this is not free, so we'd like to avoid it.
744 intel_batchbuffer_require_space(brw
, 1500, RENDER_RING
);
745 brw_require_statebuffer_space(brw
, 2400);
746 intel_batchbuffer_save_state(brw
);
748 if (brw
->num_instances
!= prim
->num_instances
||
749 brw
->basevertex
!= prim
->basevertex
||
750 brw
->baseinstance
!= prim
->base_instance
) {
751 brw
->num_instances
= prim
->num_instances
;
752 brw
->basevertex
= prim
->basevertex
;
753 brw
->baseinstance
= prim
->base_instance
;
754 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
755 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
756 brw_merge_inputs(brw
, arrays
);
760 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
761 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
762 * always flag if the shader uses one of the values. For direct draws,
763 * we only flag if the values change.
765 const int new_basevertex
=
766 prim
->indexed
? prim
->basevertex
: prim
->start
;
767 const int new_baseinstance
= prim
->base_instance
;
768 const struct brw_vs_prog_data
*vs_prog_data
=
769 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
771 const bool uses_draw_parameters
=
772 vs_prog_data
->uses_basevertex
||
773 vs_prog_data
->uses_baseinstance
;
775 if ((uses_draw_parameters
&& prim
->is_indirect
) ||
776 (vs_prog_data
->uses_basevertex
&&
777 brw
->draw
.params
.gl_basevertex
!= new_basevertex
) ||
778 (vs_prog_data
->uses_baseinstance
&&
779 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
780 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
783 brw
->draw
.params
.gl_basevertex
= new_basevertex
;
784 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
785 brw_bo_unreference(brw
->draw
.draw_params_bo
);
787 if (prim
->is_indirect
) {
788 /* Point draw_params_bo at the indirect buffer. */
789 brw
->draw
.draw_params_bo
=
790 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
791 brw_bo_reference(brw
->draw
.draw_params_bo
);
792 brw
->draw
.draw_params_offset
=
793 prim
->indirect_offset
+ (prim
->indexed
? 12 : 8);
795 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
796 * has to upload gl_BaseVertex and such if they're needed.
798 brw
->draw
.draw_params_bo
= NULL
;
799 brw
->draw
.draw_params_offset
= 0;
802 /* gl_DrawID always needs its own vertex buffer since it's not part of
803 * the indirect parameter buffer. If the program uses gl_DrawID we need
804 * to flag BRW_NEW_VERTICES. For the first iteration, we don't have
805 * valid vs_prog_data, but we always flag BRW_NEW_VERTICES before
808 brw
->draw
.gl_drawid
= prim
->draw_id
;
809 brw_bo_unreference(brw
->draw
.draw_id_bo
);
810 brw
->draw
.draw_id_bo
= NULL
;
811 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
812 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
814 if (devinfo
->gen
< 6)
815 brw_set_prim(brw
, prim
);
817 gen6_set_prim(brw
, prim
);
821 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
822 * that the state updated in the loop outside of this block is that in
823 * *_set_prim or intel_batchbuffer_flush(), which only impacts
824 * brw->ctx.NewDriverState.
826 if (brw
->ctx
.NewDriverState
) {
827 brw
->batch
.no_wrap
= true;
828 brw_upload_render_state(brw
);
831 brw_emit_prim(brw
, prim
, brw
->primitive
, xfb_obj
, stream
);
833 brw
->batch
.no_wrap
= false;
835 if (!brw_batch_has_aperture_space(brw
, 0)) {
837 intel_batchbuffer_reset_to_saved(brw
);
838 intel_batchbuffer_flush(brw
);
842 int ret
= intel_batchbuffer_flush(brw
);
843 WARN_ONCE(ret
== -ENOSPC
,
844 "i965: Single primitive emit exceeded "
845 "available aperture space\n");
849 /* Now that we know we haven't run out of aperture space, we can safely
850 * reset the dirty bits.
852 if (brw
->ctx
.NewDriverState
)
853 brw_render_state_finished(brw
);
859 brw_draw_prims(struct gl_context
*ctx
,
860 const struct _mesa_prim
*prims
,
862 const struct _mesa_index_buffer
*ib
,
863 GLboolean index_bounds_valid
,
866 struct gl_transform_feedback_object
*gl_xfb_obj
,
868 struct gl_buffer_object
*indirect
)
871 struct brw_context
*brw
= brw_context(ctx
);
872 const struct gl_vertex_array
**arrays
= ctx
->Array
._DrawArrays
;
873 int predicate_state
= brw
->predicate
.state
;
874 struct brw_transform_feedback_object
*xfb_obj
=
875 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
877 if (!brw_check_conditional_render(brw
))
880 /* Handle primitive restart if needed */
881 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
882 /* The draw was handled, so we can exit now */
886 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
887 * won't support all the extensions we support.
889 if (ctx
->RenderMode
!= GL_RENDER
) {
890 perf_debug("%s render mode not supported in hardware\n",
891 _mesa_enum_to_string(ctx
->RenderMode
));
892 _swsetup_Wakeup(ctx
);
894 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
895 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
899 /* If we're going to have to upload any of the user's vertex arrays, then
900 * get the minimum and maximum of their index buffer so we know what range
903 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
904 perf_debug("Scanning index buffer to compute index buffer bounds. "
905 "Use glDrawRangeElements() to avoid this.\n");
906 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
907 index_bounds_valid
= true;
910 brw_prepare_drawing(ctx
, arrays
, ib
, index_bounds_valid
, min_index
,
912 /* Try drawing with the hardware, but don't do anything else if we can't
913 * manage it. swrast doesn't support our featureset, so we can't fall back
917 for (i
= 0; i
< nr_prims
; i
++) {
918 /* Implementation of ARB_indirect_parameters via predicates */
919 if (brw
->draw
.draw_params_count_bo
) {
920 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
922 /* Upload the current draw count from the draw parameters buffer to
925 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
926 brw
->draw
.draw_params_count_bo
,
927 brw
->draw
.draw_params_count_offset
);
928 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
929 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
930 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
931 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
934 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
935 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
936 MI_PREDICATE_COMBINEOP_SET
|
937 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
939 OUT_BATCH(GEN7_MI_PREDICATE
|
940 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
941 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
945 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
948 brw_draw_single_prim(ctx
, arrays
, &prims
[i
], i
, xfb_obj
, stream
,
952 brw_finish_drawing(ctx
);
953 brw
->predicate
.state
= predicate_state
;
957 brw_draw_indirect_prims(struct gl_context
*ctx
,
959 struct gl_buffer_object
*indirect_data
,
960 GLsizeiptr indirect_offset
,
963 struct gl_buffer_object
*indirect_params
,
964 GLsizeiptr indirect_params_offset
,
965 const struct _mesa_index_buffer
*ib
)
967 struct brw_context
*brw
= brw_context(ctx
);
968 struct _mesa_prim
*prim
;
971 prim
= calloc(draw_count
, sizeof(*prim
));
973 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
974 (draw_count
> 1) ? "Multi" : "",
975 ib
? "Elements" : "Arrays",
976 indirect_params
? "CountARB" : "");
981 prim
[draw_count
- 1].end
= 1;
982 for (i
= 0; i
< draw_count
; ++i
, indirect_offset
+= stride
) {
984 prim
[i
].indexed
= ib
!= NULL
;
985 prim
[i
].indirect_offset
= indirect_offset
;
986 prim
[i
].is_indirect
= 1;
990 if (indirect_params
) {
991 brw
->draw
.draw_params_count_bo
=
992 intel_buffer_object(indirect_params
)->buffer
;
993 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
994 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
997 brw_draw_prims(ctx
, prim
, draw_count
,
1006 brw_draw_init(struct brw_context
*brw
)
1008 struct gl_context
*ctx
= &brw
->ctx
;
1009 struct vbo_context
*vbo
= vbo_context(ctx
);
1011 /* Register our drawing function:
1013 vbo
->draw_prims
= brw_draw_prims
;
1014 vbo
->draw_indirect_prims
= brw_draw_indirect_prims
;
1016 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1017 brw
->vb
.inputs
[i
].buffer
= -1;
1018 brw
->vb
.nr_buffers
= 0;
1019 brw
->vb
.nr_enabled
= 0;
1023 brw_draw_destroy(struct brw_context
*brw
)
1027 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1028 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1029 brw
->vb
.buffers
[i
].bo
= NULL
;
1031 brw
->vb
.nr_buffers
= 0;
1033 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1034 brw
->vb
.enabled
[i
]->buffer
= -1;
1036 brw
->vb
.nr_enabled
= 0;
1038 brw_bo_unreference(brw
->ib
.bo
);