1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <sys/errno.h>
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/condrender.h"
33 #include "main/samplerobj.h"
34 #include "main/state.h"
35 #include "main/enums.h"
36 #include "main/macros.h"
37 #include "main/transformfeedback.h"
39 #include "vbo/vbo_context.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_buffer_objects.h"
56 #define FILE_DEBUG_FLAG DEBUG_PRIMS
58 static const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
70 _3DPRIM_LINESTRIP_ADJ
,
76 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
90 get_hw_prim_for_gl_prim(int mode
)
92 if (mode
>= BRW_PRIM_OFFSET
)
93 return mode
- BRW_PRIM_OFFSET
;
95 return prim_to_hw_prim
[mode
];
99 /* When the primitive changes, set a state bit and re-validate. Not
100 * the nicest and would rather deal with this by having all the
101 * programs be immune to the active primitive (ie. cope with all
102 * possibilities). That may not be realistic however.
104 static void brw_set_prim(struct brw_context
*brw
,
105 const struct _mesa_prim
*prim
)
107 struct gl_context
*ctx
= &brw
->ctx
;
108 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
110 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
112 /* Slight optimization to avoid the GS program when not needed:
114 if (prim
->mode
== GL_QUAD_STRIP
&&
115 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
116 ctx
->Polygon
.FrontMode
== GL_FILL
&&
117 ctx
->Polygon
.BackMode
== GL_FILL
)
118 hw_prim
= _3DPRIM_TRISTRIP
;
120 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
121 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
122 ctx
->Polygon
.FrontMode
== GL_FILL
&&
123 ctx
->Polygon
.BackMode
== GL_FILL
) {
124 hw_prim
= _3DPRIM_TRIFAN
;
127 if (hw_prim
!= brw
->primitive
) {
128 brw
->primitive
= hw_prim
;
129 SET_DIRTY_BIT(brw
, BRW_NEW_PRIMITIVE
);
131 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
132 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
133 SET_DIRTY_BIT(brw
, BRW_NEW_REDUCED_PRIMITIVE
);
138 static void gen6_set_prim(struct brw_context
*brw
,
139 const struct _mesa_prim
*prim
)
143 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
145 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
147 if (hw_prim
!= brw
->primitive
) {
148 brw
->primitive
= hw_prim
;
149 SET_DIRTY_BIT(brw
, BRW_NEW_PRIMITIVE
);
155 * The hardware is capable of removing dangling vertices on its own; however,
156 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
157 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
158 * This function manually trims dangling vertices from a draw call involving
159 * quads so that those dangling vertices won't get drawn when we convert to
162 static GLuint
trim(GLenum prim
, GLuint length
)
164 if (prim
== GL_QUAD_STRIP
)
165 return length
> 3 ? (length
- length
% 2) : 0;
166 else if (prim
== GL_QUADS
)
167 return length
- length
% 4;
173 static void brw_emit_prim(struct brw_context
*brw
,
174 const struct _mesa_prim
*prim
,
177 int verts_per_instance
;
178 int vertex_access_type
;
179 int start_vertex_location
;
180 int base_vertex_location
;
183 DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim
->mode
),
184 prim
->start
, prim
->count
);
186 start_vertex_location
= prim
->start
;
187 base_vertex_location
= prim
->basevertex
;
189 vertex_access_type
= brw
->gen
>= 7 ?
190 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
191 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
192 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
193 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
195 vertex_access_type
= brw
->gen
>= 7 ?
196 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
197 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
198 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
201 /* We only need to trim the primitive count on pre-Gen6. */
203 verts_per_instance
= trim(prim
->mode
, prim
->count
);
205 verts_per_instance
= prim
->count
;
207 /* If nothing to emit, just return. */
208 if (verts_per_instance
== 0 && !prim
->is_indirect
)
211 /* If we're set to always flush, do it before and after the primitive emit.
212 * We want to catch both missed flushes that hurt instruction/state cache
213 * and missed flushes of the render cache as it heads to other parts of
214 * the besides the draw code.
216 if (brw
->always_flush_cache
) {
217 intel_batchbuffer_emit_mi_flush(brw
);
220 /* If indirect, emit a bunch of loads from the indirect BO. */
221 if (prim
->is_indirect
) {
222 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
223 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
224 intel_buffer_object(indirect_buffer
),
225 prim
->indirect_offset
, 5 * sizeof(GLuint
));
227 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
229 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
230 I915_GEM_DOMAIN_VERTEX
, 0,
231 prim
->indirect_offset
+ 0);
232 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
233 I915_GEM_DOMAIN_VERTEX
, 0,
234 prim
->indirect_offset
+ 4);
236 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
237 I915_GEM_DOMAIN_VERTEX
, 0,
238 prim
->indirect_offset
+ 8);
240 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
241 I915_GEM_DOMAIN_VERTEX
, 0,
242 prim
->indirect_offset
+ 12);
243 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
244 I915_GEM_DOMAIN_VERTEX
, 0,
245 prim
->indirect_offset
+ 16);
247 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
248 I915_GEM_DOMAIN_VERTEX
, 0,
249 prim
->indirect_offset
+ 12);
251 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
252 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
264 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
);
265 OUT_BATCH(hw_prim
| vertex_access_type
);
268 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
269 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
272 OUT_BATCH(verts_per_instance
);
273 OUT_BATCH(start_vertex_location
);
274 OUT_BATCH(prim
->num_instances
);
275 OUT_BATCH(prim
->base_instance
);
276 OUT_BATCH(base_vertex_location
);
279 /* Only used on Sandybridge; harmless to set elsewhere. */
280 brw
->batch
.need_workaround_flush
= true;
282 if (brw
->always_flush_cache
) {
283 intel_batchbuffer_emit_mi_flush(brw
);
288 static void brw_merge_inputs( struct brw_context
*brw
,
289 const struct gl_client_array
*arrays
[])
293 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
294 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
295 brw
->vb
.buffers
[i
].bo
= NULL
;
297 brw
->vb
.nr_buffers
= 0;
299 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
300 brw
->vb
.inputs
[i
].buffer
= -1;
301 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
306 * \brief Call this after drawing to mark which buffers need resolving
308 * If the depth buffer was written to and if it has an accompanying HiZ
309 * buffer, then mark that it needs a depth resolve.
311 * If the color buffer is a multisample window system buffer, then
312 * mark that it needs a downsample.
314 * Also mark any render targets which will be textured as needing a render
317 static void brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
319 struct gl_context
*ctx
= &brw
->ctx
;
320 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
322 struct intel_renderbuffer
*front_irb
= NULL
;
323 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
324 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
325 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
326 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
328 if (brw_is_front_buffer_drawing(fb
))
329 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
332 front_irb
->need_downsample
= true;
334 back_irb
->need_downsample
= true;
335 if (depth_irb
&& ctx
->Depth
.Mask
) {
336 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
337 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
340 if (ctx
->Extensions
.ARB_stencil_texturing
&&
341 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
342 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
345 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
346 struct intel_renderbuffer
*irb
=
347 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
350 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
354 /* May fail if out of video memory for texture or vbo upload, or on
355 * fallback conditions.
357 static bool brw_try_draw_prims( struct gl_context
*ctx
,
358 const struct gl_client_array
*arrays
[],
359 const struct _mesa_prim
*prims
,
361 const struct _mesa_index_buffer
*ib
,
364 struct gl_buffer_object
*indirect
)
366 struct brw_context
*brw
= brw_context(ctx
);
369 bool fail_next
= false;
372 _mesa_update_state( ctx
);
374 /* Find the highest sampler unit used by each shader program. A bit-count
375 * won't work since ARB programs use the texture unit number as the sampler
378 brw
->wm
.base
.sampler_count
=
379 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
380 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
381 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
382 brw
->vs
.base
.sampler_count
=
383 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
385 /* We have to validate the textures *before* checking for fallbacks;
386 * otherwise, the software fallback won't be able to rely on the
387 * texture state, the firstLevel and lastLevel fields won't be
388 * set in the intel texture object (they'll both be 0), and the
389 * software fallback will segfault if it attempts to access any
390 * texture level other than level 0.
392 brw_validate_textures( brw
);
394 intel_prepare_render(brw
);
396 /* This workaround has to happen outside of brw_upload_state() because it
397 * may flush the batchbuffer for a blit, affecting the state flags.
399 brw_workaround_depthstencil_alignment(brw
, 0);
401 /* Bind all inputs, derive varying and size information:
403 brw_merge_inputs( brw
, arrays
);
406 SET_DIRTY_BIT(brw
, BRW_NEW_INDICES
);
408 brw
->vb
.min_index
= min_index
;
409 brw
->vb
.max_index
= max_index
;
410 SET_DIRTY_BIT(brw
, BRW_NEW_VERTICES
);
412 for (i
= 0; i
< nr_prims
; i
++) {
413 int estimated_max_prim_size
;
414 const int sampler_state_size
= 16;
416 estimated_max_prim_size
= 512; /* batchbuffer commands */
417 estimated_max_prim_size
+= BRW_MAX_TEX_UNIT
*
418 (sampler_state_size
+ sizeof(struct gen5_sampler_default_color
));
419 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
420 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
421 estimated_max_prim_size
+= 512; /* misc. pad */
423 /* Flush the batch if it's approaching full, so that we don't wrap while
424 * we've got validated state that needs to be in the same batch as the
427 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
428 intel_batchbuffer_save_state(brw
);
430 if (brw
->num_instances
!= prims
[i
].num_instances
||
431 brw
->basevertex
!= prims
[i
].basevertex
) {
432 brw
->num_instances
= prims
[i
].num_instances
;
433 brw
->basevertex
= prims
[i
].basevertex
;
434 if (i
> 0) { /* For i == 0 we just did this before the loop */
435 SET_DIRTY_BIT(brw
, BRW_NEW_VERTICES
);
436 brw_merge_inputs(brw
, arrays
);
440 brw_set_prim(brw
, &prims
[i
]);
442 gen6_set_prim(brw
, &prims
[i
]);
445 /* Note that before the loop, brw->state.dirty.brw was set to != 0, and
446 * that the state updated in the loop outside of this block is that in
447 * *_set_prim or intel_batchbuffer_flush(), which only impacts
448 * brw->state.dirty.brw.
450 if (brw
->state
.dirty
.brw
) {
451 brw
->no_batch_wrap
= true;
452 brw_upload_state(brw
);
455 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
457 brw
->no_batch_wrap
= false;
459 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
461 intel_batchbuffer_reset_to_saved(brw
);
462 intel_batchbuffer_flush(brw
);
466 if (intel_batchbuffer_flush(brw
) == -ENOSPC
) {
467 static bool warned
= false;
470 fprintf(stderr
, "i965: Single primitive emit exceeded"
471 "available aperture space\n");
480 /* Now that we know we haven't run out of aperture space, we can safely
481 * reset the dirty bits.
483 if (brw
->state
.dirty
.brw
)
484 brw_clear_dirty_bits(brw
);
487 if (brw
->always_flush_batch
)
488 intel_batchbuffer_flush(brw
);
490 brw_state_cache_check_size(brw
);
491 brw_postdraw_set_buffers_need_resolve(brw
);
496 void brw_draw_prims( struct gl_context
*ctx
,
497 const struct _mesa_prim
*prims
,
499 const struct _mesa_index_buffer
*ib
,
500 GLboolean index_bounds_valid
,
503 struct gl_transform_feedback_object
*unused_tfb_object
,
504 struct gl_buffer_object
*indirect
)
506 struct brw_context
*brw
= brw_context(ctx
);
507 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
509 assert(unused_tfb_object
== NULL
);
511 if (ctx
->Query
.CondRenderQuery
) {
512 perf_debug("Conditional rendering is implemented in software and may "
513 "stall. This should be fixed in the driver.\n");
516 if (!_mesa_check_conditional_render(ctx
))
519 /* Handle primitive restart if needed */
520 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
521 /* The draw was handled, so we can exit now */
525 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
526 * won't support all the extensions we support.
528 if (ctx
->RenderMode
!= GL_RENDER
) {
529 perf_debug("%s render mode not supported in hardware\n",
530 _mesa_lookup_enum_by_nr(ctx
->RenderMode
));
531 _swsetup_Wakeup(ctx
);
533 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
534 index_bounds_valid
, min_index
, max_index
, NULL
, NULL
);
538 /* If we're going to have to upload any of the user's vertex arrays, then
539 * get the minimum and maximum of their index buffer so we know what range
542 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
543 perf_debug("Scanning index buffer to compute index buffer bounds. "
544 "Use glDrawRangeElements() to avoid this.\n");
545 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
548 /* Try drawing with the hardware, but don't do anything else if we can't
549 * manage it. swrast doesn't support our featureset, so we can't fall back
552 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
, indirect
);
555 void brw_draw_init( struct brw_context
*brw
)
557 struct gl_context
*ctx
= &brw
->ctx
;
558 struct vbo_context
*vbo
= vbo_context(ctx
);
561 /* Register our drawing function:
563 vbo
->draw_prims
= brw_draw_prims
;
565 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
566 brw
->vb
.inputs
[i
].buffer
= -1;
567 brw
->vb
.nr_buffers
= 0;
568 brw
->vb
.nr_enabled
= 0;
571 void brw_draw_destroy( struct brw_context
*brw
)
575 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
576 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
577 brw
->vb
.buffers
[i
].bo
= NULL
;
579 brw
->vb
.nr_buffers
= 0;
581 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
582 brw
->vb
.enabled
[i
]->buffer
= -1;
584 brw
->vb
.nr_enabled
= 0;
586 drm_intel_bo_unreference(brw
->ib
.bo
);