2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/glheader.h"
29 #include "main/context.h"
30 #include "main/condrender.h"
31 #include "main/samplerobj.h"
32 #include "main/state.h"
33 #include "main/enums.h"
34 #include "main/macros.h"
35 #include "main/transformfeedback.h"
36 #include "main/framebuffer.h"
38 #include "vbo/vbo_context.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "drivers/common/meta.h"
43 #include "brw_blorp.h"
45 #include "brw_defines.h"
46 #include "brw_context.h"
47 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_buffer_objects.h"
56 #define FILE_DEBUG_FLAG DEBUG_PRIMS
58 static const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
59 [GL_POINTS
] =_3DPRIM_POINTLIST
,
60 [GL_LINES
] = _3DPRIM_LINELIST
,
61 [GL_LINE_LOOP
] = _3DPRIM_LINELOOP
,
62 [GL_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
63 [GL_TRIANGLES
] = _3DPRIM_TRILIST
,
64 [GL_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
65 [GL_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
66 [GL_QUADS
] = _3DPRIM_QUADLIST
,
67 [GL_QUAD_STRIP
] = _3DPRIM_QUADSTRIP
,
68 [GL_POLYGON
] = _3DPRIM_POLYGON
,
69 [GL_LINES_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
70 [GL_LINE_STRIP_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
71 [GL_TRIANGLES_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
72 [GL_TRIANGLE_STRIP_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
76 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
77 [GL_POINTS
] = GL_POINTS
,
78 [GL_LINES
] = GL_LINES
,
79 [GL_LINE_LOOP
] = GL_LINES
,
80 [GL_LINE_STRIP
] = GL_LINES
,
81 [GL_TRIANGLES
] = GL_TRIANGLES
,
82 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
83 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
84 [GL_QUADS
] = GL_TRIANGLES
,
85 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
86 [GL_POLYGON
] = GL_TRIANGLES
90 get_hw_prim_for_gl_prim(int mode
)
92 if (mode
>= BRW_PRIM_OFFSET
)
93 return mode
- BRW_PRIM_OFFSET
;
95 assert(mode
< ARRAY_SIZE(prim_to_hw_prim
));
96 return prim_to_hw_prim
[mode
];
101 /* When the primitive changes, set a state bit and re-validate. Not
102 * the nicest and would rather deal with this by having all the
103 * programs be immune to the active primitive (ie. cope with all
104 * possibilities). That may not be realistic however.
107 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
109 struct gl_context
*ctx
= &brw
->ctx
;
110 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
112 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
114 /* Slight optimization to avoid the GS program when not needed:
116 if (prim
->mode
== GL_QUAD_STRIP
&&
117 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
118 ctx
->Polygon
.FrontMode
== GL_FILL
&&
119 ctx
->Polygon
.BackMode
== GL_FILL
)
120 hw_prim
= _3DPRIM_TRISTRIP
;
122 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
123 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
124 ctx
->Polygon
.FrontMode
== GL_FILL
&&
125 ctx
->Polygon
.BackMode
== GL_FILL
) {
126 hw_prim
= _3DPRIM_TRIFAN
;
129 if (hw_prim
!= brw
->primitive
) {
130 brw
->primitive
= hw_prim
;
131 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
133 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
134 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
135 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
141 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
143 const struct gl_context
*ctx
= &brw
->ctx
;
146 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
148 if (prim
->mode
== GL_PATCHES
)
149 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
151 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
153 if (hw_prim
!= brw
->primitive
) {
154 brw
->primitive
= hw_prim
;
155 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
161 * The hardware is capable of removing dangling vertices on its own; however,
162 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
163 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
164 * This function manually trims dangling vertices from a draw call involving
165 * quads so that those dangling vertices won't get drawn when we convert to
169 trim(GLenum prim
, GLuint length
)
171 if (prim
== GL_QUAD_STRIP
)
172 return length
> 3 ? (length
- length
% 2) : 0;
173 else if (prim
== GL_QUADS
)
174 return length
- length
% 4;
181 brw_emit_prim(struct brw_context
*brw
,
182 const struct _mesa_prim
*prim
,
185 int verts_per_instance
;
186 int vertex_access_type
;
189 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
190 prim
->start
, prim
->count
);
192 int start_vertex_location
= prim
->start
;
193 int base_vertex_location
= prim
->basevertex
;
196 vertex_access_type
= brw
->gen
>= 7 ?
197 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
198 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
199 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
200 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
202 vertex_access_type
= brw
->gen
>= 7 ?
203 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
204 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
205 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
208 /* We only need to trim the primitive count on pre-Gen6. */
210 verts_per_instance
= trim(prim
->mode
, prim
->count
);
212 verts_per_instance
= prim
->count
;
214 /* If nothing to emit, just return. */
215 if (verts_per_instance
== 0 && !prim
->is_indirect
)
218 /* If we're set to always flush, do it before and after the primitive emit.
219 * We want to catch both missed flushes that hurt instruction/state cache
220 * and missed flushes of the render cache as it heads to other parts of
221 * the besides the draw code.
223 if (brw
->always_flush_cache
)
224 brw_emit_mi_flush(brw
);
226 /* If indirect, emit a bunch of loads from the indirect BO. */
227 if (prim
->is_indirect
) {
228 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
229 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
230 intel_buffer_object(indirect_buffer
),
231 prim
->indirect_offset
, 5 * sizeof(GLuint
));
233 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
235 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
236 I915_GEM_DOMAIN_VERTEX
, 0,
237 prim
->indirect_offset
+ 0);
238 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
239 I915_GEM_DOMAIN_VERTEX
, 0,
240 prim
->indirect_offset
+ 4);
242 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
243 I915_GEM_DOMAIN_VERTEX
, 0,
244 prim
->indirect_offset
+ 8);
246 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
247 I915_GEM_DOMAIN_VERTEX
, 0,
248 prim
->indirect_offset
+ 12);
249 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
250 I915_GEM_DOMAIN_VERTEX
, 0,
251 prim
->indirect_offset
+ 16);
253 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
254 I915_GEM_DOMAIN_VERTEX
, 0,
255 prim
->indirect_offset
+ 12);
257 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
258 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
266 BEGIN_BATCH(brw
->gen
>= 7 ? 7 : 6);
269 const int predicate_enable
=
270 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
271 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
273 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
274 OUT_BATCH(hw_prim
| vertex_access_type
);
276 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
277 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
280 OUT_BATCH(verts_per_instance
);
281 OUT_BATCH(start_vertex_location
);
282 OUT_BATCH(prim
->num_instances
);
283 OUT_BATCH(prim
->base_instance
);
284 OUT_BATCH(base_vertex_location
);
287 if (brw
->always_flush_cache
)
288 brw_emit_mi_flush(brw
);
293 brw_merge_inputs(struct brw_context
*brw
,
294 const struct gl_client_array
*arrays
[])
296 const struct gl_context
*ctx
= &brw
->ctx
;
299 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
300 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
301 brw
->vb
.buffers
[i
].bo
= NULL
;
303 brw
->vb
.nr_buffers
= 0;
305 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
306 brw
->vb
.inputs
[i
].buffer
= -1;
307 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
310 if (brw
->gen
< 8 && !brw
->is_haswell
) {
311 struct gl_program
*vp
= &ctx
->VertexProgram
._Current
->Base
;
312 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
313 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
315 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
316 if (!(vp
->InputsRead
& BITFIELD64_BIT(i
)))
319 uint8_t wa_flags
= 0;
321 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
324 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
327 case GL_INT_2_10_10_10_REV
:
328 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
331 case GL_UNSIGNED_INT_2_10_10_10_REV
:
332 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
333 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
335 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
336 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
337 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
338 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
343 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
344 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
345 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
352 * \brief Call this after drawing to mark which buffers need resolving
354 * If the depth buffer was written to and if it has an accompanying HiZ
355 * buffer, then mark that it needs a depth resolve.
357 * If the color buffer is a multisample window system buffer, then
358 * mark that it needs a downsample.
360 * Also mark any render targets which will be textured as needing a render
364 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
366 struct gl_context
*ctx
= &brw
->ctx
;
367 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
369 struct intel_renderbuffer
*front_irb
= NULL
;
370 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
371 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
372 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
373 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
375 if (_mesa_is_front_buffer_drawing(fb
))
376 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
379 front_irb
->need_downsample
= true;
381 back_irb
->need_downsample
= true;
382 if (depth_irb
&& ctx
->Depth
.Mask
) {
383 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
384 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
387 if (ctx
->Extensions
.ARB_stencil_texturing
&&
388 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
389 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
392 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
393 struct intel_renderbuffer
*irb
=
394 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
397 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
401 /* May fail if out of video memory for texture or vbo upload, or on
402 * fallback conditions.
405 brw_try_draw_prims(struct gl_context
*ctx
,
406 const struct gl_client_array
*arrays
[],
407 const struct _mesa_prim
*prims
,
409 const struct _mesa_index_buffer
*ib
,
412 struct gl_buffer_object
*indirect
)
414 struct brw_context
*brw
= brw_context(ctx
);
416 bool fail_next
= false;
419 _mesa_update_state(ctx
);
421 /* Find the highest sampler unit used by each shader program. A bit-count
422 * won't work since ARB programs use the texture unit number as the sampler
425 brw
->wm
.base
.sampler_count
=
426 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
427 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
428 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
429 brw
->vs
.base
.sampler_count
=
430 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
432 /* We have to validate the textures *before* checking for fallbacks;
433 * otherwise, the software fallback won't be able to rely on the
434 * texture state, the firstLevel and lastLevel fields won't be
435 * set in the intel texture object (they'll both be 0), and the
436 * software fallback will segfault if it attempts to access any
437 * texture level other than level 0.
439 brw_validate_textures(brw
);
441 intel_prepare_render(brw
);
443 /* This workaround has to happen outside of brw_upload_render_state()
444 * because it may flush the batchbuffer for a blit, affecting the state
447 brw_workaround_depthstencil_alignment(brw
, 0);
449 /* Bind all inputs, derive varying and size information:
451 brw_merge_inputs(brw
, arrays
);
454 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
456 brw
->vb
.min_index
= min_index
;
457 brw
->vb
.max_index
= max_index
;
458 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
460 for (i
= 0; i
< nr_prims
; i
++) {
461 int estimated_max_prim_size
;
462 const int sampler_state_size
= 16;
464 estimated_max_prim_size
= 512; /* batchbuffer commands */
465 estimated_max_prim_size
+= BRW_MAX_TEX_UNIT
*
466 (sampler_state_size
+ sizeof(struct gen5_sampler_default_color
));
467 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
468 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
469 estimated_max_prim_size
+= 512; /* misc. pad */
471 /* Flush the batch if it's approaching full, so that we don't wrap while
472 * we've got validated state that needs to be in the same batch as the
475 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
476 intel_batchbuffer_save_state(brw
);
478 if (brw
->num_instances
!= prims
[i
].num_instances
||
479 brw
->basevertex
!= prims
[i
].basevertex
) {
480 brw
->num_instances
= prims
[i
].num_instances
;
481 brw
->basevertex
= prims
[i
].basevertex
;
482 if (i
> 0) { /* For i == 0 we just did this before the loop */
483 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
484 brw_merge_inputs(brw
, arrays
);
488 brw
->draw
.gl_basevertex
=
489 prims
[i
].indexed
? prims
[i
].basevertex
: prims
[i
].start
;
491 drm_intel_bo_unreference(brw
->draw
.draw_params_bo
);
493 if (prims
[i
].is_indirect
) {
494 /* Point draw_params_bo at the indirect buffer. */
495 brw
->draw
.draw_params_bo
=
496 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
497 drm_intel_bo_reference(brw
->draw
.draw_params_bo
);
498 brw
->draw
.draw_params_offset
=
499 prims
[i
].indirect_offset
+ (prims
[i
].indexed
? 12 : 8);
501 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
502 * has to upload gl_BaseVertex and such if they're needed.
504 brw
->draw
.draw_params_bo
= NULL
;
505 brw
->draw
.draw_params_offset
= 0;
509 brw_set_prim(brw
, &prims
[i
]);
511 gen6_set_prim(brw
, &prims
[i
]);
515 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
516 * that the state updated in the loop outside of this block is that in
517 * *_set_prim or intel_batchbuffer_flush(), which only impacts
518 * brw->ctx.NewDriverState.
520 if (brw
->ctx
.NewDriverState
) {
521 brw
->no_batch_wrap
= true;
522 brw_upload_render_state(brw
);
525 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
527 brw
->no_batch_wrap
= false;
529 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
531 intel_batchbuffer_reset_to_saved(brw
);
532 intel_batchbuffer_flush(brw
);
536 int ret
= intel_batchbuffer_flush(brw
);
537 WARN_ONCE(ret
== -ENOSPC
,
538 "i965: Single primitive emit exceeded "
539 "available aperture space\n");
543 /* Now that we know we haven't run out of aperture space, we can safely
544 * reset the dirty bits.
546 if (brw
->ctx
.NewDriverState
)
547 brw_render_state_finished(brw
);
550 if (brw
->always_flush_batch
)
551 intel_batchbuffer_flush(brw
);
553 brw_state_cache_check_size(brw
);
554 brw_postdraw_set_buffers_need_resolve(brw
);
560 brw_draw_prims(struct gl_context
*ctx
,
561 const struct _mesa_prim
*prims
,
563 const struct _mesa_index_buffer
*ib
,
564 GLboolean index_bounds_valid
,
567 struct gl_transform_feedback_object
*unused_tfb_object
,
569 struct gl_buffer_object
*indirect
)
571 struct brw_context
*brw
= brw_context(ctx
);
572 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
574 assert(unused_tfb_object
== NULL
);
576 if (!brw_check_conditional_render(brw
))
579 /* Handle primitive restart if needed */
580 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
581 /* The draw was handled, so we can exit now */
585 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
586 * won't support all the extensions we support.
588 if (ctx
->RenderMode
!= GL_RENDER
) {
589 perf_debug("%s render mode not supported in hardware\n",
590 _mesa_enum_to_string(ctx
->RenderMode
));
591 _swsetup_Wakeup(ctx
);
593 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
594 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
598 /* If we're going to have to upload any of the user's vertex arrays, then
599 * get the minimum and maximum of their index buffer so we know what range
602 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
603 perf_debug("Scanning index buffer to compute index buffer bounds. "
604 "Use glDrawRangeElements() to avoid this.\n");
605 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
608 /* Try drawing with the hardware, but don't do anything else if we can't
609 * manage it. swrast doesn't support our featureset, so we can't fall back
612 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
,
617 brw_draw_init(struct brw_context
*brw
)
619 struct gl_context
*ctx
= &brw
->ctx
;
620 struct vbo_context
*vbo
= vbo_context(ctx
);
622 /* Register our drawing function:
624 vbo
->draw_prims
= brw_draw_prims
;
626 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
627 brw
->vb
.inputs
[i
].buffer
= -1;
628 brw
->vb
.nr_buffers
= 0;
629 brw
->vb
.nr_enabled
= 0;
633 brw_draw_destroy(struct brw_context
*brw
)
637 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
638 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
639 brw
->vb
.buffers
[i
].bo
= NULL
;
641 brw
->vb
.nr_buffers
= 0;
643 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
644 brw
->vb
.enabled
[i
]->buffer
= -1;
646 brw
->vb
.nr_enabled
= 0;
648 drm_intel_bo_unreference(brw
->ib
.bo
);