1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <sys/errno.h>
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/condrender.h"
33 #include "main/samplerobj.h"
34 #include "main/state.h"
35 #include "main/enums.h"
36 #include "main/macros.h"
37 #include "main/transformfeedback.h"
39 #include "vbo/vbo_context.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
51 #include "intel_batchbuffer.h"
52 #include "intel_buffers.h"
53 #include "intel_fbo.h"
54 #include "intel_mipmap_tree.h"
55 #include "intel_buffer_objects.h"
57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
59 static const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
71 _3DPRIM_LINESTRIP_ADJ
,
77 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
91 get_hw_prim_for_gl_prim(int mode
)
93 if (mode
>= BRW_PRIM_OFFSET
)
94 return mode
- BRW_PRIM_OFFSET
;
96 return prim_to_hw_prim
[mode
];
100 /* When the primitive changes, set a state bit and re-validate. Not
101 * the nicest and would rather deal with this by having all the
102 * programs be immune to the active primitive (ie. cope with all
103 * possibilities). That may not be realistic however.
105 static void brw_set_prim(struct brw_context
*brw
,
106 const struct _mesa_prim
*prim
)
108 struct gl_context
*ctx
= &brw
->ctx
;
109 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
111 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
113 /* Slight optimization to avoid the GS program when not needed:
115 if (prim
->mode
== GL_QUAD_STRIP
&&
116 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
117 ctx
->Polygon
.FrontMode
== GL_FILL
&&
118 ctx
->Polygon
.BackMode
== GL_FILL
)
119 hw_prim
= _3DPRIM_TRISTRIP
;
121 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
122 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
123 ctx
->Polygon
.FrontMode
== GL_FILL
&&
124 ctx
->Polygon
.BackMode
== GL_FILL
) {
125 hw_prim
= _3DPRIM_TRIFAN
;
128 if (hw_prim
!= brw
->primitive
) {
129 brw
->primitive
= hw_prim
;
130 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
132 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
133 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
134 brw
->state
.dirty
.brw
|= BRW_NEW_REDUCED_PRIMITIVE
;
139 static void gen6_set_prim(struct brw_context
*brw
,
140 const struct _mesa_prim
*prim
)
144 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
146 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
148 if (hw_prim
!= brw
->primitive
) {
149 brw
->primitive
= hw_prim
;
150 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
156 * The hardware is capable of removing dangling vertices on its own; however,
157 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
158 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
159 * This function manually trims dangling vertices from a draw call involving
160 * quads so that those dangling vertices won't get drawn when we convert to
163 static GLuint
trim(GLenum prim
, GLuint length
)
165 if (prim
== GL_QUAD_STRIP
)
166 return length
> 3 ? (length
- length
% 2) : 0;
167 else if (prim
== GL_QUADS
)
168 return length
- length
% 4;
174 static void brw_emit_prim(struct brw_context
*brw
,
175 const struct _mesa_prim
*prim
,
178 int verts_per_instance
;
179 int vertex_access_type
;
182 DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim
->mode
),
183 prim
->start
, prim
->count
);
186 vertex_access_type
= brw
->gen
>= 7 ?
187 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
188 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
190 vertex_access_type
= brw
->gen
>= 7 ?
191 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
192 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
195 /* We only need to trim the primitive count on pre-Gen6. */
197 verts_per_instance
= trim(prim
->mode
, prim
->count
);
199 verts_per_instance
= prim
->count
;
201 /* If nothing to emit, just return. */
202 if (verts_per_instance
== 0 && !prim
->is_indirect
)
205 /* If we're set to always flush, do it before and after the primitive emit.
206 * We want to catch both missed flushes that hurt instruction/state cache
207 * and missed flushes of the render cache as it heads to other parts of
208 * the besides the draw code.
210 if (brw
->always_flush_cache
) {
211 intel_batchbuffer_emit_mi_flush(brw
);
214 /* If indirect, emit a bunch of loads from the indirect BO. */
215 if (prim
->is_indirect
) {
216 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
217 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
218 intel_buffer_object(indirect_buffer
),
219 prim
->indirect_offset
, 5 * sizeof(GLuint
));
221 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
223 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
224 I915_GEM_DOMAIN_VERTEX
, 0,
225 prim
->indirect_offset
+ 0);
226 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
227 I915_GEM_DOMAIN_VERTEX
, 0,
228 prim
->indirect_offset
+ 4);
230 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
231 I915_GEM_DOMAIN_VERTEX
, 0,
232 prim
->indirect_offset
+ 8);
234 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
235 I915_GEM_DOMAIN_VERTEX
, 0,
236 prim
->indirect_offset
+ 12);
237 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
238 I915_GEM_DOMAIN_VERTEX
, 0,
239 prim
->indirect_offset
+ 16);
241 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
242 I915_GEM_DOMAIN_VERTEX
, 0,
243 prim
->indirect_offset
+ 12);
245 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
246 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
258 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
);
259 OUT_BATCH(hw_prim
| vertex_access_type
);
262 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
263 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
266 OUT_BATCH(verts_per_instance
);
267 OUT_BATCH(brw
->draw
.start_vertex_location
);
268 OUT_BATCH(prim
->num_instances
);
269 OUT_BATCH(prim
->base_instance
);
270 OUT_BATCH(brw
->draw
.base_vertex_location
);
273 /* Only used on Sandybridge; harmless to set elsewhere. */
274 brw
->batch
.need_workaround_flush
= true;
276 if (brw
->always_flush_cache
) {
277 intel_batchbuffer_emit_mi_flush(brw
);
282 static void brw_merge_inputs( struct brw_context
*brw
,
283 const struct gl_client_array
*arrays
[])
285 const struct gl_context
*ctx
= &brw
->ctx
;
288 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
289 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
290 brw
->vb
.buffers
[i
].bo
= NULL
;
292 brw
->vb
.nr_buffers
= 0;
294 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
295 brw
->vb
.inputs
[i
].buffer
= -1;
296 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
299 if (brw
->gen
< 8 && !brw
->is_haswell
) {
300 struct gl_program
*vp
= &ctx
->VertexProgram
._Current
->Base
;
301 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
302 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
304 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
305 if (!(vp
->InputsRead
& BITFIELD64_BIT(i
)))
308 uint8_t wa_flags
= 0;
310 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
313 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
316 case GL_INT_2_10_10_10_REV
:
317 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
320 case GL_UNSIGNED_INT_2_10_10_10_REV
:
321 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
322 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
324 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
325 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
326 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
327 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
332 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
333 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
334 brw
->state
.dirty
.brw
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
341 * \brief Call this after drawing to mark which buffers need resolving
343 * If the depth buffer was written to and if it has an accompanying HiZ
344 * buffer, then mark that it needs a depth resolve.
346 * If the color buffer is a multisample window system buffer, then
347 * mark that it needs a downsample.
349 * Also mark any render targets which will be textured as needing a render
352 static void brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
354 struct gl_context
*ctx
= &brw
->ctx
;
355 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
357 struct intel_renderbuffer
*front_irb
= NULL
;
358 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
359 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
360 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
361 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
363 if (brw_is_front_buffer_drawing(fb
))
364 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
367 front_irb
->need_downsample
= true;
369 back_irb
->need_downsample
= true;
370 if (depth_irb
&& ctx
->Depth
.Mask
) {
371 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
372 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
375 if (ctx
->Extensions
.ARB_stencil_texturing
&&
376 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
377 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
380 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
381 struct intel_renderbuffer
*irb
=
382 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
385 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
389 /* May fail if out of video memory for texture or vbo upload, or on
390 * fallback conditions.
392 static void brw_try_draw_prims( struct gl_context
*ctx
,
393 const struct gl_client_array
*arrays
[],
394 const struct _mesa_prim
*prims
,
396 const struct _mesa_index_buffer
*ib
,
399 struct gl_buffer_object
*indirect
)
401 struct brw_context
*brw
= brw_context(ctx
);
403 bool fail_next
= false;
406 _mesa_update_state( ctx
);
408 /* Find the highest sampler unit used by each shader program. A bit-count
409 * won't work since ARB programs use the texture unit number as the sampler
412 brw
->wm
.base
.sampler_count
=
413 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
414 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
415 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
416 brw
->vs
.base
.sampler_count
=
417 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
419 /* We have to validate the textures *before* checking for fallbacks;
420 * otherwise, the software fallback won't be able to rely on the
421 * texture state, the firstLevel and lastLevel fields won't be
422 * set in the intel texture object (they'll both be 0), and the
423 * software fallback will segfault if it attempts to access any
424 * texture level other than level 0.
426 brw_validate_textures( brw
);
428 intel_prepare_render(brw
);
430 /* This workaround has to happen outside of brw_upload_state() because it
431 * may flush the batchbuffer for a blit, affecting the state flags.
433 brw_workaround_depthstencil_alignment(brw
, 0);
435 /* Bind all inputs, derive varying and size information:
437 brw_merge_inputs( brw
, arrays
);
440 brw
->state
.dirty
.brw
|= BRW_NEW_INDICES
;
442 brw
->vb
.min_index
= min_index
;
443 brw
->vb
.max_index
= max_index
;
444 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
446 for (i
= 0; i
< nr_prims
; i
++) {
447 int estimated_max_prim_size
;
448 const int sampler_state_size
= 16;
450 estimated_max_prim_size
= 512; /* batchbuffer commands */
451 estimated_max_prim_size
+= BRW_MAX_TEX_UNIT
*
452 (sampler_state_size
+ sizeof(struct gen5_sampler_default_color
));
453 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
454 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
455 estimated_max_prim_size
+= 512; /* misc. pad */
457 /* Flush the batch if it's approaching full, so that we don't wrap while
458 * we've got validated state that needs to be in the same batch as the
461 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
462 intel_batchbuffer_save_state(brw
);
464 if (brw
->num_instances
!= prims
[i
].num_instances
||
465 brw
->basevertex
!= prims
[i
].basevertex
) {
466 brw
->num_instances
= prims
[i
].num_instances
;
467 brw
->basevertex
= prims
[i
].basevertex
;
468 if (i
> 0) { /* For i == 0 we just did this before the loop */
469 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
470 brw_merge_inputs(brw
, arrays
);
474 brw
->draw
.indexed
= prims
[i
].indexed
;
475 brw
->draw
.start_vertex_location
= prims
[i
].start
;
476 brw
->draw
.base_vertex_location
= prims
[i
].basevertex
;
478 drm_intel_bo_unreference(brw
->draw
.draw_params_bo
);
480 if (prims
[i
].is_indirect
) {
481 /* Point draw_params_bo at the indirect buffer. */
482 brw
->draw
.draw_params_bo
=
483 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
484 drm_intel_bo_reference(brw
->draw
.draw_params_bo
);
485 brw
->draw
.draw_params_offset
=
486 prims
[i
].indirect_offset
+ (prims
[i
].indexed
? 12 : 8);
488 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
489 * has to upload gl_BaseVertex and such if they're needed.
491 brw
->draw
.draw_params_bo
= NULL
;
492 brw
->draw
.draw_params_offset
= 0;
496 brw_set_prim(brw
, &prims
[i
]);
498 gen6_set_prim(brw
, &prims
[i
]);
502 /* Note that before the loop, brw->state.dirty.brw was set to != 0, and
503 * that the state updated in the loop outside of this block is that in
504 * *_set_prim or intel_batchbuffer_flush(), which only impacts
505 * brw->state.dirty.brw.
507 if (brw
->state
.dirty
.brw
) {
508 brw
->no_batch_wrap
= true;
509 brw_upload_state(brw
);
512 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
514 brw
->no_batch_wrap
= false;
516 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
518 intel_batchbuffer_reset_to_saved(brw
);
519 intel_batchbuffer_flush(brw
);
523 if (intel_batchbuffer_flush(brw
) == -ENOSPC
) {
524 static bool warned
= false;
527 fprintf(stderr
, "i965: Single primitive emit exceeded"
528 "available aperture space\n");
535 /* Now that we know we haven't run out of aperture space, we can safely
536 * reset the dirty bits.
538 if (brw
->state
.dirty
.brw
)
539 brw_clear_dirty_bits(brw
);
542 if (brw
->always_flush_batch
)
543 intel_batchbuffer_flush(brw
);
545 brw_state_cache_check_size(brw
);
546 brw_postdraw_set_buffers_need_resolve(brw
);
551 void brw_draw_prims( struct gl_context
*ctx
,
552 const struct _mesa_prim
*prims
,
554 const struct _mesa_index_buffer
*ib
,
555 GLboolean index_bounds_valid
,
558 struct gl_transform_feedback_object
*unused_tfb_object
,
559 struct gl_buffer_object
*indirect
)
561 struct brw_context
*brw
= brw_context(ctx
);
562 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
564 assert(unused_tfb_object
== NULL
);
566 if (ctx
->Query
.CondRenderQuery
) {
567 perf_debug("Conditional rendering is implemented in software and may "
568 "stall. This should be fixed in the driver.\n");
571 if (!_mesa_check_conditional_render(ctx
))
574 /* Handle primitive restart if needed */
575 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
576 /* The draw was handled, so we can exit now */
580 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
581 * won't support all the extensions we support.
583 if (ctx
->RenderMode
!= GL_RENDER
) {
584 perf_debug("%s render mode not supported in hardware\n",
585 _mesa_lookup_enum_by_nr(ctx
->RenderMode
));
586 _swsetup_Wakeup(ctx
);
588 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
589 index_bounds_valid
, min_index
, max_index
, NULL
, NULL
);
593 /* If we're going to have to upload any of the user's vertex arrays, then
594 * get the minimum and maximum of their index buffer so we know what range
597 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
598 perf_debug("Scanning index buffer to compute index buffer bounds. "
599 "Use glDrawRangeElements() to avoid this.\n");
600 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
603 /* Try drawing with the hardware, but don't do anything else if we can't
604 * manage it. swrast doesn't support our featureset, so we can't fall back
607 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
, indirect
);
610 void brw_draw_init( struct brw_context
*brw
)
612 struct gl_context
*ctx
= &brw
->ctx
;
613 struct vbo_context
*vbo
= vbo_context(ctx
);
616 /* Register our drawing function:
618 vbo
->draw_prims
= brw_draw_prims
;
620 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
621 brw
->vb
.inputs
[i
].buffer
= -1;
622 brw
->vb
.nr_buffers
= 0;
623 brw
->vb
.nr_enabled
= 0;
626 void brw_draw_destroy( struct brw_context
*brw
)
630 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
631 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
632 brw
->vb
.buffers
[i
].bo
= NULL
;
634 brw
->vb
.nr_buffers
= 0;
636 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
637 brw
->vb
.enabled
[i
]->buffer
= -1;
639 brw
->vb
.nr_enabled
= 0;
641 drm_intel_bo_unreference(brw
->ib
.bo
);