1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <sys/errno.h>
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/condrender.h"
33 #include "main/samplerobj.h"
34 #include "main/state.h"
35 #include "main/enums.h"
36 #include "main/macros.h"
37 #include "main/transformfeedback.h"
39 #include "vbo/vbo_context.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
51 #include "intel_batchbuffer.h"
52 #include "intel_buffers.h"
53 #include "intel_fbo.h"
54 #include "intel_mipmap_tree.h"
55 #include "intel_buffer_objects.h"
57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
59 static const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
71 _3DPRIM_LINESTRIP_ADJ
,
77 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
91 get_hw_prim_for_gl_prim(int mode
)
93 if (mode
>= BRW_PRIM_OFFSET
)
94 return mode
- BRW_PRIM_OFFSET
;
96 assert(mode
< ARRAY_SIZE(prim_to_hw_prim
));
97 return prim_to_hw_prim
[mode
];
102 /* When the primitive changes, set a state bit and re-validate. Not
103 * the nicest and would rather deal with this by having all the
104 * programs be immune to the active primitive (ie. cope with all
105 * possibilities). That may not be realistic however.
108 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
110 struct gl_context
*ctx
= &brw
->ctx
;
111 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
113 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
115 /* Slight optimization to avoid the GS program when not needed:
117 if (prim
->mode
== GL_QUAD_STRIP
&&
118 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
119 ctx
->Polygon
.FrontMode
== GL_FILL
&&
120 ctx
->Polygon
.BackMode
== GL_FILL
)
121 hw_prim
= _3DPRIM_TRISTRIP
;
123 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
124 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
125 ctx
->Polygon
.FrontMode
== GL_FILL
&&
126 ctx
->Polygon
.BackMode
== GL_FILL
) {
127 hw_prim
= _3DPRIM_TRIFAN
;
130 if (hw_prim
!= brw
->primitive
) {
131 brw
->primitive
= hw_prim
;
132 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
134 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
135 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
136 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
142 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
144 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
146 const uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
147 if (hw_prim
!= brw
->primitive
) {
148 brw
->primitive
= hw_prim
;
149 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
155 * The hardware is capable of removing dangling vertices on its own; however,
156 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
157 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
158 * This function manually trims dangling vertices from a draw call involving
159 * quads so that those dangling vertices won't get drawn when we convert to
163 trim(GLenum prim
, GLuint length
)
165 if (prim
== GL_QUAD_STRIP
)
166 return length
> 3 ? (length
- length
% 2) : 0;
167 else if (prim
== GL_QUADS
)
168 return length
- length
% 4;
175 brw_emit_prim(struct brw_context
*brw
,
176 const struct _mesa_prim
*prim
,
179 int verts_per_instance
;
180 int vertex_access_type
;
183 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
184 prim
->start
, prim
->count
);
186 int start_vertex_location
= prim
->start
;
187 int base_vertex_location
= prim
->basevertex
;
190 vertex_access_type
= brw
->gen
>= 7 ?
191 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
192 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
193 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
194 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
196 vertex_access_type
= brw
->gen
>= 7 ?
197 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
198 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
199 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
202 /* We only need to trim the primitive count on pre-Gen6. */
204 verts_per_instance
= trim(prim
->mode
, prim
->count
);
206 verts_per_instance
= prim
->count
;
208 /* If nothing to emit, just return. */
209 if (verts_per_instance
== 0 && !prim
->is_indirect
)
212 /* If we're set to always flush, do it before and after the primitive emit.
213 * We want to catch both missed flushes that hurt instruction/state cache
214 * and missed flushes of the render cache as it heads to other parts of
215 * the besides the draw code.
217 if (brw
->always_flush_cache
)
218 brw_emit_mi_flush(brw
);
220 /* If indirect, emit a bunch of loads from the indirect BO. */
221 if (prim
->is_indirect
) {
222 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
223 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
224 intel_buffer_object(indirect_buffer
),
225 prim
->indirect_offset
, 5 * sizeof(GLuint
));
227 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
229 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
230 I915_GEM_DOMAIN_VERTEX
, 0,
231 prim
->indirect_offset
+ 0);
232 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
233 I915_GEM_DOMAIN_VERTEX
, 0,
234 prim
->indirect_offset
+ 4);
236 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
237 I915_GEM_DOMAIN_VERTEX
, 0,
238 prim
->indirect_offset
+ 8);
240 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
241 I915_GEM_DOMAIN_VERTEX
, 0,
242 prim
->indirect_offset
+ 12);
243 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
244 I915_GEM_DOMAIN_VERTEX
, 0,
245 prim
->indirect_offset
+ 16);
247 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
248 I915_GEM_DOMAIN_VERTEX
, 0,
249 prim
->indirect_offset
+ 12);
251 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
252 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
260 BEGIN_BATCH(brw
->gen
>= 7 ? 7 : 6);
263 const int predicate_enable
=
264 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
265 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
267 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
268 OUT_BATCH(hw_prim
| vertex_access_type
);
270 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
271 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
274 OUT_BATCH(verts_per_instance
);
275 OUT_BATCH(start_vertex_location
);
276 OUT_BATCH(prim
->num_instances
);
277 OUT_BATCH(prim
->base_instance
);
278 OUT_BATCH(base_vertex_location
);
281 if (brw
->always_flush_cache
)
282 brw_emit_mi_flush(brw
);
287 brw_merge_inputs(struct brw_context
*brw
,
288 const struct gl_client_array
*arrays
[])
290 const struct gl_context
*ctx
= &brw
->ctx
;
293 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
294 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
295 brw
->vb
.buffers
[i
].bo
= NULL
;
297 brw
->vb
.nr_buffers
= 0;
299 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
300 brw
->vb
.inputs
[i
].buffer
= -1;
301 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
304 if (brw
->gen
< 8 && !brw
->is_haswell
) {
305 struct gl_program
*vp
= &ctx
->VertexProgram
._Current
->Base
;
306 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
307 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
309 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
310 if (!(vp
->InputsRead
& BITFIELD64_BIT(i
)))
313 uint8_t wa_flags
= 0;
315 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
318 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
321 case GL_INT_2_10_10_10_REV
:
322 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
325 case GL_UNSIGNED_INT_2_10_10_10_REV
:
326 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
327 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
329 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
330 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
331 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
332 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
337 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
338 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
339 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
346 * \brief Call this after drawing to mark which buffers need resolving
348 * If the depth buffer was written to and if it has an accompanying HiZ
349 * buffer, then mark that it needs a depth resolve.
351 * If the color buffer is a multisample window system buffer, then
352 * mark that it needs a downsample.
354 * Also mark any render targets which will be textured as needing a render
358 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
360 struct gl_context
*ctx
= &brw
->ctx
;
361 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
363 struct intel_renderbuffer
*front_irb
= NULL
;
364 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
365 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
366 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
367 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
369 if (brw_is_front_buffer_drawing(fb
))
370 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
373 front_irb
->need_downsample
= true;
375 back_irb
->need_downsample
= true;
376 if (depth_irb
&& ctx
->Depth
.Mask
) {
377 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
378 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
381 if (ctx
->Extensions
.ARB_stencil_texturing
&&
382 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
383 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
386 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
387 struct intel_renderbuffer
*irb
=
388 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
391 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
395 /* May fail if out of video memory for texture or vbo upload, or on
396 * fallback conditions.
399 brw_try_draw_prims(struct gl_context
*ctx
,
400 const struct gl_client_array
*arrays
[],
401 const struct _mesa_prim
*prims
,
403 const struct _mesa_index_buffer
*ib
,
406 struct gl_buffer_object
*indirect
)
408 struct brw_context
*brw
= brw_context(ctx
);
410 bool fail_next
= false;
413 _mesa_update_state(ctx
);
415 /* Find the highest sampler unit used by each shader program. A bit-count
416 * won't work since ARB programs use the texture unit number as the sampler
419 brw
->wm
.base
.sampler_count
=
420 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
421 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
422 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
423 brw
->vs
.base
.sampler_count
=
424 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
426 /* We have to validate the textures *before* checking for fallbacks;
427 * otherwise, the software fallback won't be able to rely on the
428 * texture state, the firstLevel and lastLevel fields won't be
429 * set in the intel texture object (they'll both be 0), and the
430 * software fallback will segfault if it attempts to access any
431 * texture level other than level 0.
433 brw_validate_textures(brw
);
435 intel_prepare_render(brw
);
437 /* This workaround has to happen outside of brw_upload_render_state()
438 * because it may flush the batchbuffer for a blit, affecting the state
441 brw_workaround_depthstencil_alignment(brw
, 0);
443 /* Bind all inputs, derive varying and size information:
445 brw_merge_inputs(brw
, arrays
);
448 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
450 brw
->vb
.min_index
= min_index
;
451 brw
->vb
.max_index
= max_index
;
452 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
454 for (i
= 0; i
< nr_prims
; i
++) {
455 int estimated_max_prim_size
;
456 const int sampler_state_size
= 16;
458 estimated_max_prim_size
= 512; /* batchbuffer commands */
459 estimated_max_prim_size
+= BRW_MAX_TEX_UNIT
*
460 (sampler_state_size
+ sizeof(struct gen5_sampler_default_color
));
461 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
462 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
463 estimated_max_prim_size
+= 512; /* misc. pad */
465 /* Flush the batch if it's approaching full, so that we don't wrap while
466 * we've got validated state that needs to be in the same batch as the
469 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
470 intel_batchbuffer_save_state(brw
);
472 if (brw
->num_instances
!= prims
[i
].num_instances
||
473 brw
->basevertex
!= prims
[i
].basevertex
) {
474 brw
->num_instances
= prims
[i
].num_instances
;
475 brw
->basevertex
= prims
[i
].basevertex
;
476 if (i
> 0) { /* For i == 0 we just did this before the loop */
477 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
478 brw_merge_inputs(brw
, arrays
);
482 brw
->draw
.gl_basevertex
=
483 prims
[i
].indexed
? prims
[i
].basevertex
: prims
[i
].start
;
485 drm_intel_bo_unreference(brw
->draw
.draw_params_bo
);
487 if (prims
[i
].is_indirect
) {
488 /* Point draw_params_bo at the indirect buffer. */
489 brw
->draw
.draw_params_bo
=
490 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
491 drm_intel_bo_reference(brw
->draw
.draw_params_bo
);
492 brw
->draw
.draw_params_offset
=
493 prims
[i
].indirect_offset
+ (prims
[i
].indexed
? 12 : 8);
495 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
496 * has to upload gl_BaseVertex and such if they're needed.
498 brw
->draw
.draw_params_bo
= NULL
;
499 brw
->draw
.draw_params_offset
= 0;
503 brw_set_prim(brw
, &prims
[i
]);
505 gen6_set_prim(brw
, &prims
[i
]);
509 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
510 * that the state updated in the loop outside of this block is that in
511 * *_set_prim or intel_batchbuffer_flush(), which only impacts
512 * brw->ctx.NewDriverState.
514 if (brw
->ctx
.NewDriverState
) {
515 brw
->no_batch_wrap
= true;
516 brw_upload_render_state(brw
);
519 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
521 brw
->no_batch_wrap
= false;
523 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
525 intel_batchbuffer_reset_to_saved(brw
);
526 intel_batchbuffer_flush(brw
);
530 int ret
= intel_batchbuffer_flush(brw
);
531 WARN_ONCE(ret
== -ENOSPC
,
532 "i965: Single primitive emit exceeded "
533 "available aperture space\n");
537 /* Now that we know we haven't run out of aperture space, we can safely
538 * reset the dirty bits.
540 if (brw
->ctx
.NewDriverState
)
541 brw_render_state_finished(brw
);
544 if (brw
->always_flush_batch
)
545 intel_batchbuffer_flush(brw
);
547 brw_state_cache_check_size(brw
);
548 brw_postdraw_set_buffers_need_resolve(brw
);
554 brw_draw_prims(struct gl_context
*ctx
,
555 const struct _mesa_prim
*prims
,
557 const struct _mesa_index_buffer
*ib
,
558 GLboolean index_bounds_valid
,
561 struct gl_transform_feedback_object
*unused_tfb_object
,
563 struct gl_buffer_object
*indirect
)
565 struct brw_context
*brw
= brw_context(ctx
);
566 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
568 assert(unused_tfb_object
== NULL
);
570 if (!brw_check_conditional_render(brw
))
573 /* Handle primitive restart if needed */
574 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
575 /* The draw was handled, so we can exit now */
579 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
580 * won't support all the extensions we support.
582 if (ctx
->RenderMode
!= GL_RENDER
) {
583 perf_debug("%s render mode not supported in hardware\n",
584 _mesa_enum_to_string(ctx
->RenderMode
));
585 _swsetup_Wakeup(ctx
);
587 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
588 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
592 /* If we're going to have to upload any of the user's vertex arrays, then
593 * get the minimum and maximum of their index buffer so we know what range
596 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
597 perf_debug("Scanning index buffer to compute index buffer bounds. "
598 "Use glDrawRangeElements() to avoid this.\n");
599 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
602 /* Try drawing with the hardware, but don't do anything else if we can't
603 * manage it. swrast doesn't support our featureset, so we can't fall back
606 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
,
611 brw_draw_init(struct brw_context
*brw
)
613 struct gl_context
*ctx
= &brw
->ctx
;
614 struct vbo_context
*vbo
= vbo_context(ctx
);
616 /* Register our drawing function:
618 vbo
->draw_prims
= brw_draw_prims
;
620 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
621 brw
->vb
.inputs
[i
].buffer
= -1;
622 brw
->vb
.nr_buffers
= 0;
623 brw
->vb
.nr_enabled
= 0;
627 brw_draw_destroy(struct brw_context
*brw
)
631 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
632 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
633 brw
->vb
.buffers
[i
].bo
= NULL
;
635 brw
->vb
.nr_buffers
= 0;
637 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
638 brw
->vb
.enabled
[i
]->buffer
= -1;
640 brw
->vb
.nr_enabled
= 0;
642 drm_intel_bo_unreference(brw
->ib
.bo
);