2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/arrayobj.h"
29 #include "main/blend.h"
30 #include "main/context.h"
31 #include "main/condrender.h"
32 #include "main/samplerobj.h"
33 #include "main/state.h"
34 #include "main/enums.h"
35 #include "main/macros.h"
36 #include "main/transformfeedback.h"
37 #include "main/framebuffer.h"
38 #include "main/varray.h"
41 #include "swrast/swrast.h"
42 #include "swrast_setup/swrast_setup.h"
43 #include "drivers/common/meta.h"
44 #include "util/bitscan.h"
45 #include "util/bitset.h"
47 #include "brw_blorp.h"
49 #include "brw_defines.h"
50 #include "compiler/brw_eu_defines.h"
51 #include "brw_context.h"
52 #include "brw_state.h"
54 #include "intel_batchbuffer.h"
55 #include "intel_buffers.h"
56 #include "intel_fbo.h"
57 #include "intel_mipmap_tree.h"
58 #include "intel_buffer_objects.h"
60 #define FILE_DEBUG_FLAG DEBUG_PRIMS
63 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
64 [GL_POINTS
] = GL_POINTS
,
65 [GL_LINES
] = GL_LINES
,
66 [GL_LINE_LOOP
] = GL_LINES
,
67 [GL_LINE_STRIP
] = GL_LINES
,
68 [GL_TRIANGLES
] = GL_TRIANGLES
,
69 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
70 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
71 [GL_QUADS
] = GL_TRIANGLES
,
72 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
73 [GL_POLYGON
] = GL_TRIANGLES
76 /* When the primitive changes, set a state bit and re-validate. Not
77 * the nicest and would rather deal with this by having all the
78 * programs be immune to the active primitive (ie. cope with all
79 * possibilities). That may not be realistic however.
82 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
84 struct gl_context
*ctx
= &brw
->ctx
;
85 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
87 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
89 /* Slight optimization to avoid the GS program when not needed:
91 if (prim
->mode
== GL_QUAD_STRIP
&&
92 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
93 ctx
->Polygon
.FrontMode
== GL_FILL
&&
94 ctx
->Polygon
.BackMode
== GL_FILL
)
95 hw_prim
= _3DPRIM_TRISTRIP
;
97 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
98 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
99 ctx
->Polygon
.FrontMode
== GL_FILL
&&
100 ctx
->Polygon
.BackMode
== GL_FILL
) {
101 hw_prim
= _3DPRIM_TRIFAN
;
104 if (hw_prim
!= brw
->primitive
) {
105 brw
->primitive
= hw_prim
;
106 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
108 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
109 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
110 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
116 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
118 const struct gl_context
*ctx
= &brw
->ctx
;
121 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
123 if (prim
->mode
== GL_PATCHES
) {
124 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
126 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
129 if (hw_prim
!= brw
->primitive
) {
130 brw
->primitive
= hw_prim
;
131 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
132 if (prim
->mode
== GL_PATCHES
)
133 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
139 * The hardware is capable of removing dangling vertices on its own; however,
140 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
141 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
142 * This function manually trims dangling vertices from a draw call involving
143 * quads so that those dangling vertices won't get drawn when we convert to
147 trim(GLenum prim
, GLuint length
)
149 if (prim
== GL_QUAD_STRIP
)
150 return length
> 3 ? (length
- length
% 2) : 0;
151 else if (prim
== GL_QUADS
)
152 return length
- length
% 4;
159 brw_emit_prim(struct brw_context
*brw
,
160 const struct _mesa_prim
*prim
,
163 GLuint num_instances
, GLuint base_instance
,
164 struct brw_transform_feedback_object
*xfb_obj
,
167 GLsizeiptr indirect_offset
)
169 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
170 int verts_per_instance
;
171 int vertex_access_type
;
174 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
175 prim
->start
, prim
->count
);
177 int start_vertex_location
= prim
->start
;
178 int base_vertex_location
= prim
->basevertex
;
181 vertex_access_type
= devinfo
->gen
>= 7 ?
182 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
183 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
184 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
185 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
187 vertex_access_type
= devinfo
->gen
>= 7 ?
188 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
189 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
190 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
193 /* We only need to trim the primitive count on pre-Gen6. */
194 if (devinfo
->gen
< 6)
195 verts_per_instance
= trim(prim
->mode
, prim
->count
);
197 verts_per_instance
= prim
->count
;
199 /* If nothing to emit, just return. */
200 if (verts_per_instance
== 0 && !is_indirect
&& !xfb_obj
)
203 /* If we're set to always flush, do it before and after the primitive emit.
204 * We want to catch both missed flushes that hurt instruction/state cache
205 * and missed flushes of the render cache as it heads to other parts of
206 * the besides the draw code.
208 if (brw
->always_flush_cache
)
209 brw_emit_mi_flush(brw
);
211 /* If indirect, emit a bunch of loads from the indirect BO. */
213 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
215 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
216 xfb_obj
->prim_count_bo
,
217 stream
* sizeof(uint32_t));
219 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
220 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
221 OUT_BATCH(num_instances
);
222 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
224 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
226 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
229 } else if (is_indirect
) {
230 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
231 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
232 intel_buffer_object(indirect_buffer
),
233 indirect_offset
, 5 * sizeof(GLuint
), false);
235 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
237 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
238 indirect_offset
+ 0);
239 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
240 indirect_offset
+ 4);
242 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
243 indirect_offset
+ 8);
245 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
246 indirect_offset
+ 12);
247 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
248 indirect_offset
+ 16);
250 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
251 indirect_offset
+ 12);
252 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
258 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
260 if (devinfo
->gen
>= 7) {
261 const int predicate_enable
=
262 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
263 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
265 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
266 OUT_BATCH(hw_prim
| vertex_access_type
);
268 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
269 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
272 OUT_BATCH(verts_per_instance
);
273 OUT_BATCH(start_vertex_location
);
274 OUT_BATCH(num_instances
);
275 OUT_BATCH(base_instance
);
276 OUT_BATCH(base_vertex_location
);
279 if (brw
->always_flush_cache
)
280 brw_emit_mi_flush(brw
);
285 brw_clear_buffers(struct brw_context
*brw
)
287 for (unsigned i
= 0; i
< brw
->vb
.nr_buffers
; ++i
) {
288 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
289 brw
->vb
.buffers
[i
].bo
= NULL
;
291 brw
->vb
.nr_buffers
= 0;
293 for (unsigned i
= 0; i
< brw
->vb
.nr_enabled
; ++i
) {
294 brw
->vb
.enabled
[i
]->buffer
= -1;
297 for (unsigned i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
298 assert(brw
->vb
.inputs
[i
].buffer
== -1);
305 brw_merge_inputs(struct brw_context
*brw
)
307 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
308 const struct gl_context
*ctx
= &brw
->ctx
;
310 for (unsigned i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
311 struct brw_vertex_element
*input
= &brw
->vb
.inputs
[i
];
312 _mesa_draw_attrib_and_binding(ctx
, i
,
313 &input
->glattrib
, &input
->glbinding
);
316 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
317 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
318 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
319 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
322 const struct gl_vertex_format
*glformat
;
323 uint8_t wa_flags
= 0;
324 const gl_vert_attrib i
= u_bit_scan64(&mask
);
326 glformat
= &brw
->vb
.inputs
[i
].glattrib
->Format
;
328 switch (glformat
->Type
) {
331 wa_flags
= glformat
->Size
;
334 case GL_INT_2_10_10_10_REV
:
335 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
338 case GL_UNSIGNED_INT_2_10_10_10_REV
:
339 if (glformat
->Format
== GL_BGRA
)
340 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
342 if (glformat
->Normalized
)
343 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
344 else if (!glformat
->Integer
)
345 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
350 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
351 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
352 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
358 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
359 * or shader image. This causes a self-dependency, where both rendering
360 * and sampling may concurrently read or write the CCS buffer, causing
364 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
365 bool *draw_aux_buffer_disabled
,
366 struct intel_mipmap_tree
*tex_mt
,
367 unsigned min_level
, unsigned num_levels
,
370 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
373 /* We only need to worry about color compression and fast clears. */
374 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
375 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
378 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
379 const struct intel_renderbuffer
*irb
=
380 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
382 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
383 irb
->mt_level
>= min_level
&&
384 irb
->mt_level
< min_level
+ num_levels
) {
385 found
= draw_aux_buffer_disabled
[i
] = true;
390 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
397 /** Implement the ASTC 5x5 sampler workaround
399 * Gen9 sampling hardware has a bug where an ASTC 5x5 compressed surface
400 * cannot live in the sampler cache at the same time as an aux compressed
401 * surface. In order to work around the bug we have to stall rendering with a
402 * CS and pixel scoreboard stall (implicit in the CS stall) and invalidate the
403 * texture cache whenever one of ASTC 5x5 or aux compressed may be in the
404 * sampler cache and we're about to render with something which samples from
407 * In the case of a single shader which textures from both ASTC 5x5 and
408 * a texture which is CCS or HiZ compressed, we have to resolve the aux
409 * compressed texture prior to rendering. This second part is handled in
410 * brw_predraw_resolve_inputs() below.
412 * We have observed this issue to affect CCS and HiZ sampling but whether or
413 * not it also affects MCS is unknown. Because MCS has no concept of a
414 * resolve (and doing one would be stupid expensive), we choose to simply
415 * ignore the possibility and hope for the best.
418 gen9_apply_astc5x5_wa_flush(struct brw_context
*brw
,
419 enum gen9_astc5x5_wa_tex_type curr_mask
)
421 assert(brw
->screen
->devinfo
.gen
== 9);
423 if (((brw
->gen9_astc5x5_wa_tex_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
424 (curr_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_AUX
)) ||
425 ((brw
->gen9_astc5x5_wa_tex_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_AUX
) &&
426 (curr_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
))) {
427 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
428 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
431 brw
->gen9_astc5x5_wa_tex_mask
= curr_mask
;
434 static enum gen9_astc5x5_wa_tex_type
435 gen9_astc5x5_wa_bits(mesa_format format
, enum isl_aux_usage aux_usage
)
437 if (aux_usage
!= ISL_AUX_USAGE_NONE
&&
438 aux_usage
!= ISL_AUX_USAGE_MCS
)
439 return GEN9_ASTC5X5_WA_TEX_TYPE_AUX
;
441 if (format
== MESA_FORMAT_RGBA_ASTC_5x5
||
442 format
== MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5
)
443 return GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
;
448 /* Helper for the gen9 ASTC 5x5 workaround. This version exists for BLORP's
449 * use-cases where only a single texture is bound.
452 gen9_apply_single_tex_astc5x5_wa(struct brw_context
*brw
,
454 enum isl_aux_usage aux_usage
)
456 gen9_apply_astc5x5_wa_flush(brw
, gen9_astc5x5_wa_bits(format
, aux_usage
));
460 mark_textures_used_for_txf(BITSET_WORD
*used_for_txf
,
461 const struct gl_program
*prog
)
466 uint32_t mask
= prog
->info
.textures_used_by_txf
;
468 int s
= u_bit_scan(&mask
);
469 BITSET_SET(used_for_txf
, prog
->SamplerUnits
[s
]);
474 * \brief Resolve buffers before drawing.
476 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
477 * enabled depth texture, and flush the render cache for any dirty textures.
480 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
481 bool *draw_aux_buffer_disabled
)
483 struct gl_context
*ctx
= &brw
->ctx
;
484 struct intel_texture_object
*tex_obj
;
486 BITSET_DECLARE(used_for_txf
, MAX_COMBINED_TEXTURE_IMAGE_UNITS
);
487 memset(used_for_txf
, 0, sizeof(used_for_txf
));
489 mark_textures_used_for_txf(used_for_txf
, ctx
->VertexProgram
._Current
);
490 mark_textures_used_for_txf(used_for_txf
, ctx
->TessCtrlProgram
._Current
);
491 mark_textures_used_for_txf(used_for_txf
, ctx
->TessEvalProgram
._Current
);
492 mark_textures_used_for_txf(used_for_txf
, ctx
->GeometryProgram
._Current
);
493 mark_textures_used_for_txf(used_for_txf
, ctx
->FragmentProgram
._Current
);
495 mark_textures_used_for_txf(used_for_txf
, ctx
->ComputeProgram
._Current
);
498 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
500 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
= 0;
501 if (brw
->screen
->devinfo
.gen
== 9) {
502 /* In order to properly implement the ASTC 5x5 workaround for an
503 * arbitrary draw or dispatch call, we have to walk the entire list of
504 * textures looking for ASTC 5x5. If there is any ASTC 5x5 in this draw
505 * call, all aux compressed textures must be resolved and have aux
506 * compression disabled while sampling.
508 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
509 if (!ctx
->Texture
.Unit
[i
]._Current
)
511 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
512 if (!tex_obj
|| !tex_obj
->mt
)
515 astc5x5_wa_bits
|= gen9_astc5x5_wa_bits(tex_obj
->_Format
,
516 tex_obj
->mt
->aux_usage
);
518 gen9_apply_astc5x5_wa_flush(brw
, astc5x5_wa_bits
);
521 /* Resolve depth buffer and render cache of each enabled texture. */
522 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
523 if (!ctx
->Texture
.Unit
[i
]._Current
)
525 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
526 if (!tex_obj
|| !tex_obj
->mt
)
529 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
530 enum isl_format view_format
=
531 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
533 unsigned min_level
, min_layer
, num_levels
, num_layers
;
534 if (tex_obj
->base
.Immutable
) {
535 min_level
= tex_obj
->base
.MinLevel
;
536 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
537 min_layer
= tex_obj
->base
.MinLayer
;
538 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
539 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
541 min_level
= tex_obj
->base
.BaseLevel
;
542 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
544 num_layers
= INTEL_REMAINING_LAYERS
;
548 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
549 tex_obj
->mt
, min_level
, num_levels
,
553 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
554 min_level
, num_levels
,
555 min_layer
, num_layers
,
558 /* If any programs are using it with texelFetch, we may need to also do
559 * a prepare with an sRGB format to ensure texelFetch works "properly".
561 if (BITSET_TEST(used_for_txf
, i
)) {
562 enum isl_format txf_format
=
563 translate_tex_format(brw
, tex_obj
->_Format
, GL_DECODE_EXT
);
564 if (txf_format
!= view_format
) {
565 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, txf_format
,
566 min_level
, num_levels
,
567 min_layer
, num_layers
,
572 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
574 if (tex_obj
->base
.StencilSampling
||
575 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
576 intel_update_r8stencil(brw
, tex_obj
->mt
);
579 if (intel_miptree_has_etc_shadow(brw
, tex_obj
->mt
) &&
580 tex_obj
->mt
->shadow_needs_update
) {
581 intel_miptree_update_etc_shadow_levels(brw
, tex_obj
->mt
);
585 /* Resolve color for each active shader image. */
586 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
587 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
589 if (unlikely(prog
&& prog
->info
.num_images
)) {
590 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
591 struct gl_image_unit
*u
=
592 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
593 tex_obj
= intel_texture_object(u
->TexObj
);
595 if (tex_obj
&& tex_obj
->mt
) {
597 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
599 "as a shader image");
602 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
604 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
612 brw_predraw_resolve_framebuffer(struct brw_context
*brw
,
613 bool *draw_aux_buffer_disabled
)
615 struct gl_context
*ctx
= &brw
->ctx
;
616 struct intel_renderbuffer
*depth_irb
;
618 /* Resolve the depth buffer's HiZ buffer. */
619 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
620 if (depth_irb
&& depth_irb
->mt
) {
621 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
624 depth_irb
->layer_count
);
627 /* Resolve color buffers for non-coherent framebuffer fetch. */
628 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
&&
629 ctx
->FragmentProgram
._Current
&&
630 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
631 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
633 /* This is only used for non-coherent framebuffer fetch, so we don't
634 * need to worry about CCS_E and can simply pass 'false' below.
636 assert(brw
->screen
->devinfo
.gen
< 9);
638 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
639 const struct intel_renderbuffer
*irb
=
640 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
643 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
645 irb
->mt_layer
, irb
->layer_count
,
646 brw
->gen9_astc5x5_wa_tex_mask
);
651 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
652 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
653 struct intel_renderbuffer
*irb
=
654 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
656 if (irb
== NULL
|| irb
->mt
== NULL
)
659 mesa_format mesa_format
=
660 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
661 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
662 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
663 enum isl_aux_usage aux_usage
=
664 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
666 draw_aux_buffer_disabled
[i
]);
667 if (brw
->draw_aux_usage
[i
] != aux_usage
) {
668 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
669 brw
->draw_aux_usage
[i
] = aux_usage
;
672 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
673 irb
->mt_layer
, irb
->layer_count
,
676 brw_cache_flush_for_render(brw
, irb
->mt
->bo
,
677 isl_format
, aux_usage
);
682 * \brief Call this after drawing to mark which buffers need resolving
684 * If the depth buffer was written to and if it has an accompanying HiZ
685 * buffer, then mark that it needs a depth resolve.
687 * If the stencil buffer was written to then mark that it may need to be
688 * copied to an R8 texture.
690 * If the color buffer is a multisample window system buffer, then
691 * mark that it needs a downsample.
693 * Also mark any render targets which will be textured as needing a render
697 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
699 struct gl_context
*ctx
= &brw
->ctx
;
700 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
702 struct intel_renderbuffer
*front_irb
= NULL
;
703 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
704 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
705 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
706 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
708 if (_mesa_is_front_buffer_drawing(fb
))
709 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
712 front_irb
->need_downsample
= true;
714 back_irb
->need_downsample
= true;
716 bool depth_written
= brw_depth_writes_enabled(brw
);
717 if (depth_att
->Layered
) {
718 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
721 depth_irb
->layer_count
,
724 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
726 depth_irb
->mt_layer
, 1,
730 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
733 if (stencil_irb
&& brw
->stencil_write_enabled
) {
734 struct intel_mipmap_tree
*stencil_mt
=
735 stencil_irb
->mt
->stencil_mt
!= NULL
?
736 stencil_irb
->mt
->stencil_mt
: stencil_irb
->mt
;
737 brw_depth_cache_add_bo(brw
, stencil_mt
->bo
);
738 intel_miptree_finish_write(brw
, stencil_mt
, stencil_irb
->mt_level
,
739 stencil_irb
->mt_layer
,
740 stencil_irb
->layer_count
, ISL_AUX_USAGE_NONE
);
743 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
744 struct intel_renderbuffer
*irb
=
745 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
750 mesa_format mesa_format
=
751 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
752 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
753 enum isl_aux_usage aux_usage
= brw
->draw_aux_usage
[i
];
755 brw_render_cache_add_bo(brw
, irb
->mt
->bo
, isl_format
, aux_usage
);
757 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
758 irb
->mt_layer
, irb
->layer_count
,
764 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
765 struct intel_renderbuffer
*irb
)
767 if (irb
->align_wa_mt
== NULL
)
770 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
772 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
774 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
776 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
778 /* Finally restore the x,y to correspond to full miptree. */
779 intel_renderbuffer_set_draw_offset(irb
);
781 /* Make sure render surface state gets re-emitted with updated miptree. */
782 brw
->NewGLState
|= _NEW_BUFFERS
;
786 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
788 struct gl_context
*ctx
= &brw
->ctx
;
789 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
791 struct intel_renderbuffer
*depth_irb
=
792 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
793 struct intel_renderbuffer
*stencil_irb
=
794 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
796 if (depth_irb
&& depth_irb
->align_wa_mt
)
797 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
799 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
800 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
802 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
803 struct intel_renderbuffer
*irb
=
804 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
806 if (!irb
|| irb
->align_wa_mt
== NULL
)
809 intel_renderbuffer_move_temp_back(brw
, irb
);
814 brw_prepare_drawing(struct gl_context
*ctx
,
815 const struct _mesa_index_buffer
*ib
,
816 bool index_bounds_valid
,
820 struct brw_context
*brw
= brw_context(ctx
);
823 _mesa_update_state(ctx
);
825 /* We have to validate the textures *before* checking for fallbacks;
826 * otherwise, the software fallback won't be able to rely on the
827 * texture state, the firstLevel and lastLevel fields won't be
828 * set in the intel texture object (they'll both be 0), and the
829 * software fallback will segfault if it attempts to access any
830 * texture level other than level 0.
832 brw_validate_textures(brw
);
834 /* Find the highest sampler unit used by each shader program. A bit-count
835 * won't work since ARB programs use the texture unit number as the sampler
838 brw
->wm
.base
.sampler_count
=
839 util_last_bit(ctx
->FragmentProgram
._Current
->info
.textures_used
);
840 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
841 util_last_bit(ctx
->GeometryProgram
._Current
->info
.textures_used
) : 0;
842 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
843 util_last_bit(ctx
->TessEvalProgram
._Current
->info
.textures_used
) : 0;
844 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
845 util_last_bit(ctx
->TessCtrlProgram
._Current
->info
.textures_used
) : 0;
846 brw
->vs
.base
.sampler_count
=
847 util_last_bit(ctx
->VertexProgram
._Current
->info
.textures_used
);
849 intel_prepare_render(brw
);
851 /* This workaround has to happen outside of brw_upload_render_state()
852 * because it may flush the batchbuffer for a blit, affecting the state
855 brw_workaround_depthstencil_alignment(brw
, 0);
857 /* Resolves must occur after updating renderbuffers, updating context state,
858 * and finalizing textures but before setting up any hardware state for
861 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
] = { };
862 brw_predraw_resolve_inputs(brw
, true, draw_aux_buffer_disabled
);
863 brw_predraw_resolve_framebuffer(brw
, draw_aux_buffer_disabled
);
865 /* Bind all inputs, derive varying and size information:
867 brw_clear_buffers(brw
);
868 brw_merge_inputs(brw
);
871 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
873 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
874 brw
->vb
.min_index
= min_index
;
875 brw
->vb
.max_index
= max_index
;
876 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
880 brw_finish_drawing(struct gl_context
*ctx
)
882 struct brw_context
*brw
= brw_context(ctx
);
884 if (brw
->always_flush_batch
)
885 intel_batchbuffer_flush(brw
);
887 brw_program_cache_check_size(brw
);
888 brw_postdraw_reconcile_align_wa_slices(brw
);
889 brw_postdraw_set_buffers_need_resolve(brw
);
891 if (brw
->draw
.draw_params_count_bo
) {
892 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
893 brw
->draw
.draw_params_count_bo
= NULL
;
896 if (brw
->draw
.draw_params_bo
) {
897 brw_bo_unreference(brw
->draw
.draw_params_bo
);
898 brw
->draw
.draw_params_bo
= NULL
;
901 if (brw
->draw
.derived_draw_params_bo
) {
902 brw_bo_unreference(brw
->draw
.derived_draw_params_bo
);
903 brw
->draw
.derived_draw_params_bo
= NULL
;
908 * Implement workarounds for preemption:
909 * - WaDisableMidObjectPreemptionForGSLineStripAdj
910 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
911 * - WaDisableMidObjectPreemptionForLineLoop
915 gen9_emit_preempt_wa(struct brw_context
*brw
,
916 const struct _mesa_prim
*prim
, GLuint num_instances
)
918 bool object_preemption
= true;
919 ASSERTED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
921 /* Only apply these workarounds for gen9 */
922 assert(devinfo
->gen
== 9);
924 /* WaDisableMidObjectPreemptionForGSLineStripAdj
926 * WA: Disable mid-draw preemption when draw-call is a linestrip_adj and
929 if (brw
->primitive
== _3DPRIM_LINESTRIP_ADJ
&& brw
->gs
.enabled
)
930 object_preemption
= false;
932 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
934 * TriFan miscompare in Execlist Preemption test. Cut index that is on a
935 * previous context. End the previous, the resume another context with a
936 * tri-fan or polygon, and the vertex count is corrupted. If we prempt
937 * again we will cause corruption.
939 * WA: Disable mid-draw preemption when draw-call has a tri-fan.
941 if (brw
->primitive
== _3DPRIM_TRIFAN
)
942 object_preemption
= false;
944 /* WaDisableMidObjectPreemptionForLineLoop
946 * VF Stats Counters Missing a vertex when preemption enabled.
948 * WA: Disable mid-draw preemption when the draw uses a lineloop
951 if (brw
->primitive
== _3DPRIM_LINELOOP
)
952 object_preemption
= false;
956 * VF is corrupting GAFS data when preempted on an instance boundary and
957 * replayed with instancing enabled.
959 * WA: Disable preemption when using instanceing.
961 if (num_instances
> 1)
962 object_preemption
= false;
964 brw_enable_obj_preemption(brw
, object_preemption
);
967 /* May fail if out of video memory for texture or vbo upload, or on
968 * fallback conditions.
971 brw_draw_single_prim(struct gl_context
*ctx
,
972 const struct _mesa_prim
*prim
,
975 GLuint num_instances
, GLuint base_instance
,
976 struct brw_transform_feedback_object
*xfb_obj
,
978 GLsizeiptr indirect_offset
)
980 struct brw_context
*brw
= brw_context(ctx
);
981 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
983 bool is_indirect
= brw
->draw
.draw_indirect_data
!= NULL
;
985 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
986 * atoms that happen on every draw call.
988 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
990 /* Flush the batch if the batch/state buffers are nearly full. We can
991 * grow them if needed, but this is not free, so we'd like to avoid it.
993 intel_batchbuffer_require_space(brw
, 1500);
994 brw_require_statebuffer_space(brw
, 2400);
995 intel_batchbuffer_save_state(brw
);
996 fail_next
= intel_batchbuffer_saved_state_is_empty(brw
);
998 if (brw
->num_instances
!= num_instances
||
999 brw
->basevertex
!= prim
->basevertex
||
1000 brw
->baseinstance
!= base_instance
) {
1001 brw
->num_instances
= num_instances
;
1002 brw
->basevertex
= prim
->basevertex
;
1003 brw
->baseinstance
= base_instance
;
1004 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
1005 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
1006 brw_clear_buffers(brw
);
1010 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
1011 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
1012 * always flag if the shader uses one of the values. For direct draws,
1013 * we only flag if the values change.
1015 const int new_firstvertex
=
1016 is_indexed
? prim
->basevertex
: prim
->start
;
1017 const int new_baseinstance
= base_instance
;
1018 const struct brw_vs_prog_data
*vs_prog_data
=
1019 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
1021 const bool uses_draw_parameters
=
1022 vs_prog_data
->uses_firstvertex
||
1023 vs_prog_data
->uses_baseinstance
;
1025 if ((uses_draw_parameters
&& is_indirect
) ||
1026 (vs_prog_data
->uses_firstvertex
&&
1027 brw
->draw
.params
.firstvertex
!= new_firstvertex
) ||
1028 (vs_prog_data
->uses_baseinstance
&&
1029 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
1030 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
1033 brw
->draw
.params
.firstvertex
= new_firstvertex
;
1034 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
1035 brw_bo_unreference(brw
->draw
.draw_params_bo
);
1038 /* Point draw_params_bo at the indirect buffer. */
1039 brw
->draw
.draw_params_bo
=
1040 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
1041 brw_bo_reference(brw
->draw
.draw_params_bo
);
1042 brw
->draw
.draw_params_offset
=
1043 indirect_offset
+ (is_indexed
? 12 : 8);
1045 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
1046 * has to upload gl_BaseVertex and such if they're needed.
1048 brw
->draw
.draw_params_bo
= NULL
;
1049 brw
->draw
.draw_params_offset
= 0;
1052 /* gl_DrawID always needs its own vertex buffer since it's not part of
1053 * the indirect parameter buffer. Same for is_indexed_draw, which shares
1054 * the buffer with gl_DrawID. If the program uses gl_DrawID, we need to
1055 * flag BRW_NEW_VERTICES. For the first iteration, we don't have valid
1056 * vs_prog_data, but we always flag BRW_NEW_VERTICES before the loop.
1058 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
1059 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
1061 brw
->draw
.derived_params
.gl_drawid
= prim
->draw_id
;
1062 brw
->draw
.derived_params
.is_indexed_draw
= is_indexed
? ~0 : 0;
1064 brw_bo_unreference(brw
->draw
.derived_draw_params_bo
);
1065 brw
->draw
.derived_draw_params_bo
= NULL
;
1066 brw
->draw
.derived_draw_params_offset
= 0;
1068 if (devinfo
->gen
< 6)
1069 brw_set_prim(brw
, prim
);
1071 gen6_set_prim(brw
, prim
);
1075 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
1076 * that the state updated in the loop outside of this block is that in
1077 * *_set_prim or intel_batchbuffer_flush(), which only impacts
1078 * brw->ctx.NewDriverState.
1080 if (brw
->ctx
.NewDriverState
) {
1081 brw
->batch
.no_wrap
= true;
1082 brw_upload_render_state(brw
);
1085 if (devinfo
->gen
== 9)
1086 gen9_emit_preempt_wa(brw
, prim
, num_instances
);
1088 brw_emit_prim(brw
, prim
, brw
->primitive
, is_indexed
, num_instances
,
1089 base_instance
, xfb_obj
, stream
, is_indirect
,
1092 brw
->batch
.no_wrap
= false;
1094 if (!brw_batch_has_aperture_space(brw
, 0)) {
1096 intel_batchbuffer_reset_to_saved(brw
);
1097 intel_batchbuffer_flush(brw
);
1101 int ret
= intel_batchbuffer_flush(brw
);
1102 WARN_ONCE(ret
== -ENOSPC
,
1103 "i965: Single primitive emit exceeded "
1104 "available aperture space\n");
1108 /* Now that we know we haven't run out of aperture space, we can safely
1109 * reset the dirty bits.
1111 if (brw
->ctx
.NewDriverState
)
1112 brw_render_state_finished(brw
);
1120 brw_draw_prims(struct gl_context
*ctx
,
1121 const struct _mesa_prim
*prims
,
1123 const struct _mesa_index_buffer
*ib
,
1124 GLboolean index_bounds_valid
,
1127 GLuint num_instances
,
1128 GLuint base_instance
,
1129 struct gl_transform_feedback_object
*gl_xfb_obj
,
1133 struct brw_context
*brw
= brw_context(ctx
);
1134 int predicate_state
= brw
->predicate
.state
;
1135 struct brw_transform_feedback_object
*xfb_obj
=
1136 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
1138 if (!brw_check_conditional_render(brw
))
1141 /* Handle primitive restart if needed */
1142 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, num_instances
,
1144 /* The draw was handled, so we can exit now */
1148 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
1149 * won't support all the extensions we support.
1151 if (ctx
->RenderMode
!= GL_RENDER
) {
1152 perf_debug("%s render mode not supported in hardware\n",
1153 _mesa_enum_to_string(ctx
->RenderMode
));
1154 _swsetup_Wakeup(ctx
);
1156 _tnl_draw(ctx
, prims
, nr_prims
, ib
, index_bounds_valid
, min_index
,
1157 max_index
, num_instances
, base_instance
, NULL
, 0);
1161 /* If we're going to have to upload any of the user's vertex arrays, then
1162 * get the minimum and maximum of their index buffer so we know what range
1165 if (!index_bounds_valid
&& _mesa_draw_user_array_bits(ctx
) != 0) {
1166 perf_debug("Scanning index buffer to compute index buffer bounds. "
1167 "Use glDrawRangeElements() to avoid this.\n");
1168 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
1169 index_bounds_valid
= true;
1172 brw_prepare_drawing(ctx
, ib
, index_bounds_valid
, min_index
, max_index
);
1173 /* Try drawing with the hardware, but don't do anything else if we can't
1174 * manage it. swrast doesn't support our featureset, so we can't fall back
1178 for (i
= 0; i
< nr_prims
; i
++) {
1179 /* Implementation of ARB_indirect_parameters via predicates */
1180 if (brw
->draw
.draw_params_count_bo
) {
1181 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
1183 /* Upload the current draw count from the draw parameters buffer to
1184 * MI_PREDICATE_SRC0.
1186 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
1187 brw
->draw
.draw_params_count_bo
,
1188 brw
->draw
.draw_params_count_offset
);
1189 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
1190 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
1191 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
1192 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
1195 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
1196 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
1197 MI_PREDICATE_COMBINEOP_SET
|
1198 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1200 OUT_BATCH(GEN7_MI_PREDICATE
|
1201 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
1202 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1206 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
1209 brw_draw_single_prim(ctx
, &prims
[i
], i
, ib
!= NULL
, num_instances
,
1210 base_instance
, xfb_obj
, stream
,
1211 brw
->draw
.draw_indirect_offset
+
1212 brw
->draw
.draw_indirect_stride
* i
);
1215 brw_finish_drawing(ctx
);
1216 brw
->predicate
.state
= predicate_state
;
1220 brw_draw_indirect_prims(struct gl_context
*ctx
,
1222 struct gl_buffer_object
*indirect_data
,
1223 GLsizeiptr indirect_offset
,
1224 unsigned draw_count
,
1226 struct gl_buffer_object
*indirect_params
,
1227 GLsizeiptr indirect_params_offset
,
1228 const struct _mesa_index_buffer
*ib
)
1230 struct brw_context
*brw
= brw_context(ctx
);
1231 struct _mesa_prim
*prim
;
1234 prim
= calloc(draw_count
, sizeof(*prim
));
1236 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
1237 (draw_count
> 1) ? "Multi" : "",
1238 ib
? "Elements" : "Arrays",
1239 indirect_params
? "CountARB" : "");
1243 brw
->draw
.draw_indirect_stride
= stride
;
1244 brw
->draw
.draw_indirect_offset
= indirect_offset
;
1247 prim
[draw_count
- 1].end
= 1;
1248 for (i
= 0; i
< draw_count
; ++i
) {
1249 prim
[i
].mode
= mode
;
1250 prim
[i
].draw_id
= i
;
1253 if (indirect_params
) {
1254 brw
->draw
.draw_params_count_bo
=
1255 intel_buffer_object(indirect_params
)->buffer
;
1256 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
1257 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
1260 brw
->draw
.draw_indirect_data
= indirect_data
;
1262 brw_draw_prims(ctx
, prim
, draw_count
, ib
, false, 0, ~0, 0, 0, NULL
, 0);
1264 brw
->draw
.draw_indirect_data
= NULL
;
1269 brw_init_draw_functions(struct dd_function_table
*functions
)
1271 /* Register our drawing function:
1273 functions
->Draw
= brw_draw_prims
;
1274 functions
->DrawIndirect
= brw_draw_indirect_prims
;
1278 brw_draw_init(struct brw_context
*brw
)
1280 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1281 brw
->vb
.inputs
[i
].buffer
= -1;
1282 brw
->vb
.nr_buffers
= 0;
1283 brw
->vb
.nr_enabled
= 0;
1287 brw_draw_destroy(struct brw_context
*brw
)
1291 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1292 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1293 brw
->vb
.buffers
[i
].bo
= NULL
;
1295 brw
->vb
.nr_buffers
= 0;
1297 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1298 brw
->vb
.enabled
[i
]->buffer
= -1;
1300 brw
->vb
.nr_enabled
= 0;
1302 brw_bo_unreference(brw
->ib
.bo
);