src/mesa/drivers/dri/i965/brw_draw_upload.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #undef NDEBUG
  29
  30 #include "main/glheader.h"
  31 #include "main/bufferobj.h"
  32 #include "main/context.h"
  33 #include "main/enums.h"
  34 #include "main/macros.h"
  35
  36 #include "brw_draw.h"
  37 #include "brw_defines.h"
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40
  41 #include "intel_batchbuffer.h"
  42 #include "intel_buffer_objects.h"
  43
  44 static GLuint double_types[5] = {
  45    0,
  46    BRW_SURFACEFORMAT_R64_FLOAT,
  47    BRW_SURFACEFORMAT_R64G64_FLOAT,
  48    BRW_SURFACEFORMAT_R64G64B64_FLOAT,
  49    BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
  50 };
  51
  52 static GLuint float_types[5] = {
  53    0,
  54    BRW_SURFACEFORMAT_R32_FLOAT,
  55    BRW_SURFACEFORMAT_R32G32_FLOAT,
  56    BRW_SURFACEFORMAT_R32G32B32_FLOAT,
  57    BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
  58 };
  59
  60 static GLuint half_float_types[5] = {
  61    0,
  62    BRW_SURFACEFORMAT_R16_FLOAT,
  63    BRW_SURFACEFORMAT_R16G16_FLOAT,
  64    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
  65    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
  66 };
  67
  68 static GLuint uint_types_direct[5] = {
  69    0,
  70    BRW_SURFACEFORMAT_R32_UINT,
  71    BRW_SURFACEFORMAT_R32G32_UINT,
  72    BRW_SURFACEFORMAT_R32G32B32_UINT,
  73    BRW_SURFACEFORMAT_R32G32B32A32_UINT
  74 };
  75
  76 static GLuint uint_types_norm[5] = {
  77    0,
  78    BRW_SURFACEFORMAT_R32_UNORM,
  79    BRW_SURFACEFORMAT_R32G32_UNORM,
  80    BRW_SURFACEFORMAT_R32G32B32_UNORM,
  81    BRW_SURFACEFORMAT_R32G32B32A32_UNORM
  82 };
  83
  84 static GLuint uint_types_scale[5] = {
  85    0,
  86    BRW_SURFACEFORMAT_R32_USCALED,
  87    BRW_SURFACEFORMAT_R32G32_USCALED,
  88    BRW_SURFACEFORMAT_R32G32B32_USCALED,
  89    BRW_SURFACEFORMAT_R32G32B32A32_USCALED
  90 };
  91
  92 static GLuint int_types_direct[5] = {
  93    0,
  94    BRW_SURFACEFORMAT_R32_SINT,
  95    BRW_SURFACEFORMAT_R32G32_SINT,
  96    BRW_SURFACEFORMAT_R32G32B32_SINT,
  97    BRW_SURFACEFORMAT_R32G32B32A32_SINT
  98 };
  99
 100 static GLuint int_types_norm[5] = {
 101    0,
 102    BRW_SURFACEFORMAT_R32_SNORM,
 103    BRW_SURFACEFORMAT_R32G32_SNORM,
 104    BRW_SURFACEFORMAT_R32G32B32_SNORM,
 105    BRW_SURFACEFORMAT_R32G32B32A32_SNORM
 106 };
 107
 108 static GLuint int_types_scale[5] = {
 109    0,
 110    BRW_SURFACEFORMAT_R32_SSCALED,
 111    BRW_SURFACEFORMAT_R32G32_SSCALED,
 112    BRW_SURFACEFORMAT_R32G32B32_SSCALED,
 113    BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
 114 };
 115
 116 static GLuint ushort_types_direct[5] = {
 117    0,
 118    BRW_SURFACEFORMAT_R16_UINT,
 119    BRW_SURFACEFORMAT_R16G16_UINT,
 120    BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 121    BRW_SURFACEFORMAT_R16G16B16A16_UINT
 122 };
 123
 124 static GLuint ushort_types_norm[5] = {
 125    0,
 126    BRW_SURFACEFORMAT_R16_UNORM,
 127    BRW_SURFACEFORMAT_R16G16_UNORM,
 128    BRW_SURFACEFORMAT_R16G16B16_UNORM,
 129    BRW_SURFACEFORMAT_R16G16B16A16_UNORM
 130 };
 131
 132 static GLuint ushort_types_scale[5] = {
 133    0,
 134    BRW_SURFACEFORMAT_R16_USCALED,
 135    BRW_SURFACEFORMAT_R16G16_USCALED,
 136    BRW_SURFACEFORMAT_R16G16B16_USCALED,
 137    BRW_SURFACEFORMAT_R16G16B16A16_USCALED
 138 };
 139
 140 static GLuint short_types_direct[5] = {
 141    0,
 142    BRW_SURFACEFORMAT_R16_SINT,
 143    BRW_SURFACEFORMAT_R16G16_SINT,
 144    BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 145    BRW_SURFACEFORMAT_R16G16B16A16_SINT
 146 };
 147
 148 static GLuint short_types_norm[5] = {
 149    0,
 150    BRW_SURFACEFORMAT_R16_SNORM,
 151    BRW_SURFACEFORMAT_R16G16_SNORM,
 152    BRW_SURFACEFORMAT_R16G16B16_SNORM,
 153    BRW_SURFACEFORMAT_R16G16B16A16_SNORM
 154 };
 155
 156 static GLuint short_types_scale[5] = {
 157    0,
 158    BRW_SURFACEFORMAT_R16_SSCALED,
 159    BRW_SURFACEFORMAT_R16G16_SSCALED,
 160    BRW_SURFACEFORMAT_R16G16B16_SSCALED,
 161    BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
 162 };
 163
 164 static GLuint ubyte_types_direct[5] = {
 165    0,
 166    BRW_SURFACEFORMAT_R8_UINT,
 167    BRW_SURFACEFORMAT_R8G8_UINT,
 168    BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 169    BRW_SURFACEFORMAT_R8G8B8A8_UINT
 170 };
 171
 172 static GLuint ubyte_types_norm[5] = {
 173    0,
 174    BRW_SURFACEFORMAT_R8_UNORM,
 175    BRW_SURFACEFORMAT_R8G8_UNORM,
 176    BRW_SURFACEFORMAT_R8G8B8_UNORM,
 177    BRW_SURFACEFORMAT_R8G8B8A8_UNORM
 178 };
 179
 180 static GLuint ubyte_types_scale[5] = {
 181    0,
 182    BRW_SURFACEFORMAT_R8_USCALED,
 183    BRW_SURFACEFORMAT_R8G8_USCALED,
 184    BRW_SURFACEFORMAT_R8G8B8_USCALED,
 185    BRW_SURFACEFORMAT_R8G8B8A8_USCALED
 186 };
 187
 188 static GLuint byte_types_direct[5] = {
 189    0,
 190    BRW_SURFACEFORMAT_R8_SINT,
 191    BRW_SURFACEFORMAT_R8G8_SINT,
 192    BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 193    BRW_SURFACEFORMAT_R8G8B8A8_SINT
 194 };
 195
 196 static GLuint byte_types_norm[5] = {
 197    0,
 198    BRW_SURFACEFORMAT_R8_SNORM,
 199    BRW_SURFACEFORMAT_R8G8_SNORM,
 200    BRW_SURFACEFORMAT_R8G8B8_SNORM,
 201    BRW_SURFACEFORMAT_R8G8B8A8_SNORM
 202 };
 203
 204 static GLuint byte_types_scale[5] = {
 205    0,
 206    BRW_SURFACEFORMAT_R8_SSCALED,
 207    BRW_SURFACEFORMAT_R8G8_SSCALED,
 208    BRW_SURFACEFORMAT_R8G8B8_SSCALED,
 209    BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
 210 };
 211
 212
 213 /**
 214  * Given vertex array type/size/format/normalized info, return
 215  * the appopriate hardware surface type.
 216  * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
 217  */
 218 static GLuint get_surface_type( GLenum type, GLuint size,
 219                                 GLenum format, bool normalized, bool integer )
 220 {
 221    if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
 222       printf("type %s size %d normalized %d\n",
 223                    _mesa_lookup_enum_by_nr(type), size, normalized);
 224
 225    if (integer) {
 226       assert(format == GL_RGBA); /* sanity check */
 227       switch (type) {
 228       case GL_INT: return int_types_direct[size];
 229       case GL_SHORT: return short_types_direct[size];
 230       case GL_BYTE: return byte_types_direct[size];
 231       case GL_UNSIGNED_INT: return uint_types_direct[size];
 232       case GL_UNSIGNED_SHORT: return ushort_types_direct[size];
 233       case GL_UNSIGNED_BYTE: return ubyte_types_direct[size];
 234       default: assert(0); return 0;
 235       }
 236    } else if (normalized) {
 237       switch (type) {
 238       case GL_DOUBLE: return double_types[size];
 239       case GL_FLOAT: return float_types[size];
 240       case GL_HALF_FLOAT: return half_float_types[size];
 241       case GL_INT: return int_types_norm[size];
 242       case GL_SHORT: return short_types_norm[size];
 243       case GL_BYTE: return byte_types_norm[size];
 244       case GL_UNSIGNED_INT: return uint_types_norm[size];
 245       case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
 246       case GL_UNSIGNED_BYTE:
 247          if (format == GL_BGRA) {
 248             /* See GL_EXT_vertex_array_bgra */
 249             assert(size == 4);
 250             return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 251          }
 252          else {
 253             return ubyte_types_norm[size];
 254          }
 255       default: assert(0); return 0;
 256       }
 257    }
 258    else {
 259       assert(format == GL_RGBA); /* sanity check */
 260       switch (type) {
 261       case GL_DOUBLE: return double_types[size];
 262       case GL_FLOAT: return float_types[size];
 263       case GL_HALF_FLOAT: return half_float_types[size];
 264       case GL_INT: return int_types_scale[size];
 265       case GL_SHORT: return short_types_scale[size];
 266       case GL_BYTE: return byte_types_scale[size];
 267       case GL_UNSIGNED_INT: return uint_types_scale[size];
 268       case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
 269       case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
 270       /* This produces GL_FIXED inputs as values between INT32_MIN and
 271        * INT32_MAX, which will be scaled down by 1/65536 by the VS.
 272        */
 273       case GL_FIXED: return int_types_scale[size];
 274       default: assert(0); return 0;
 275       }
 276    }
 277 }
 278
 279
 280 static GLuint get_size( GLenum type )
 281 {
 282    switch (type) {
 283    case GL_DOUBLE: return sizeof(GLdouble);
 284    case GL_FLOAT: return sizeof(GLfloat);
 285    case GL_HALF_FLOAT: return sizeof(GLhalfARB);
 286    case GL_INT: return sizeof(GLint);
 287    case GL_SHORT: return sizeof(GLshort);
 288    case GL_BYTE: return sizeof(GLbyte);
 289    case GL_UNSIGNED_INT: return sizeof(GLuint);
 290    case GL_UNSIGNED_SHORT: return sizeof(GLushort);
 291    case GL_UNSIGNED_BYTE: return sizeof(GLubyte);
 292    case GL_FIXED: return sizeof(GLuint);
 293    default: assert(0); return 0;
 294    }
 295 }
 296
 297 static GLuint get_index_type(GLenum type)
 298 {
 299    switch (type) {
 300    case GL_UNSIGNED_BYTE:  return BRW_INDEX_BYTE;
 301    case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
 302    case GL_UNSIGNED_INT:   return BRW_INDEX_DWORD;
 303    default: assert(0); return 0;
 304    }
 305 }
 306
 307 static void
 308 copy_array_to_vbo_array(struct brw_context *brw,
 309                         struct brw_vertex_element *element,
 310                         int min, int max,
 311                         struct brw_vertex_buffer *buffer,
 312                         GLuint dst_stride)
 313 {
 314    if (min == -1) {
 315       /* If we don't have computed min/max bounds, then this must be a use of
 316        * the current attribute, which has a 0 stride.  Otherwise, we wouldn't
 317        * know what data to upload.
 318        */
 319       assert(element->glarray->StrideB == 0);
 320
 321       intel_upload_data(&brw->intel, element->glarray->Ptr,
 322                         element->element_size,
 323                         element->element_size,
 324                         &buffer->bo, &buffer->offset);
 325
 326       buffer->stride = 0;
 327       return;
 328    }
 329
 330    int src_stride = element->glarray->StrideB;
 331    const unsigned char *src = element->glarray->Ptr + min * src_stride;
 332    int count = max - min + 1;
 333    GLuint size = count * dst_stride;
 334
 335    if (dst_stride == src_stride) {
 336       intel_upload_data(&brw->intel, src, size, dst_stride,
 337                         &buffer->bo, &buffer->offset);
 338    } else {
 339       char * const map = intel_upload_map(&brw->intel, size, dst_stride);
 340       char *dst = map;
 341
 342       while (count--) {
 343          memcpy(dst, src, dst_stride);
 344          src += src_stride;
 345          dst += dst_stride;
 346       }
 347       intel_upload_unmap(&brw->intel, map, size, dst_stride,
 348                          &buffer->bo, &buffer->offset);
 349    }
 350    buffer->stride = dst_stride;
 351 }
 352
 353 static void brw_prepare_vertices(struct brw_context *brw)
 354 {
 355    struct gl_context *ctx = &brw->intel.ctx;
 356    struct intel_context *intel = intel_context(ctx);
 357    /* CACHE_NEW_VS_PROG */
 358    GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
 359    const unsigned char *ptr = NULL;
 360    GLuint interleaved = 0, total_size = 0;
 361    unsigned int min_index = brw->vb.min_index;
 362    unsigned int max_index = brw->vb.max_index;
 363    int delta, i, j;
 364
 365    struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
 366    GLuint nr_uploads = 0;
 367
 368    /* First build an array of pointers to ve's in vb.inputs_read
 369     */
 370    if (0)
 371       printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
 372
 373    /* Accumulate the list of enabled arrays. */
 374    brw->vb.nr_enabled = 0;
 375    while (vs_inputs) {
 376       GLuint i = ffs(vs_inputs) - 1;
 377       struct brw_vertex_element *input = &brw->vb.inputs[i];
 378
 379       vs_inputs &= ~(1 << i);
 380       if (input->glarray->Size && get_size(input->glarray->Type))
 381          brw->vb.enabled[brw->vb.nr_enabled++] = input;
 382    }
 383
 384    if (brw->vb.nr_enabled == 0)
 385       return;
 386
 387    if (brw->vb.nr_buffers)
 388       goto prepare;
 389
 390    for (i = j = 0; i < brw->vb.nr_enabled; i++) {
 391       struct brw_vertex_element *input = brw->vb.enabled[i];
 392       const struct gl_client_array *glarray = input->glarray;
 393       int type_size = get_size(glarray->Type);
 394
 395       input->element_size = type_size * glarray->Size;
 396
 397       if (_mesa_is_bufferobj(glarray->BufferObj)) {
 398          struct intel_buffer_object *intel_buffer =
 399             intel_buffer_object(glarray->BufferObj);
 400          int k;
 401
 402          for (k = 0; k < i; k++) {
 403             const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
 404             if (glarray->BufferObj == other->BufferObj &&
 405                 glarray->StrideB == other->StrideB &&
 406                 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
 407             {
 408                input->buffer = brw->vb.enabled[k]->buffer;
 409                input->offset = glarray->Ptr - other->Ptr;
 410                break;
 411             }
 412          }
 413          if (k == i) {
 414             struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 415
 416             /* Named buffer object: Just reference its contents directly. */
 417             buffer->bo = intel_bufferobj_source(intel,
 418                                                 intel_buffer, type_size,
 419                                                 &buffer->offset);
 420             drm_intel_bo_reference(buffer->bo);
 421             buffer->offset += (uintptr_t)glarray->Ptr;
 422             buffer->stride = glarray->StrideB;
 423
 424             input->buffer = j++;
 425             input->offset = 0;
 426          }
 427
 428          /* This is a common place to reach if the user mistakenly supplies
 429           * a pointer in place of a VBO offset.  If we just let it go through,
 430           * we may end up dereferencing a pointer beyond the bounds of the
 431           * GTT.  We would hope that the VBO's max_index would save us, but
 432           * Mesa appears to hand us min/max values not clipped to the
 433           * array object's _MaxElement, and _MaxElement frequently appears
 434           * to be wrong anyway.
 435           *
 436           * The VBO spec allows application termination in this case, and it's
 437           * probably a service to the poor programmer to do so rather than
 438           * trying to just not render.
 439           */
 440          assert(input->offset < brw->vb.buffers[input->buffer].bo->size);
 441       } else {
 442          /* Queue the buffer object up to be uploaded in the next pass,
 443           * when we've decided if we're doing interleaved or not.
 444           */
 445          if (nr_uploads == 0) {
 446             /* Position array not properly enabled:
 447              */
 448             if (input->attrib == VERT_ATTRIB_POS && glarray->StrideB == 0) {
 449                intel->Fallback = true; /* boolean, not bitfield */
 450                return;
 451             }
 452
 453             interleaved = glarray->StrideB;
 454             ptr = glarray->Ptr;
 455          }
 456          else if (interleaved != glarray->StrideB ||
 457                   (uintptr_t)(glarray->Ptr - ptr) > interleaved)
 458          {
 459             interleaved = 0;
 460          }
 461          else if ((uintptr_t)(glarray->Ptr - ptr) & (type_size -1))
 462          {
 463             /* enforce natural alignment (for doubles) */
 464             interleaved = 0;
 465          }
 466
 467          upload[nr_uploads++] = input;
 468          total_size = ALIGN(total_size, type_size);
 469          total_size += input->element_size;
 470       }
 471    }
 472
 473    /* If we need to upload all the arrays, then we can trim those arrays to
 474     * only the used elements [min_index, max_index] so long as we adjust all
 475     * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
 476     */
 477    brw->vb.start_vertex_bias = 0;
 478    delta = min_index;
 479    if (nr_uploads == brw->vb.nr_enabled) {
 480       brw->vb.start_vertex_bias = -delta;
 481       delta = 0;
 482    }
 483    if (delta && !brw->intel.intelScreen->relaxed_relocations)
 484       min_index = delta = 0;
 485
 486    /* Handle any arrays to be uploaded. */
 487    if (nr_uploads > 1) {
 488       if (interleaved && interleaved <= 2*total_size) {
 489          struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 490          /* All uploads are interleaved, so upload the arrays together as
 491           * interleaved.  First, upload the contents and set up upload[0].
 492           */
 493          copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
 494                                  buffer, interleaved);
 495          buffer->offset -= delta * interleaved;
 496
 497          for (i = 0; i < nr_uploads; i++) {
 498             /* Then, just point upload[i] at upload[0]'s buffer. */
 499             upload[i]->offset =
 500                ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
 501             upload[i]->buffer = j;
 502          }
 503          j++;
 504
 505          nr_uploads = 0;
 506       }
 507       else if (total_size < 2048) {
 508          /* Upload non-interleaved arrays into a single interleaved array */
 509          struct brw_vertex_buffer *buffer;
 510          int count = MAX2(max_index - min_index + 1, 1);
 511          int offset;
 512          char *map;
 513
 514          map = intel_upload_map(&brw->intel, total_size * count, total_size);
 515          for (i = offset = 0; i < nr_uploads; i++) {
 516             const unsigned char *src = upload[i]->glarray->Ptr;
 517             int size = upload[i]->element_size;
 518             int stride = upload[i]->glarray->StrideB;
 519             char *dst;
 520             int n;
 521
 522             offset = ALIGN(offset, get_size(upload[i]->glarray->Type));
 523             dst = map + offset;
 524             src += min_index * stride;
 525
 526             for (n = 0; n < count; n++) {
 527                memcpy(dst, src, size);
 528                src += stride;
 529                dst += total_size;
 530             }
 531
 532             upload[i]->offset = offset;
 533             upload[i]->buffer = j;
 534
 535             offset += size;
 536          }
 537          assert(offset == total_size);
 538          buffer = &brw->vb.buffers[j++];
 539          intel_upload_unmap(&brw->intel, map, offset * count, offset,
 540                             &buffer->bo, &buffer->offset);
 541          buffer->stride = offset;
 542          buffer->offset -= delta * offset;
 543
 544          nr_uploads = 0;
 545       }
 546    }
 547    /* Upload non-interleaved arrays */
 548    for (i = 0; i < nr_uploads; i++) {
 549       struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 550       copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
 551                               buffer, upload[i]->element_size);
 552       buffer->offset -= delta * buffer->stride;
 553       upload[i]->buffer = j++;
 554       upload[i]->offset = 0;
 555    }
 556
 557    /* can we simply extend the current vb? */
 558    if (j == brw->vb.nr_current_buffers) {
 559       int delta = 0;
 560       for (i = 0; i < j; i++) {
 561          int d;
 562
 563          if (brw->vb.current_buffers[i].handle != brw->vb.buffers[i].bo->handle ||
 564              brw->vb.current_buffers[i].stride != brw->vb.buffers[i].stride)
 565             break;
 566
 567          d = brw->vb.buffers[i].offset - brw->vb.current_buffers[i].offset;
 568          if (d < 0)
 569             break;
 570          if (i == 0)
 571             delta = d / brw->vb.current_buffers[i].stride;
 572          if (delta * brw->vb.current_buffers[i].stride != d)
 573             break;
 574       }
 575
 576       if (i == j) {
 577          brw->vb.start_vertex_bias += delta;
 578          while (--j >= 0)
 579             drm_intel_bo_unreference(brw->vb.buffers[j].bo);
 580          j = 0;
 581       }
 582    }
 583
 584    brw->vb.nr_buffers = j;
 585
 586 prepare:
 587    brw_prepare_query_begin(brw);
 588 }
 589
 590 static void brw_emit_vertices(struct brw_context *brw)
 591 {
 592    struct gl_context *ctx = &brw->intel.ctx;
 593    struct intel_context *intel = intel_context(ctx);
 594    GLuint i, nr_elements;
 595
 596    brw_prepare_vertices(brw);
 597
 598    brw_emit_query_begin(brw);
 599
 600    /* If the VS doesn't read any inputs (calculating vertex position from
 601     * a state variable for some reason, for example), emit a single pad
 602     * VERTEX_ELEMENT struct and bail.
 603     *
 604     * The stale VB state stays in place, but they don't do anything unless
 605     * a VE loads from them.
 606     */
 607    if (brw->vb.nr_enabled == 0) {
 608       BEGIN_BATCH(3);
 609       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
 610       if (intel->gen >= 6) {
 611          OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
 612                    GEN6_VE0_VALID |
 613                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 614                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 615       } else {
 616          OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
 617                    BRW_VE0_VALID |
 618                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 619                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 620       }
 621       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 622                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 623                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 624                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
 625       CACHED_BATCH();
 626       return;
 627    }
 628
 629    /* Now emit VB and VEP state packets.
 630     */
 631
 632    if (brw->vb.nr_buffers) {
 633       if (intel->gen >= 6) {
 634          assert(brw->vb.nr_buffers <= 33);
 635       } else {
 636          assert(brw->vb.nr_buffers <= 17);
 637       }
 638
 639       BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
 640       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
 641       for (i = 0; i < brw->vb.nr_buffers; i++) {
 642          struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
 643          uint32_t dw0;
 644
 645          if (intel->gen >= 6) {
 646             dw0 = GEN6_VB0_ACCESS_VERTEXDATA | (i << GEN6_VB0_INDEX_SHIFT);
 647          } else {
 648             dw0 = BRW_VB0_ACCESS_VERTEXDATA | (i << BRW_VB0_INDEX_SHIFT);
 649          }
 650
 651          if (intel->gen >= 7)
 652             dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 653
 654          OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
 655          OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
 656          if (intel->gen >= 5) {
 657             OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1);
 658          } else
 659             OUT_BATCH(0);
 660          OUT_BATCH(0); /* Instance data step rate */
 661
 662          brw->vb.current_buffers[i].handle = buffer->bo->handle;
 663          brw->vb.current_buffers[i].offset = buffer->offset;
 664          brw->vb.current_buffers[i].stride = buffer->stride;
 665       }
 666       brw->vb.nr_current_buffers = i;
 667       ADVANCE_BATCH();
 668    }
 669
 670    nr_elements = brw->vb.nr_enabled + brw->vs.prog_data->uses_vertexid;
 671
 672    /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
 673     * for VertexID/InstanceID.
 674     */
 675    if (intel->gen >= 6) {
 676       assert(nr_elements <= 34);
 677    } else {
 678       assert(nr_elements <= 18);
 679    }
 680
 681    BEGIN_BATCH(1 + nr_elements * 2);
 682    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
 683    for (i = 0; i < brw->vb.nr_enabled; i++) {
 684       struct brw_vertex_element *input = brw->vb.enabled[i];
 685       uint32_t format = get_surface_type(input->glarray->Type,
 686                                          input->glarray->Size,
 687                                          input->glarray->Format,
 688                                          input->glarray->Normalized,
 689                                          input->glarray->Integer);
 690       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 691       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 692       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
 693       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
 694
 695       switch (input->glarray->Size) {
 696       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
 697       case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
 698       case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
 699       case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
 700                                               : BRW_VE1_COMPONENT_STORE_1_FLT;
 701          break;
 702       }
 703
 704       if (intel->gen >= 6) {
 705          OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
 706                    GEN6_VE0_VALID |
 707                    (format << BRW_VE0_FORMAT_SHIFT) |
 708                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 709       } else {
 710          OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
 711                    BRW_VE0_VALID |
 712                    (format << BRW_VE0_FORMAT_SHIFT) |
 713                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 714       }
 715
 716       if (intel->gen >= 5)
 717           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 718                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 719                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 720                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
 721       else
 722           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 723                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 724                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 725                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
 726                     ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
 727    }
 728
 729    if (brw->vs.prog_data->uses_vertexid) {
 730       uint32_t dw0 = 0, dw1 = 0;
 731
 732       dw1 = ((BRW_VE1_COMPONENT_STORE_VID << BRW_VE1_COMPONENT_0_SHIFT) |
 733              (BRW_VE1_COMPONENT_STORE_IID << BRW_VE1_COMPONENT_1_SHIFT) |
 734              (BRW_VE1_COMPONENT_STORE_PID << BRW_VE1_COMPONENT_2_SHIFT) |
 735              (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 736
 737       if (intel->gen >= 6) {
 738          dw0 |= GEN6_VE0_VALID;
 739       } else {
 740          dw0 |= BRW_VE0_VALID;
 741          dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
 742       }
 743
 744       /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
 745        * the format is ignored and the value is always int.
 746        */
 747
 748       OUT_BATCH(dw0);
 749       OUT_BATCH(dw1);
 750    }
 751
 752    CACHED_BATCH();
 753 }
 754
 755 const struct brw_tracked_state brw_vertices = {
 756    .dirty = {
 757       .mesa = 0,
 758       .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
 759       .cache = CACHE_NEW_VS_PROG,
 760    },
 761    .emit = brw_emit_vertices,
 762 };
 763
 764 static void brw_upload_indices(struct brw_context *brw)
 765 {
 766    struct gl_context *ctx = &brw->intel.ctx;
 767    struct intel_context *intel = &brw->intel;
 768    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 769    GLuint ib_size;
 770    drm_intel_bo *bo = NULL;
 771    struct gl_buffer_object *bufferobj;
 772    GLuint offset;
 773    GLuint ib_type_size;
 774
 775    if (index_buffer == NULL)
 776       return;
 777
 778    ib_type_size = get_size(index_buffer->type);
 779    ib_size = ib_type_size * index_buffer->count;
 780    bufferobj = index_buffer->obj;
 781
 782    /* Turn into a proper VBO:
 783     */
 784    if (!_mesa_is_bufferobj(bufferobj)) {
 785
 786       /* Get new bufferobj, offset:
 787        */
 788       intel_upload_data(&brw->intel, index_buffer->ptr, ib_size, ib_type_size,
 789                         &bo, &offset);
 790       brw->ib.start_vertex_offset = offset / ib_type_size;
 791    } else {
 792       offset = (GLuint) (unsigned long) index_buffer->ptr;
 793
 794       /* If the index buffer isn't aligned to its element size, we have to
 795        * rebase it into a temporary.
 796        */
 797        if ((get_size(index_buffer->type) - 1) & offset) {
 798            GLubyte *map = ctx->Driver.MapBufferRange(ctx,
 799                                                      offset,
 800                                                      ib_size,
 801                                                      GL_MAP_WRITE_BIT,
 802                                                      bufferobj);
 803
 804            intel_upload_data(&brw->intel, map, ib_size, ib_type_size,
 805                              &bo, &offset);
 806            brw->ib.start_vertex_offset = offset / ib_type_size;
 807
 808            ctx->Driver.UnmapBuffer(ctx, bufferobj);
 809        } else {
 810           /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
 811            * the index buffer state when we're just moving the start index
 812            * of our drawing.
 813            */
 814           brw->ib.start_vertex_offset = offset / ib_type_size;
 815
 816           bo = intel_bufferobj_source(intel,
 817                                       intel_buffer_object(bufferobj),
 818                                       ib_type_size,
 819                                       &offset);
 820           drm_intel_bo_reference(bo);
 821
 822           brw->ib.start_vertex_offset += offset / ib_type_size;
 823        }
 824    }
 825
 826    if (brw->ib.bo != bo) {
 827       drm_intel_bo_unreference(brw->ib.bo);
 828       brw->ib.bo = bo;
 829
 830       brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
 831    } else {
 832       drm_intel_bo_unreference(bo);
 833    }
 834
 835    if (index_buffer->type != brw->ib.type) {
 836       brw->ib.type = index_buffer->type;
 837       brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
 838    }
 839 }
 840
 841 const struct brw_tracked_state brw_indices = {
 842    .dirty = {
 843       .mesa = 0,
 844       .brw = BRW_NEW_INDICES,
 845       .cache = 0,
 846    },
 847    .emit = brw_upload_indices,
 848 };
 849
 850 static void brw_emit_index_buffer(struct brw_context *brw)
 851 {
 852    struct intel_context *intel = &brw->intel;
 853    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 854
 855    if (index_buffer == NULL)
 856       return;
 857
 858    BEGIN_BATCH(3);
 859    OUT_BATCH(CMD_INDEX_BUFFER << 16 |
 860              /* cut index enable << 10 */
 861              get_index_type(index_buffer->type) << 8 |
 862              1);
 863    OUT_RELOC(brw->ib.bo,
 864              I915_GEM_DOMAIN_VERTEX, 0,
 865              0);
 866    OUT_RELOC(brw->ib.bo,
 867              I915_GEM_DOMAIN_VERTEX, 0,
 868              brw->ib.bo->size - 1);
 869    ADVANCE_BATCH();
 870 }
 871
 872 const struct brw_tracked_state brw_index_buffer = {
 873    .dirty = {
 874       .mesa = 0,
 875       .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
 876       .cache = 0,
 877    },
 878    .emit = brw_emit_index_buffer,
 879 };