projects / mesa.git / blob
? search:


f4d1b2c6af10af7da9417d1204e08145a9b74fe8
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/bufferobj.h"
27 #include "main/context.h"
28 #include "main/enums.h"
29 #include "main/macros.h"
30 #include "main/glformats.h"
31
32 #include "brw_draw.h"
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
36
37 #include "intel_batchbuffer.h"
38 #include "intel_buffer_objects.h"
39
40 static const GLuint double_types_float[5] = {
41 0,
42 BRW_SURFACEFORMAT_R64_FLOAT,
43 BRW_SURFACEFORMAT_R64G64_FLOAT,
44 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
45 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
46 };
47
48 static const GLuint double_types_passthru[5] = {
49 0,
50 BRW_SURFACEFORMAT_R64_PASSTHRU,
51 BRW_SURFACEFORMAT_R64G64_PASSTHRU,
52 BRW_SURFACEFORMAT_R64G64B64_PASSTHRU,
53 BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU
54 };
55
56 static const GLuint float_types[5] = {
57 0,
58 BRW_SURFACEFORMAT_R32_FLOAT,
59 BRW_SURFACEFORMAT_R32G32_FLOAT,
60 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
61 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
62 };
63
64 static const GLuint half_float_types[5] = {
65 0,
66 BRW_SURFACEFORMAT_R16_FLOAT,
67 BRW_SURFACEFORMAT_R16G16_FLOAT,
68 BRW_SURFACEFORMAT_R16G16B16_FLOAT,
69 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
70 };
71
72 static const GLuint fixed_point_types[5] = {
73 0,
74 BRW_SURFACEFORMAT_R32_SFIXED,
75 BRW_SURFACEFORMAT_R32G32_SFIXED,
76 BRW_SURFACEFORMAT_R32G32B32_SFIXED,
77 BRW_SURFACEFORMAT_R32G32B32A32_SFIXED,
78 };
79
80 static const GLuint uint_types_direct[5] = {
81 0,
82 BRW_SURFACEFORMAT_R32_UINT,
83 BRW_SURFACEFORMAT_R32G32_UINT,
84 BRW_SURFACEFORMAT_R32G32B32_UINT,
85 BRW_SURFACEFORMAT_R32G32B32A32_UINT
86 };
87
88 static const GLuint uint_types_norm[5] = {
89 0,
90 BRW_SURFACEFORMAT_R32_UNORM,
91 BRW_SURFACEFORMAT_R32G32_UNORM,
92 BRW_SURFACEFORMAT_R32G32B32_UNORM,
93 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
94 };
95
96 static const GLuint uint_types_scale[5] = {
97 0,
98 BRW_SURFACEFORMAT_R32_USCALED,
99 BRW_SURFACEFORMAT_R32G32_USCALED,
100 BRW_SURFACEFORMAT_R32G32B32_USCALED,
101 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
102 };
103
104 static const GLuint int_types_direct[5] = {
105 0,
106 BRW_SURFACEFORMAT_R32_SINT,
107 BRW_SURFACEFORMAT_R32G32_SINT,
108 BRW_SURFACEFORMAT_R32G32B32_SINT,
109 BRW_SURFACEFORMAT_R32G32B32A32_SINT
110 };
111
112 static const GLuint int_types_norm[5] = {
113 0,
114 BRW_SURFACEFORMAT_R32_SNORM,
115 BRW_SURFACEFORMAT_R32G32_SNORM,
116 BRW_SURFACEFORMAT_R32G32B32_SNORM,
117 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
118 };
119
120 static const GLuint int_types_scale[5] = {
121 0,
122 BRW_SURFACEFORMAT_R32_SSCALED,
123 BRW_SURFACEFORMAT_R32G32_SSCALED,
124 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
125 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
126 };
127
128 static const GLuint ushort_types_direct[5] = {
129 0,
130 BRW_SURFACEFORMAT_R16_UINT,
131 BRW_SURFACEFORMAT_R16G16_UINT,
132 BRW_SURFACEFORMAT_R16G16B16_UINT,
133 BRW_SURFACEFORMAT_R16G16B16A16_UINT
134 };
135
136 static const GLuint ushort_types_norm[5] = {
137 0,
138 BRW_SURFACEFORMAT_R16_UNORM,
139 BRW_SURFACEFORMAT_R16G16_UNORM,
140 BRW_SURFACEFORMAT_R16G16B16_UNORM,
141 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
142 };
143
144 static const GLuint ushort_types_scale[5] = {
145 0,
146 BRW_SURFACEFORMAT_R16_USCALED,
147 BRW_SURFACEFORMAT_R16G16_USCALED,
148 BRW_SURFACEFORMAT_R16G16B16_USCALED,
149 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
150 };
151
152 static const GLuint short_types_direct[5] = {
153 0,
154 BRW_SURFACEFORMAT_R16_SINT,
155 BRW_SURFACEFORMAT_R16G16_SINT,
156 BRW_SURFACEFORMAT_R16G16B16_SINT,
157 BRW_SURFACEFORMAT_R16G16B16A16_SINT
158 };
159
160 static const GLuint short_types_norm[5] = {
161 0,
162 BRW_SURFACEFORMAT_R16_SNORM,
163 BRW_SURFACEFORMAT_R16G16_SNORM,
164 BRW_SURFACEFORMAT_R16G16B16_SNORM,
165 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
166 };
167
168 static const GLuint short_types_scale[5] = {
169 0,
170 BRW_SURFACEFORMAT_R16_SSCALED,
171 BRW_SURFACEFORMAT_R16G16_SSCALED,
172 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
173 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
174 };
175
176 static const GLuint ubyte_types_direct[5] = {
177 0,
178 BRW_SURFACEFORMAT_R8_UINT,
179 BRW_SURFACEFORMAT_R8G8_UINT,
180 BRW_SURFACEFORMAT_R8G8B8_UINT,
181 BRW_SURFACEFORMAT_R8G8B8A8_UINT
182 };
183
184 static const GLuint ubyte_types_norm[5] = {
185 0,
186 BRW_SURFACEFORMAT_R8_UNORM,
187 BRW_SURFACEFORMAT_R8G8_UNORM,
188 BRW_SURFACEFORMAT_R8G8B8_UNORM,
189 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
190 };
191
192 static const GLuint ubyte_types_scale[5] = {
193 0,
194 BRW_SURFACEFORMAT_R8_USCALED,
195 BRW_SURFACEFORMAT_R8G8_USCALED,
196 BRW_SURFACEFORMAT_R8G8B8_USCALED,
197 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
198 };
199
200 static const GLuint byte_types_direct[5] = {
201 0,
202 BRW_SURFACEFORMAT_R8_SINT,
203 BRW_SURFACEFORMAT_R8G8_SINT,
204 BRW_SURFACEFORMAT_R8G8B8_SINT,
205 BRW_SURFACEFORMAT_R8G8B8A8_SINT
206 };
207
208 static const GLuint byte_types_norm[5] = {
209 0,
210 BRW_SURFACEFORMAT_R8_SNORM,
211 BRW_SURFACEFORMAT_R8G8_SNORM,
212 BRW_SURFACEFORMAT_R8G8B8_SNORM,
213 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
214 };
215
216 static const GLuint byte_types_scale[5] = {
217 0,
218 BRW_SURFACEFORMAT_R8_SSCALED,
219 BRW_SURFACEFORMAT_R8G8_SSCALED,
220 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
221 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
222 };
223
224 static GLuint
225 double_types(struct brw_context *brw,
226 int size,
227 GLboolean doubles)
228 {
229 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
230 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
231 * 64-bit components are stored in the URB without any conversion."
232 * Also included on BDW PRM, Volume 7, page 470, table "Source Element
233 * Formats Supported in VF Unit"
234 * Previous PRMs don't include those references.
235 */
236 return (brw->gen >= 8 && doubles
237 ? double_types_passthru[size]
238 : double_types_float[size]);
239 }
240
241 /**
242 * Given vertex array type/size/format/normalized info, return
243 * the appopriate hardware surface type.
244 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
245 */
246 unsigned
247 brw_get_vertex_surface_type(struct brw_context *brw,
248 const struct gl_client_array *glarray)
249 {
250 int size = glarray->Size;
251 const bool is_ivybridge_or_older =
252 brw->gen <= 7 && !brw->is_baytrail && !brw->is_haswell;
253
254 if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
255 fprintf(stderr, "type %s size %d normalized %d\n",
256 _mesa_enum_to_string(glarray->Type),
257 glarray->Size, glarray->Normalized);
258
259 if (glarray->Integer) {
260 assert(glarray->Format == GL_RGBA); /* sanity check */
261 switch (glarray->Type) {
262 case GL_INT: return int_types_direct[size];
263 case GL_SHORT:
264 if (is_ivybridge_or_older && size == 3)
265 return short_types_direct[4];
266 else
267 return short_types_direct[size];
268 case GL_BYTE:
269 if (is_ivybridge_or_older && size == 3)
270 return byte_types_direct[4];
271 else
272 return byte_types_direct[size];
273 case GL_UNSIGNED_INT: return uint_types_direct[size];
274 case GL_UNSIGNED_SHORT:
275 if (is_ivybridge_or_older && size == 3)
276 return ushort_types_direct[4];
277 else
278 return ushort_types_direct[size];
279 case GL_UNSIGNED_BYTE:
280 if (is_ivybridge_or_older && size == 3)
281 return ubyte_types_direct[4];
282 else
283 return ubyte_types_direct[size];
284 default: unreachable("not reached");
285 }
286 } else if (glarray->Type == GL_UNSIGNED_INT_10F_11F_11F_REV) {
287 return BRW_SURFACEFORMAT_R11G11B10_FLOAT;
288 } else if (glarray->Normalized) {
289 switch (glarray->Type) {
290 case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
291 case GL_FLOAT: return float_types[size];
292 case GL_HALF_FLOAT:
293 if (brw->gen < 6 && size == 3)
294 return half_float_types[4];
295 else
296 return half_float_types[size];
297 case GL_INT: return int_types_norm[size];
298 case GL_SHORT: return short_types_norm[size];
299 case GL_BYTE: return byte_types_norm[size];
300 case GL_UNSIGNED_INT: return uint_types_norm[size];
301 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
302 case GL_UNSIGNED_BYTE:
303 if (glarray->Format == GL_BGRA) {
304 /* See GL_EXT_vertex_array_bgra */
305 assert(size == 4);
306 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
307 }
308 else {
309 return ubyte_types_norm[size];
310 }
311 case GL_FIXED:
312 if (brw->gen >= 8 || brw->is_haswell)
313 return fixed_point_types[size];
314
315 /* This produces GL_FIXED inputs as values between INT32_MIN and
316 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
317 */
318 return int_types_scale[size];
319 /* See GL_ARB_vertex_type_2_10_10_10_rev.
320 * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
321 * like to use here, so upload everything as UINT and fix
322 * it in the shader
323 */
324 case GL_INT_2_10_10_10_REV:
325 assert(size == 4);
326 if (brw->gen >= 8 || brw->is_haswell) {
327 return glarray->Format == GL_BGRA
328 ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
329 : BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
330 }
331 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
332 case GL_UNSIGNED_INT_2_10_10_10_REV:
333 assert(size == 4);
334 if (brw->gen >= 8 || brw->is_haswell) {
335 return glarray->Format == GL_BGRA
336 ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
337 : BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
338 }
339 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
340 default: unreachable("not reached");
341 }
342 }
343 else {
344 /* See GL_ARB_vertex_type_2_10_10_10_rev.
345 * W/A: the hardware doesn't really support the formats we'd
346 * like to use here, so upload everything as UINT and fix
347 * it in the shader
348 */
349 if (glarray->Type == GL_INT_2_10_10_10_REV) {
350 assert(size == 4);
351 if (brw->gen >= 8 || brw->is_haswell) {
352 return glarray->Format == GL_BGRA
353 ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
354 : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
355 }
356 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
357 } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
358 assert(size == 4);
359 if (brw->gen >= 8 || brw->is_haswell) {
360 return glarray->Format == GL_BGRA
361 ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
362 : BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
363 }
364 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
365 }
366 assert(glarray->Format == GL_RGBA); /* sanity check */
367 switch (glarray->Type) {
368 case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
369 case GL_FLOAT: return float_types[size];
370 case GL_HALF_FLOAT:
371 if (brw->gen < 6 && size == 3)
372 return half_float_types[4];
373 else
374 return half_float_types[size];
375 case GL_INT: return int_types_scale[size];
376 case GL_SHORT: return short_types_scale[size];
377 case GL_BYTE: return byte_types_scale[size];
378 case GL_UNSIGNED_INT: return uint_types_scale[size];
379 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
380 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
381 case GL_FIXED:
382 if (brw->gen >= 8 || brw->is_haswell)
383 return fixed_point_types[size];
384
385 /* This produces GL_FIXED inputs as values between INT32_MIN and
386 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
387 */
388 return int_types_scale[size];
389 default: unreachable("not reached");
390 }
391 }
392 }
393
394 static void
395 copy_array_to_vbo_array(struct brw_context *brw,
396 struct brw_vertex_element *element,
397 int min, int max,
398 struct brw_vertex_buffer *buffer,
399 GLuint dst_stride)
400 {
401 const int src_stride = element->glarray->StrideB;
402
403 /* If the source stride is zero, we just want to upload the current
404 * attribute once and set the buffer's stride to 0. There's no need
405 * to replicate it out.
406 */
407 if (src_stride == 0) {
408 intel_upload_data(brw, element->glarray->Ptr,
409 element->glarray->_ElementSize,
410 element->glarray->_ElementSize,
411 &buffer->bo, &buffer->offset);
412
413 buffer->stride = 0;
414 buffer->size = element->glarray->_ElementSize;
415 return;
416 }
417
418 const unsigned char *src = element->glarray->Ptr + min * src_stride;
419 int count = max - min + 1;
420 GLuint size = count * dst_stride;
421 uint8_t *dst = intel_upload_space(brw, size, dst_stride,
422 &buffer->bo, &buffer->offset);
423
424 if (dst_stride == src_stride) {
425 memcpy(dst, src, size);
426 } else {
427 while (count--) {
428 memcpy(dst, src, dst_stride);
429 src += src_stride;
430 dst += dst_stride;
431 }
432 }
433 buffer->stride = dst_stride;
434 buffer->size = size;
435 }
436
437 void
438 brw_prepare_vertices(struct brw_context *brw)
439 {
440 struct gl_context *ctx = &brw->ctx;
441 /* BRW_NEW_VS_PROG_DATA */
442 GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
443 const unsigned char *ptr = NULL;
444 GLuint interleaved = 0;
445 unsigned int min_index = brw->vb.min_index + brw->basevertex;
446 unsigned int max_index = brw->vb.max_index + brw->basevertex;
447 unsigned i;
448 int delta, j;
449
450 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
451 GLuint nr_uploads = 0;
452
453 /* _NEW_POLYGON
454 *
455 * On gen6+, edge flags don't end up in the VUE (either in or out of the
456 * VS). Instead, they're uploaded as the last vertex element, and the data
457 * is passed sideband through the fixed function units. So, we need to
458 * prepare the vertex buffer for it, but it's not present in inputs_read.
459 */
460 if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
461 ctx->Polygon.BackMode != GL_FILL)) {
462 vs_inputs |= VERT_BIT_EDGEFLAG;
463 }
464
465 if (0)
466 fprintf(stderr, "%s %d..%d\n", __func__, min_index, max_index);
467
468 /* Accumulate the list of enabled arrays. */
469 brw->vb.nr_enabled = 0;
470 while (vs_inputs) {
471 GLuint index = ffsll(vs_inputs) - 1;
472 struct brw_vertex_element *input = &brw->vb.inputs[index];
473
474 vs_inputs &= ~BITFIELD64_BIT(index);
475 brw->vb.enabled[brw->vb.nr_enabled++] = input;
476 }
477
478 if (brw->vb.nr_enabled == 0)
479 return;
480
481 if (brw->vb.nr_buffers)
482 return;
483
484 /* The range of data in a given buffer represented as [min, max) */
485 struct intel_buffer_object *enabled_buffer[VERT_ATTRIB_MAX];
486 uint32_t buffer_range_start[VERT_ATTRIB_MAX];
487 uint32_t buffer_range_end[VERT_ATTRIB_MAX];
488
489 for (i = j = 0; i < brw->vb.nr_enabled; i++) {
490 struct brw_vertex_element *input = brw->vb.enabled[i];
491 const struct gl_client_array *glarray = input->glarray;
492
493 if (_mesa_is_bufferobj(glarray->BufferObj)) {
494 struct intel_buffer_object *intel_buffer =
495 intel_buffer_object(glarray->BufferObj);
496
497 const uint32_t offset = (uintptr_t)glarray->Ptr;
498
499 /* Start with the worst case */
500 uint32_t start = 0;
501 uint32_t range = intel_buffer->Base.Size;
502 if (glarray->InstanceDivisor) {
503 if (brw->num_instances) {
504 start = offset + glarray->StrideB * brw->baseinstance;
505 range = (glarray->StrideB * ((brw->num_instances - 1) /
506 glarray->InstanceDivisor) +
507 glarray->_ElementSize);
508 }
509 } else {
510 if (brw->vb.index_bounds_valid) {
511 start = offset + min_index * glarray->StrideB;
512 range = (glarray->StrideB * (max_index - min_index) +
513 glarray->_ElementSize);
514 }
515 }
516
517 /* If we have a VB set to be uploaded for this buffer object
518 * already, reuse that VB state so that we emit fewer
519 * relocations.
520 */
521 unsigned k;
522 for (k = 0; k < i; k++) {
523 const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
524 if (glarray->BufferObj == other->BufferObj &&
525 glarray->StrideB == other->StrideB &&
526 glarray->InstanceDivisor == other->InstanceDivisor &&
527 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
528 {
529 input->buffer = brw->vb.enabled[k]->buffer;
530 input->offset = glarray->Ptr - other->Ptr;
531
532 buffer_range_start[input->buffer] =
533 MIN2(buffer_range_start[input->buffer], start);
534 buffer_range_end[input->buffer] =
535 MAX2(buffer_range_end[input->buffer], start + range);
536 break;
537 }
538 }
539 if (k == i) {
540 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
541
542 /* Named buffer object: Just reference its contents directly. */
543 buffer->offset = offset;
544 buffer->stride = glarray->StrideB;
545 buffer->step_rate = glarray->InstanceDivisor;
546
547 enabled_buffer[j] = intel_buffer;
548 buffer_range_start[j] = start;
549 buffer_range_end[j] = start + range;
550
551 input->buffer = j++;
552 input->offset = 0;
553 }
554
555 /* This is a common place to reach if the user mistakenly supplies
556 * a pointer in place of a VBO offset. If we just let it go through,
557 * we may end up dereferencing a pointer beyond the bounds of the
558 * GTT.
559 *
560 * The VBO spec allows application termination in this case, and it's
561 * probably a service to the poor programmer to do so rather than
562 * trying to just not render.
563 */
564 assert(input->offset < intel_buffer->Base.Size);
565 } else {
566 /* Queue the buffer object up to be uploaded in the next pass,
567 * when we've decided if we're doing interleaved or not.
568 */
569 if (nr_uploads == 0) {
570 interleaved = glarray->StrideB;
571 ptr = glarray->Ptr;
572 }
573 else if (interleaved != glarray->StrideB ||
574 glarray->Ptr < ptr ||
575 (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
576 {
577 /* If our stride is different from the first attribute's stride,
578 * or if the first attribute's stride didn't cover our element,
579 * disable the interleaved upload optimization. The second case
580 * can most commonly occur in cases where there is a single vertex
581 * and, for example, the data is stored on the application's
582 * stack.
583 *
584 * NOTE: This will also disable the optimization in cases where
585 * the data is in a different order than the array indices.
586 * Something like:
587 *
588 * float data[...];
589 * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
590 * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
591 */
592 interleaved = 0;
593 }
594
595 upload[nr_uploads++] = input;
596 }
597 }
598
599 /* Now that we've set up all of the buffers, we walk through and reference
600 * each of them. We do this late so that we get the right size in each
601 * buffer and don't reference too little data.
602 */
603 for (i = 0; i < j; i++) {
604 struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
605 if (buffer->bo)
606 continue;
607
608 const uint32_t start = buffer_range_start[i];
609 const uint32_t range = buffer_range_end[i] - buffer_range_start[i];
610
611 buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start, range);
612 drm_intel_bo_reference(buffer->bo);
613
614 buffer->size = start + range;
615 }
616
617 /* If we need to upload all the arrays, then we can trim those arrays to
618 * only the used elements [min_index, max_index] so long as we adjust all
619 * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
620 */
621 brw->vb.start_vertex_bias = 0;
622 delta = min_index;
623 if (nr_uploads == brw->vb.nr_enabled) {
624 brw->vb.start_vertex_bias = -delta;
625 delta = 0;
626 }
627
628 /* Handle any arrays to be uploaded. */
629 if (nr_uploads > 1) {
630 if (interleaved) {
631 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
632 /* All uploads are interleaved, so upload the arrays together as
633 * interleaved. First, upload the contents and set up upload[0].
634 */
635 copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
636 buffer, interleaved);
637 buffer->offset -= delta * interleaved;
638 buffer->size += delta * interleaved;
639
640 for (i = 0; i < nr_uploads; i++) {
641 /* Then, just point upload[i] at upload[0]'s buffer. */
642 upload[i]->offset =
643 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
644 upload[i]->buffer = j;
645 }
646 j++;
647
648 nr_uploads = 0;
649 }
650 }
651 /* Upload non-interleaved arrays */
652 for (i = 0; i < nr_uploads; i++) {
653 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
654 if (upload[i]->glarray->InstanceDivisor == 0) {
655 copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
656 buffer, upload[i]->glarray->_ElementSize);
657 } else {
658 /* This is an instanced attribute, since its InstanceDivisor
659 * is not zero. Therefore, its data will be stepped after the
660 * instanced draw has been run InstanceDivisor times.
661 */
662 uint32_t instanced_attr_max_index =
663 (brw->num_instances - 1) / upload[i]->glarray->InstanceDivisor;
664 copy_array_to_vbo_array(brw, upload[i], 0, instanced_attr_max_index,
665 buffer, upload[i]->glarray->_ElementSize);
666 }
667 buffer->offset -= delta * buffer->stride;
668 buffer->size += delta * buffer->stride;
669 buffer->step_rate = upload[i]->glarray->InstanceDivisor;
670 upload[i]->buffer = j++;
671 upload[i]->offset = 0;
672 }
673
674 brw->vb.nr_buffers = j;
675 }
676
677 void
678 brw_prepare_shader_draw_parameters(struct brw_context *brw)
679 {
680 /* For non-indirect draws, upload gl_BaseVertex. */
681 if ((brw->vs.prog_data->uses_basevertex ||
682 brw->vs.prog_data->uses_baseinstance) &&
683 brw->draw.draw_params_bo == NULL) {
684 intel_upload_data(brw, &brw->draw.params, sizeof(brw->draw.params), 4,
685 &brw->draw.draw_params_bo,
686 &brw->draw.draw_params_offset);
687 }
688
689 if (brw->vs.prog_data->uses_drawid) {
690 intel_upload_data(brw, &brw->draw.gl_drawid, sizeof(brw->draw.gl_drawid), 4,
691 &brw->draw.draw_id_bo,
692 &brw->draw.draw_id_offset);
693 }
694 }
695
696 /**
697 * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
698 */
699 static uint32_t *
700 emit_vertex_buffer_state(struct brw_context *brw,
701 unsigned buffer_nr,
702 drm_intel_bo *bo,
703 unsigned bo_ending_address,
704 unsigned bo_offset,
705 unsigned stride,
706 unsigned step_rate,
707 uint32_t *__map)
708 {
709 struct gl_context *ctx = &brw->ctx;
710 uint32_t dw0;
711
712 if (brw->gen >= 6) {
713 dw0 = (buffer_nr << GEN6_VB0_INDEX_SHIFT) |
714 (step_rate ? GEN6_VB0_ACCESS_INSTANCEDATA
715 : GEN6_VB0_ACCESS_VERTEXDATA);
716 } else {
717 dw0 = (buffer_nr << BRW_VB0_INDEX_SHIFT) |
718 (step_rate ? BRW_VB0_ACCESS_INSTANCEDATA
719 : BRW_VB0_ACCESS_VERTEXDATA);
720 }
721
722 if (brw->gen >= 7)
723 dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
724
725 if (brw->gen == 7)
726 dw0 |= GEN7_MOCS_L3 << 16;
727
728 WARN_ONCE(stride >= (brw->gen >= 5 ? 2048 : 2047),
729 "VBO stride %d too large, bad rendering may occur\n",
730 stride);
731 OUT_BATCH(dw0 | (stride << BRW_VB0_PITCH_SHIFT));
732 OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_offset);
733 if (brw->gen >= 5) {
734 OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_ending_address);
735 } else {
736 OUT_BATCH(0);
737 }
738 OUT_BATCH(step_rate);
739
740 return __map;
741 }
742 #define EMIT_VERTEX_BUFFER_STATE(...) __map = emit_vertex_buffer_state(__VA_ARGS__, __map)
743
744 static void
745 brw_emit_vertices(struct brw_context *brw)
746 {
747 GLuint i;
748
749 brw_prepare_vertices(brw);
750 brw_prepare_shader_draw_parameters(brw);
751
752 brw_emit_query_begin(brw);
753
754 unsigned nr_elements = brw->vb.nr_enabled;
755 if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid ||
756 brw->vs.prog_data->uses_basevertex || brw->vs.prog_data->uses_baseinstance)
757 ++nr_elements;
758 if (brw->vs.prog_data->uses_drawid)
759 nr_elements++;
760
761 /* If the VS doesn't read any inputs (calculating vertex position from
762 * a state variable for some reason, for example), emit a single pad
763 * VERTEX_ELEMENT struct and bail.
764 *
765 * The stale VB state stays in place, but they don't do anything unless
766 * a VE loads from them.
767 */
768 if (nr_elements == 0) {
769 BEGIN_BATCH(3);
770 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
771 if (brw->gen >= 6) {
772 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
773 GEN6_VE0_VALID |
774 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
775 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
776 } else {
777 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
778 BRW_VE0_VALID |
779 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
780 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
781 }
782 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
783 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
784 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
785 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
786 ADVANCE_BATCH();
787 return;
788 }
789
790 /* Now emit VB and VEP state packets.
791 */
792
793 const bool uses_draw_params =
794 brw->vs.prog_data->uses_basevertex ||
795 brw->vs.prog_data->uses_baseinstance;
796 const unsigned nr_buffers = brw->vb.nr_buffers +
797 uses_draw_params + brw->vs.prog_data->uses_drawid;
798
799 if (nr_buffers) {
800 if (brw->gen >= 6) {
801 assert(nr_buffers <= 33);
802 } else {
803 assert(nr_buffers <= 17);
804 }
805
806 BEGIN_BATCH(1 + 4 * nr_buffers);
807 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
808 for (i = 0; i < brw->vb.nr_buffers; i++) {
809 struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
810 /* Prior to Haswell and Bay Trail we have to use 4-component formats
811 * to fake 3-component ones. In particular, we do this for
812 * half-float and 8 and 16-bit integer formats. This means that the
813 * vertex element may poke over the end of the buffer by 2 bytes.
814 */
815 unsigned padding =
816 (brw->gen <= 7 && !brw->is_baytrail && !brw->is_haswell) * 2;
817 EMIT_VERTEX_BUFFER_STATE(brw, i, buffer->bo,
818 buffer->offset + buffer->size + padding - 1,
819 buffer->offset, buffer->stride,
820 buffer->step_rate);
821
822 }
823
824 if (uses_draw_params) {
825 EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers,
826 brw->draw.draw_params_bo,
827 brw->draw.draw_params_bo->size - 1,
828 brw->draw.draw_params_offset,
829 0, /* stride */
830 0); /* step rate */
831 }
832
833 if (brw->vs.prog_data->uses_drawid) {
834 EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers + 1,
835 brw->draw.draw_id_bo,
836 brw->draw.draw_id_bo->size - 1,
837 brw->draw.draw_id_offset,
838 0, /* stride */
839 0); /* step rate */
840 }
841
842 ADVANCE_BATCH();
843 }
844
845 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
846 * for VertexID/InstanceID.
847 */
848 if (brw->gen >= 6) {
849 assert(nr_elements <= 34);
850 } else {
851 assert(nr_elements <= 18);
852 }
853
854 struct brw_vertex_element *gen6_edgeflag_input = NULL;
855
856 BEGIN_BATCH(1 + nr_elements * 2);
857 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
858 for (i = 0; i < brw->vb.nr_enabled; i++) {
859 struct brw_vertex_element *input = brw->vb.enabled[i];
860 uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
861 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
862 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
863 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
864 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
865
866 if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
867 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
868 * of in the VUE. We have to upload it sideband as the last vertex
869 * element according to the B-Spec.
870 */
871 if (brw->gen >= 6) {
872 gen6_edgeflag_input = input;
873 continue;
874 }
875 }
876
877 switch (input->glarray->Size) {
878 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
879 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
880 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
881 case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
882 : BRW_VE1_COMPONENT_STORE_1_FLT;
883 break;
884 }
885
886 if (brw->gen >= 6) {
887 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
888 GEN6_VE0_VALID |
889 (format << BRW_VE0_FORMAT_SHIFT) |
890 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
891 } else {
892 OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
893 BRW_VE0_VALID |
894 (format << BRW_VE0_FORMAT_SHIFT) |
895 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
896 }
897
898 if (brw->gen >= 5)
899 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
900 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
901 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
902 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
903 else
904 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
905 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
906 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
907 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
908 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
909 }
910
911 if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid ||
912 brw->vs.prog_data->uses_basevertex || brw->vs.prog_data->uses_baseinstance) {
913 uint32_t dw0 = 0, dw1 = 0;
914 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_0;
915 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_0;
916 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_0;
917 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_0;
918
919 if (brw->vs.prog_data->uses_basevertex)
920 comp0 = BRW_VE1_COMPONENT_STORE_SRC;
921
922 if (brw->vs.prog_data->uses_baseinstance)
923 comp1 = BRW_VE1_COMPONENT_STORE_SRC;
924
925 if (brw->vs.prog_data->uses_vertexid)
926 comp2 = BRW_VE1_COMPONENT_STORE_VID;
927
928 if (brw->vs.prog_data->uses_instanceid)
929 comp3 = BRW_VE1_COMPONENT_STORE_IID;
930
931 dw1 = (comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
932 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
933 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
934 (comp3 << BRW_VE1_COMPONENT_3_SHIFT);
935
936 if (brw->gen >= 6) {
937 dw0 |= GEN6_VE0_VALID |
938 brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
939 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
940 } else {
941 dw0 |= BRW_VE0_VALID |
942 brw->vb.nr_buffers << BRW_VE0_INDEX_SHIFT |
943 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
944 dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
945 }
946
947 /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
948 * the format is ignored and the value is always int.
949 */
950
951 OUT_BATCH(dw0);
952 OUT_BATCH(dw1);
953 }
954
955 if (brw->vs.prog_data->uses_drawid) {
956 uint32_t dw0 = 0, dw1 = 0;
957
958 dw1 = (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
959 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
960 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
961 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT);
962
963 if (brw->gen >= 6) {
964 dw0 |= GEN6_VE0_VALID |
965 ((brw->vb.nr_buffers + 1) << GEN6_VE0_INDEX_SHIFT) |
966 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
967 } else {
968 dw0 |= BRW_VE0_VALID |
969 ((brw->vb.nr_buffers + 1) << BRW_VE0_INDEX_SHIFT) |
970 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
971
972 dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
973 }
974
975 OUT_BATCH(dw0);
976 OUT_BATCH(dw1);
977 }
978
979 if (brw->gen >= 6 && gen6_edgeflag_input) {
980 uint32_t format =
981 brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
982
983 OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
984 GEN6_VE0_VALID |
985 GEN6_VE0_EDGE_FLAG_ENABLE |
986 (format << BRW_VE0_FORMAT_SHIFT) |
987 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
988 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
989 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
990 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
991 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
992 }
993
994 ADVANCE_BATCH();
995 }
996
997 const struct brw_tracked_state brw_vertices = {
998 .dirty = {
999 .mesa = _NEW_POLYGON,
1000 .brw = BRW_NEW_BATCH |
1001 BRW_NEW_BLORP |
1002 BRW_NEW_VERTICES |
1003 BRW_NEW_VS_PROG_DATA,
1004 },
1005 .emit = brw_emit_vertices,
1006 };
1007
1008 static void
1009 brw_upload_indices(struct brw_context *brw)
1010 {
1011 struct gl_context *ctx = &brw->ctx;
1012 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
1013 GLuint ib_size;
1014 drm_intel_bo *old_bo = brw->ib.bo;
1015 struct gl_buffer_object *bufferobj;
1016 GLuint offset;
1017 GLuint ib_type_size;
1018
1019 if (index_buffer == NULL)
1020 return;
1021
1022 ib_type_size = _mesa_sizeof_type(index_buffer->type);
1023 ib_size = index_buffer->count ? ib_type_size * index_buffer->count :
1024 index_buffer->obj->Size;
1025 bufferobj = index_buffer->obj;
1026
1027 /* Turn into a proper VBO:
1028 */
1029 if (!_mesa_is_bufferobj(bufferobj)) {
1030 /* Get new bufferobj, offset:
1031 */
1032 intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
1033 &brw->ib.bo, &offset);
1034 brw->ib.size = brw->ib.bo->size;
1035 } else {
1036 offset = (GLuint) (unsigned long) index_buffer->ptr;
1037
1038 /* If the index buffer isn't aligned to its element size, we have to
1039 * rebase it into a temporary.
1040 */
1041 if ((ib_type_size - 1) & offset) {
1042 perf_debug("copying index buffer to a temporary to work around "
1043 "misaligned offset %d\n", offset);
1044
1045 GLubyte *map = ctx->Driver.MapBufferRange(ctx,
1046 offset,
1047 ib_size,
1048 GL_MAP_READ_BIT,
1049 bufferobj,
1050 MAP_INTERNAL);
1051
1052 intel_upload_data(brw, map, ib_size, ib_type_size,
1053 &brw->ib.bo, &offset);
1054 brw->ib.size = brw->ib.bo->size;
1055
1056 ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL);
1057 } else {
1058 drm_intel_bo *bo =
1059 intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
1060 offset, ib_size);
1061 if (bo != brw->ib.bo) {
1062 drm_intel_bo_unreference(brw->ib.bo);
1063 brw->ib.bo = bo;
1064 brw->ib.size = bufferobj->Size;
1065 drm_intel_bo_reference(bo);
1066 }
1067 }
1068 }
1069
1070 /* Use 3DPRIMITIVE's start_vertex_offset to avoid re-uploading
1071 * the index buffer state when we're just moving the start index
1072 * of our drawing.
1073 */
1074 brw->ib.start_vertex_offset = offset / ib_type_size;
1075
1076 if (brw->ib.bo != old_bo)
1077 brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1078
1079 if (index_buffer->type != brw->ib.type) {
1080 brw->ib.type = index_buffer->type;
1081 brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1082 }
1083 }
1084
1085 const struct brw_tracked_state brw_indices = {
1086 .dirty = {
1087 .mesa = 0,
1088 .brw = BRW_NEW_BLORP |
1089 BRW_NEW_INDICES,
1090 },
1091 .emit = brw_upload_indices,
1092 };
1093
1094 static void
1095 brw_emit_index_buffer(struct brw_context *brw)
1096 {
1097 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
1098 GLuint cut_index_setting;
1099
1100 if (index_buffer == NULL)
1101 return;
1102
1103 if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
1104 cut_index_setting = BRW_CUT_INDEX_ENABLE;
1105 } else {
1106 cut_index_setting = 0;
1107 }
1108
1109 BEGIN_BATCH(3);
1110 OUT_BATCH(CMD_INDEX_BUFFER << 16 |
1111 cut_index_setting |
1112 brw_get_index_type(index_buffer->type) |
1113 1);
1114 OUT_RELOC(brw->ib.bo,
1115 I915_GEM_DOMAIN_VERTEX, 0,
1116 0);
1117 OUT_RELOC(brw->ib.bo,
1118 I915_GEM_DOMAIN_VERTEX, 0,
1119 brw->ib.size - 1);
1120 ADVANCE_BATCH();
1121 }
1122
1123 const struct brw_tracked_state brw_index_buffer = {
1124 .dirty = {
1125 .mesa = 0,
1126 .brw = BRW_NEW_BATCH |
1127 BRW_NEW_BLORP |
1128 BRW_NEW_INDEX_BUFFER,
1129 },
1130 .emit = brw_emit_index_buffer,
1131 };