Merge commit 'origin/gallium-0.1' into gallium-0.2
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdlib.h>
29
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/state.h"
33 #include "main/api_validate.h"
34 #include "main/enums.h"
35
36 #include "brw_draw.h"
37 #include "brw_defines.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_fallback.h"
41
42 #include "intel_batchbuffer.h"
43 #include "intel_buffer_objects.h"
44 #include "intel_tex.h"
45
46 static GLuint double_types[5] = {
47 0,
48 BRW_SURFACEFORMAT_R64_FLOAT,
49 BRW_SURFACEFORMAT_R64G64_FLOAT,
50 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
51 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
52 };
53
54 static GLuint float_types[5] = {
55 0,
56 BRW_SURFACEFORMAT_R32_FLOAT,
57 BRW_SURFACEFORMAT_R32G32_FLOAT,
58 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
59 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
60 };
61
62 static GLuint uint_types_norm[5] = {
63 0,
64 BRW_SURFACEFORMAT_R32_UNORM,
65 BRW_SURFACEFORMAT_R32G32_UNORM,
66 BRW_SURFACEFORMAT_R32G32B32_UNORM,
67 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
68 };
69
70 static GLuint uint_types_scale[5] = {
71 0,
72 BRW_SURFACEFORMAT_R32_USCALED,
73 BRW_SURFACEFORMAT_R32G32_USCALED,
74 BRW_SURFACEFORMAT_R32G32B32_USCALED,
75 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
76 };
77
78 static GLuint int_types_norm[5] = {
79 0,
80 BRW_SURFACEFORMAT_R32_SNORM,
81 BRW_SURFACEFORMAT_R32G32_SNORM,
82 BRW_SURFACEFORMAT_R32G32B32_SNORM,
83 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
84 };
85
86 static GLuint int_types_scale[5] = {
87 0,
88 BRW_SURFACEFORMAT_R32_SSCALED,
89 BRW_SURFACEFORMAT_R32G32_SSCALED,
90 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
91 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
92 };
93
94 static GLuint ushort_types_norm[5] = {
95 0,
96 BRW_SURFACEFORMAT_R16_UNORM,
97 BRW_SURFACEFORMAT_R16G16_UNORM,
98 BRW_SURFACEFORMAT_R16G16B16_UNORM,
99 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
100 };
101
102 static GLuint ushort_types_scale[5] = {
103 0,
104 BRW_SURFACEFORMAT_R16_USCALED,
105 BRW_SURFACEFORMAT_R16G16_USCALED,
106 BRW_SURFACEFORMAT_R16G16B16_USCALED,
107 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
108 };
109
110 static GLuint short_types_norm[5] = {
111 0,
112 BRW_SURFACEFORMAT_R16_SNORM,
113 BRW_SURFACEFORMAT_R16G16_SNORM,
114 BRW_SURFACEFORMAT_R16G16B16_SNORM,
115 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
116 };
117
118 static GLuint short_types_scale[5] = {
119 0,
120 BRW_SURFACEFORMAT_R16_SSCALED,
121 BRW_SURFACEFORMAT_R16G16_SSCALED,
122 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
123 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
124 };
125
126 static GLuint ubyte_types_norm[5] = {
127 0,
128 BRW_SURFACEFORMAT_R8_UNORM,
129 BRW_SURFACEFORMAT_R8G8_UNORM,
130 BRW_SURFACEFORMAT_R8G8B8_UNORM,
131 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
132 };
133
134 static GLuint ubyte_types_scale[5] = {
135 0,
136 BRW_SURFACEFORMAT_R8_USCALED,
137 BRW_SURFACEFORMAT_R8G8_USCALED,
138 BRW_SURFACEFORMAT_R8G8B8_USCALED,
139 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
140 };
141
142 static GLuint byte_types_norm[5] = {
143 0,
144 BRW_SURFACEFORMAT_R8_SNORM,
145 BRW_SURFACEFORMAT_R8G8_SNORM,
146 BRW_SURFACEFORMAT_R8G8B8_SNORM,
147 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
148 };
149
150 static GLuint byte_types_scale[5] = {
151 0,
152 BRW_SURFACEFORMAT_R8_SSCALED,
153 BRW_SURFACEFORMAT_R8G8_SSCALED,
154 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
155 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
156 };
157
158
159 static GLuint get_surface_type( GLenum type, GLuint size, GLboolean normalized )
160 {
161 if (INTEL_DEBUG & DEBUG_VERTS)
162 _mesa_printf("type %s size %d normalized %d\n",
163 _mesa_lookup_enum_by_nr(type), size, normalized);
164
165 if (normalized) {
166 switch (type) {
167 case GL_DOUBLE: return double_types[size];
168 case GL_FLOAT: return float_types[size];
169 case GL_INT: return int_types_norm[size];
170 case GL_SHORT: return short_types_norm[size];
171 case GL_BYTE: return byte_types_norm[size];
172 case GL_UNSIGNED_INT: return uint_types_norm[size];
173 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
174 case GL_UNSIGNED_BYTE: return ubyte_types_norm[size];
175 default: assert(0); return 0;
176 }
177 }
178 else {
179 switch (type) {
180 case GL_DOUBLE: return double_types[size];
181 case GL_FLOAT: return float_types[size];
182 case GL_INT: return int_types_scale[size];
183 case GL_SHORT: return short_types_scale[size];
184 case GL_BYTE: return byte_types_scale[size];
185 case GL_UNSIGNED_INT: return uint_types_scale[size];
186 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
187 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
188 default: assert(0); return 0;
189 }
190 }
191 }
192
193
194 static GLuint get_size( GLenum type )
195 {
196 switch (type) {
197 case GL_DOUBLE: return sizeof(GLdouble);
198 case GL_FLOAT: return sizeof(GLfloat);
199 case GL_INT: return sizeof(GLint);
200 case GL_SHORT: return sizeof(GLshort);
201 case GL_BYTE: return sizeof(GLbyte);
202 case GL_UNSIGNED_INT: return sizeof(GLuint);
203 case GL_UNSIGNED_SHORT: return sizeof(GLushort);
204 case GL_UNSIGNED_BYTE: return sizeof(GLubyte);
205 default: return 0;
206 }
207 }
208
209 static GLuint get_index_type(GLenum type)
210 {
211 switch (type) {
212 case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
213 case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
214 case GL_UNSIGNED_INT: return BRW_INDEX_DWORD;
215 default: assert(0); return 0;
216 }
217 }
218
219 static void wrap_buffers( struct brw_context *brw,
220 GLuint size )
221 {
222 if (size < BRW_UPLOAD_INIT_SIZE)
223 size = BRW_UPLOAD_INIT_SIZE;
224
225 brw->vb.upload.offset = 0;
226
227 if (brw->vb.upload.bo != NULL)
228 dri_bo_unreference(brw->vb.upload.bo);
229 brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
230 size, 1);
231
232 /* Set the internal VBO\ to no-backing-store. We only use them as a
233 * temporary within a brw_try_draw_prims while the lock is held.
234 */
235 /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH
236 FAKE TO PUSH THIS STUFF */
237 // if (!brw->intel.ttm)
238 // dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL);
239 }
240
241 static void get_space( struct brw_context *brw,
242 GLuint size,
243 dri_bo **bo_return,
244 GLuint *offset_return )
245 {
246 size = ALIGN(size, 64);
247
248 if (brw->vb.upload.bo == NULL ||
249 brw->vb.upload.offset + size > brw->vb.upload.bo->size) {
250 wrap_buffers(brw, size);
251 }
252
253 assert(*bo_return == NULL);
254 dri_bo_reference(brw->vb.upload.bo);
255 *bo_return = brw->vb.upload.bo;
256 *offset_return = brw->vb.upload.offset;
257 brw->vb.upload.offset += size;
258 }
259
260 static void
261 copy_array_to_vbo_array( struct brw_context *brw,
262 struct brw_vertex_element *element,
263 GLuint dst_stride)
264 {
265 GLuint size = element->count * dst_stride;
266
267 get_space(brw, size, &element->bo, &element->offset);
268
269 if (element->glarray->StrideB == 0) {
270 assert(element->count == 1);
271 element->stride = 0;
272 } else {
273 element->stride = dst_stride;
274 }
275
276 if (dst_stride == element->glarray->StrideB) {
277 dri_bo_subdata(element->bo,
278 element->offset,
279 size,
280 element->glarray->Ptr);
281 } else {
282 void *data;
283 char *dest;
284 const char *src = element->glarray->Ptr;
285 int i;
286
287 data = _mesa_malloc(dst_stride * element->count);
288 dest = data;
289 for (i = 0; i < element->count; i++) {
290 memcpy(dest, src, dst_stride);
291 src += element->glarray->StrideB;
292 dest += dst_stride;
293 }
294
295 dri_bo_subdata(element->bo,
296 element->offset,
297 size,
298 data);
299 _mesa_free(data);
300 }
301 }
302
303 static void brw_prepare_vertices(struct brw_context *brw)
304 {
305 GLcontext *ctx = &brw->intel.ctx;
306 struct intel_context *intel = intel_context(ctx);
307 GLuint tmp = brw->vs.prog_data->inputs_read;
308 GLuint i;
309 const unsigned char *ptr = NULL;
310 GLuint interleave = 0;
311 unsigned int min_index = brw->vb.min_index;
312 unsigned int max_index = brw->vb.max_index;
313
314 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
315 GLuint nr_enabled = 0;
316
317 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
318 GLuint nr_uploads = 0;
319
320 /* First build an array of pointers to ve's in vb.inputs_read
321 */
322 if (0)
323 _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
324
325 /* Accumulate the list of enabled arrays. */
326 while (tmp) {
327 GLuint i = _mesa_ffsll(tmp)-1;
328 struct brw_vertex_element *input = &brw->vb.inputs[i];
329
330 tmp &= ~(1<<i);
331 enabled[nr_enabled++] = input;
332 }
333
334 /* XXX: In the rare cases where this happens we fallback all
335 * the way to software rasterization, although a tnl fallback
336 * would be sufficient. I don't know of *any* real world
337 * cases with > 17 vertex attributes enabled, so it probably
338 * isn't an issue at this point.
339 */
340 if (nr_enabled >= BRW_VEP_MAX) {
341 intel->Fallback = 1;
342 return;
343 }
344
345 for (i = 0; i < nr_enabled; i++) {
346 struct brw_vertex_element *input = enabled[i];
347
348 input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
349 input->count = input->glarray->StrideB ? max_index + 1 - min_index : 1;
350
351 if (input->glarray->BufferObj->Name != 0) {
352 struct intel_buffer_object *intel_buffer =
353 intel_buffer_object(input->glarray->BufferObj);
354
355 /* Named buffer object: Just reference its contents directly. */
356 dri_bo_unreference(input->bo);
357 input->bo = intel_bufferobj_buffer(intel, intel_buffer,
358 INTEL_READ);
359 dri_bo_reference(input->bo);
360 input->offset = (unsigned long)input->glarray->Ptr;
361 input->stride = input->glarray->StrideB;
362 } else {
363 if (input->bo != NULL) {
364 /* Already-uploaded vertex data is present from a previous
365 * prepare_vertices, but we had to re-validate state due to
366 * check_aperture failing and a new batch being produced.
367 */
368 continue;
369 }
370
371 /* Queue the buffer object up to be uploaded in the next pass,
372 * when we've decided if we're doing interleaved or not.
373 */
374 if (i == 0) {
375 /* Position array not properly enabled:
376 */
377 if (input->glarray->StrideB == 0) {
378 intel->Fallback = 1;
379 return;
380 }
381
382 interleave = input->glarray->StrideB;
383 ptr = input->glarray->Ptr;
384 }
385 else if (interleave != input->glarray->StrideB ||
386 (const unsigned char *)input->glarray->Ptr - ptr < 0 ||
387 (const unsigned char *)input->glarray->Ptr - ptr > interleave)
388 {
389 interleave = 0;
390 }
391
392 upload[nr_uploads++] = input;
393
394 /* We rebase drawing to start at element zero only when
395 * varyings are not in vbos, which means we can end up
396 * uploading non-varying arrays (stride != 0) when min_index
397 * is zero. This doesn't matter as the amount to upload is
398 * the same for these arrays whether the draw call is rebased
399 * or not - we just have to upload the one element.
400 */
401 assert(min_index == 0 || input->glarray->StrideB == 0);
402 }
403 }
404
405 /* Handle any arrays to be uploaded. */
406 if (nr_uploads > 1 && interleave && interleave <= 256) {
407 /* All uploads are interleaved, so upload the arrays together as
408 * interleaved. First, upload the contents and set up upload[0].
409 */
410 copy_array_to_vbo_array(brw, upload[0], interleave);
411
412 for (i = 1; i < nr_uploads; i++) {
413 /* Then, just point upload[i] at upload[0]'s buffer. */
414 upload[i]->stride = interleave;
415 upload[i]->offset = upload[0]->offset +
416 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
417 upload[i]->bo = upload[0]->bo;
418 dri_bo_reference(upload[i]->bo);
419 }
420 }
421 else {
422 /* Upload non-interleaved arrays */
423 for (i = 0; i < nr_uploads; i++) {
424 copy_array_to_vbo_array(brw, upload[i], upload[i]->element_size);
425 }
426 }
427
428 brw_prepare_query_begin(brw);
429
430 for (i = 0; i < nr_enabled; i++) {
431 struct brw_vertex_element *input = enabled[i];
432
433 brw_add_validated_bo(brw, input->bo);
434 }
435 }
436
437 static void brw_emit_vertices(struct brw_context *brw)
438 {
439 GLcontext *ctx = &brw->intel.ctx;
440 struct intel_context *intel = intel_context(ctx);
441 GLuint tmp = brw->vs.prog_data->inputs_read;
442 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
443 GLuint i;
444 GLuint nr_enabled = 0;
445
446 /* Accumulate the list of enabled arrays. */
447 while (tmp) {
448 i = _mesa_ffsll(tmp)-1;
449 struct brw_vertex_element *input = &brw->vb.inputs[i];
450
451 tmp &= ~(1<<i);
452 enabled[nr_enabled++] = input;
453 }
454
455 brw_emit_query_begin(brw);
456
457 /* Now emit VB and VEP state packets.
458 *
459 * This still defines a hardware VB for each input, even if they
460 * are interleaved or from the same VBO. TBD if this makes a
461 * performance difference.
462 */
463 BEGIN_BATCH(1 + nr_enabled * 4, IGNORE_CLIPRECTS);
464 OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
465 ((1 + nr_enabled * 4) - 2));
466
467 for (i = 0; i < nr_enabled; i++) {
468 struct brw_vertex_element *input = enabled[i];
469
470 OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
471 BRW_VB0_ACCESS_VERTEXDATA |
472 (input->stride << BRW_VB0_PITCH_SHIFT));
473 OUT_RELOC(input->bo,
474 I915_GEM_DOMAIN_VERTEX, 0,
475 input->offset);
476 OUT_BATCH(brw->vb.max_index);
477 OUT_BATCH(0); /* Instance data step rate */
478 }
479 ADVANCE_BATCH();
480
481 BEGIN_BATCH(1 + nr_enabled * 2, IGNORE_CLIPRECTS);
482 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + nr_enabled * 2) - 2));
483 for (i = 0; i < nr_enabled; i++) {
484 struct brw_vertex_element *input = enabled[i];
485 uint32_t format = get_surface_type(input->glarray->Type,
486 input->glarray->Size,
487 input->glarray->Normalized);
488 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
489 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
490 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
491 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
492
493 switch (input->glarray->Size) {
494 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
495 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
496 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
497 case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT;
498 break;
499 }
500
501 OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
502 BRW_VE0_VALID |
503 (format << BRW_VE0_FORMAT_SHIFT) |
504 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
505 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
506 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
507 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
508 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
509 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
510 }
511 ADVANCE_BATCH();
512 }
513
514 const struct brw_tracked_state brw_vertices = {
515 .dirty = {
516 .mesa = 0,
517 .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
518 .cache = 0,
519 },
520 .prepare = brw_prepare_vertices,
521 .emit = brw_emit_vertices,
522 };
523
524 static void brw_prepare_indices(struct brw_context *brw)
525 {
526 GLcontext *ctx = &brw->intel.ctx;
527 struct intel_context *intel = &brw->intel;
528 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
529 GLuint ib_size;
530 dri_bo *bo = NULL;
531 struct gl_buffer_object *bufferobj;
532 GLuint offset;
533
534 if (index_buffer == NULL)
535 return;
536
537 ib_size = get_size(index_buffer->type) * index_buffer->count;
538 bufferobj = index_buffer->obj;;
539
540 /* Turn into a proper VBO:
541 */
542 if (!bufferobj->Name) {
543
544 /* Get new bufferobj, offset:
545 */
546 get_space(brw, ib_size, &bo, &offset);
547
548 /* Straight upload
549 */
550 dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
551 } else {
552 offset = (GLuint)index_buffer->ptr;
553
554 /* If the index buffer isn't aligned to its element size, we have to
555 * rebase it into a temporary.
556 */
557 if ((get_size(index_buffer->type) - 1) & offset) {
558 GLubyte *map = ctx->Driver.MapBuffer(ctx,
559 GL_ELEMENT_ARRAY_BUFFER_ARB,
560 GL_DYNAMIC_DRAW_ARB,
561 bufferobj);
562 map += offset;
563
564 get_space(brw, ib_size, &bo, &offset);
565
566 dri_bo_subdata(bo, offset, ib_size, map);
567
568 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
569 } else {
570 bo = intel_bufferobj_buffer(intel, intel_buffer_object(bufferobj),
571 INTEL_READ);
572 dri_bo_reference(bo);
573 }
574 }
575
576 dri_bo_unreference(brw->ib.bo);
577 brw->ib.bo = bo;
578 brw->ib.offset = offset;
579
580 brw_add_validated_bo(brw, brw->ib.bo);
581 }
582
583 static void brw_emit_indices(struct brw_context *brw)
584 {
585 struct intel_context *intel = &brw->intel;
586 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
587 GLuint ib_size;
588
589 if (index_buffer == NULL)
590 return;
591
592 ib_size = get_size(index_buffer->type) * index_buffer->count;
593
594 /* Emit the indexbuffer packet:
595 */
596 {
597 struct brw_indexbuffer ib;
598
599 memset(&ib, 0, sizeof(ib));
600
601 ib.header.bits.opcode = CMD_INDEX_BUFFER;
602 ib.header.bits.length = sizeof(ib)/4 - 2;
603 ib.header.bits.index_format = get_index_type(index_buffer->type);
604 ib.header.bits.cut_index_enable = 0;
605
606
607 BEGIN_BATCH(4, IGNORE_CLIPRECTS);
608 OUT_BATCH( ib.header.dword );
609 OUT_RELOC(brw->ib.bo,
610 I915_GEM_DOMAIN_VERTEX, 0,
611 brw->ib.offset);
612 OUT_RELOC(brw->ib.bo,
613 I915_GEM_DOMAIN_VERTEX, 0,
614 brw->ib.offset + ib_size);
615 OUT_BATCH( 0 );
616 ADVANCE_BATCH();
617 }
618 }
619
620 const struct brw_tracked_state brw_indices = {
621 .dirty = {
622 .mesa = 0,
623 .brw = BRW_NEW_BATCH | BRW_NEW_INDICES,
624 .cache = 0,
625 },
626 .prepare = brw_prepare_indices,
627 .emit = brw_emit_indices,
628 };