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i965: Eliminate brw->vs.prog_data pointer.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/bufferobj.h"
27 #include "main/context.h"
28 #include "main/enums.h"
29 #include "main/macros.h"
30 #include "main/glformats.h"
31
32 #include "brw_draw.h"
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
36
37 #include "intel_batchbuffer.h"
38 #include "intel_buffer_objects.h"
39
40 static const GLuint double_types_float[5] = {
41 0,
42 BRW_SURFACEFORMAT_R64_FLOAT,
43 BRW_SURFACEFORMAT_R64G64_FLOAT,
44 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
45 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
46 };
47
48 static const GLuint double_types_passthru[5] = {
49 0,
50 BRW_SURFACEFORMAT_R64_PASSTHRU,
51 BRW_SURFACEFORMAT_R64G64_PASSTHRU,
52 BRW_SURFACEFORMAT_R64G64B64_PASSTHRU,
53 BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU
54 };
55
56 static const GLuint float_types[5] = {
57 0,
58 BRW_SURFACEFORMAT_R32_FLOAT,
59 BRW_SURFACEFORMAT_R32G32_FLOAT,
60 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
61 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
62 };
63
64 static const GLuint half_float_types[5] = {
65 0,
66 BRW_SURFACEFORMAT_R16_FLOAT,
67 BRW_SURFACEFORMAT_R16G16_FLOAT,
68 BRW_SURFACEFORMAT_R16G16B16_FLOAT,
69 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
70 };
71
72 static const GLuint fixed_point_types[5] = {
73 0,
74 BRW_SURFACEFORMAT_R32_SFIXED,
75 BRW_SURFACEFORMAT_R32G32_SFIXED,
76 BRW_SURFACEFORMAT_R32G32B32_SFIXED,
77 BRW_SURFACEFORMAT_R32G32B32A32_SFIXED,
78 };
79
80 static const GLuint uint_types_direct[5] = {
81 0,
82 BRW_SURFACEFORMAT_R32_UINT,
83 BRW_SURFACEFORMAT_R32G32_UINT,
84 BRW_SURFACEFORMAT_R32G32B32_UINT,
85 BRW_SURFACEFORMAT_R32G32B32A32_UINT
86 };
87
88 static const GLuint uint_types_norm[5] = {
89 0,
90 BRW_SURFACEFORMAT_R32_UNORM,
91 BRW_SURFACEFORMAT_R32G32_UNORM,
92 BRW_SURFACEFORMAT_R32G32B32_UNORM,
93 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
94 };
95
96 static const GLuint uint_types_scale[5] = {
97 0,
98 BRW_SURFACEFORMAT_R32_USCALED,
99 BRW_SURFACEFORMAT_R32G32_USCALED,
100 BRW_SURFACEFORMAT_R32G32B32_USCALED,
101 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
102 };
103
104 static const GLuint int_types_direct[5] = {
105 0,
106 BRW_SURFACEFORMAT_R32_SINT,
107 BRW_SURFACEFORMAT_R32G32_SINT,
108 BRW_SURFACEFORMAT_R32G32B32_SINT,
109 BRW_SURFACEFORMAT_R32G32B32A32_SINT
110 };
111
112 static const GLuint int_types_norm[5] = {
113 0,
114 BRW_SURFACEFORMAT_R32_SNORM,
115 BRW_SURFACEFORMAT_R32G32_SNORM,
116 BRW_SURFACEFORMAT_R32G32B32_SNORM,
117 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
118 };
119
120 static const GLuint int_types_scale[5] = {
121 0,
122 BRW_SURFACEFORMAT_R32_SSCALED,
123 BRW_SURFACEFORMAT_R32G32_SSCALED,
124 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
125 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
126 };
127
128 static const GLuint ushort_types_direct[5] = {
129 0,
130 BRW_SURFACEFORMAT_R16_UINT,
131 BRW_SURFACEFORMAT_R16G16_UINT,
132 BRW_SURFACEFORMAT_R16G16B16_UINT,
133 BRW_SURFACEFORMAT_R16G16B16A16_UINT
134 };
135
136 static const GLuint ushort_types_norm[5] = {
137 0,
138 BRW_SURFACEFORMAT_R16_UNORM,
139 BRW_SURFACEFORMAT_R16G16_UNORM,
140 BRW_SURFACEFORMAT_R16G16B16_UNORM,
141 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
142 };
143
144 static const GLuint ushort_types_scale[5] = {
145 0,
146 BRW_SURFACEFORMAT_R16_USCALED,
147 BRW_SURFACEFORMAT_R16G16_USCALED,
148 BRW_SURFACEFORMAT_R16G16B16_USCALED,
149 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
150 };
151
152 static const GLuint short_types_direct[5] = {
153 0,
154 BRW_SURFACEFORMAT_R16_SINT,
155 BRW_SURFACEFORMAT_R16G16_SINT,
156 BRW_SURFACEFORMAT_R16G16B16_SINT,
157 BRW_SURFACEFORMAT_R16G16B16A16_SINT
158 };
159
160 static const GLuint short_types_norm[5] = {
161 0,
162 BRW_SURFACEFORMAT_R16_SNORM,
163 BRW_SURFACEFORMAT_R16G16_SNORM,
164 BRW_SURFACEFORMAT_R16G16B16_SNORM,
165 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
166 };
167
168 static const GLuint short_types_scale[5] = {
169 0,
170 BRW_SURFACEFORMAT_R16_SSCALED,
171 BRW_SURFACEFORMAT_R16G16_SSCALED,
172 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
173 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
174 };
175
176 static const GLuint ubyte_types_direct[5] = {
177 0,
178 BRW_SURFACEFORMAT_R8_UINT,
179 BRW_SURFACEFORMAT_R8G8_UINT,
180 BRW_SURFACEFORMAT_R8G8B8_UINT,
181 BRW_SURFACEFORMAT_R8G8B8A8_UINT
182 };
183
184 static const GLuint ubyte_types_norm[5] = {
185 0,
186 BRW_SURFACEFORMAT_R8_UNORM,
187 BRW_SURFACEFORMAT_R8G8_UNORM,
188 BRW_SURFACEFORMAT_R8G8B8_UNORM,
189 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
190 };
191
192 static const GLuint ubyte_types_scale[5] = {
193 0,
194 BRW_SURFACEFORMAT_R8_USCALED,
195 BRW_SURFACEFORMAT_R8G8_USCALED,
196 BRW_SURFACEFORMAT_R8G8B8_USCALED,
197 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
198 };
199
200 static const GLuint byte_types_direct[5] = {
201 0,
202 BRW_SURFACEFORMAT_R8_SINT,
203 BRW_SURFACEFORMAT_R8G8_SINT,
204 BRW_SURFACEFORMAT_R8G8B8_SINT,
205 BRW_SURFACEFORMAT_R8G8B8A8_SINT
206 };
207
208 static const GLuint byte_types_norm[5] = {
209 0,
210 BRW_SURFACEFORMAT_R8_SNORM,
211 BRW_SURFACEFORMAT_R8G8_SNORM,
212 BRW_SURFACEFORMAT_R8G8B8_SNORM,
213 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
214 };
215
216 static const GLuint byte_types_scale[5] = {
217 0,
218 BRW_SURFACEFORMAT_R8_SSCALED,
219 BRW_SURFACEFORMAT_R8G8_SSCALED,
220 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
221 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
222 };
223
224 static GLuint
225 double_types(struct brw_context *brw,
226 int size,
227 GLboolean doubles)
228 {
229 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
230 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
231 * 64-bit components are stored in the URB without any conversion."
232 * Also included on BDW PRM, Volume 7, page 470, table "Source Element
233 * Formats Supported in VF Unit"
234 * Previous PRMs don't include those references.
235 */
236 return (brw->gen >= 8 && doubles
237 ? double_types_passthru[size]
238 : double_types_float[size]);
239 }
240
241 /**
242 * Given vertex array type/size/format/normalized info, return
243 * the appopriate hardware surface type.
244 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
245 */
246 unsigned
247 brw_get_vertex_surface_type(struct brw_context *brw,
248 const struct gl_client_array *glarray)
249 {
250 int size = glarray->Size;
251 const bool is_ivybridge_or_older =
252 brw->gen <= 7 && !brw->is_baytrail && !brw->is_haswell;
253
254 if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
255 fprintf(stderr, "type %s size %d normalized %d\n",
256 _mesa_enum_to_string(glarray->Type),
257 glarray->Size, glarray->Normalized);
258
259 if (glarray->Integer) {
260 assert(glarray->Format == GL_RGBA); /* sanity check */
261 switch (glarray->Type) {
262 case GL_INT: return int_types_direct[size];
263 case GL_SHORT:
264 if (is_ivybridge_or_older && size == 3)
265 return short_types_direct[4];
266 else
267 return short_types_direct[size];
268 case GL_BYTE:
269 if (is_ivybridge_or_older && size == 3)
270 return byte_types_direct[4];
271 else
272 return byte_types_direct[size];
273 case GL_UNSIGNED_INT: return uint_types_direct[size];
274 case GL_UNSIGNED_SHORT:
275 if (is_ivybridge_or_older && size == 3)
276 return ushort_types_direct[4];
277 else
278 return ushort_types_direct[size];
279 case GL_UNSIGNED_BYTE:
280 if (is_ivybridge_or_older && size == 3)
281 return ubyte_types_direct[4];
282 else
283 return ubyte_types_direct[size];
284 default: unreachable("not reached");
285 }
286 } else if (glarray->Type == GL_UNSIGNED_INT_10F_11F_11F_REV) {
287 return BRW_SURFACEFORMAT_R11G11B10_FLOAT;
288 } else if (glarray->Normalized) {
289 switch (glarray->Type) {
290 case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
291 case GL_FLOAT: return float_types[size];
292 case GL_HALF_FLOAT:
293 if (brw->gen < 6 && size == 3)
294 return half_float_types[4];
295 else
296 return half_float_types[size];
297 case GL_INT: return int_types_norm[size];
298 case GL_SHORT: return short_types_norm[size];
299 case GL_BYTE: return byte_types_norm[size];
300 case GL_UNSIGNED_INT: return uint_types_norm[size];
301 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
302 case GL_UNSIGNED_BYTE:
303 if (glarray->Format == GL_BGRA) {
304 /* See GL_EXT_vertex_array_bgra */
305 assert(size == 4);
306 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
307 }
308 else {
309 return ubyte_types_norm[size];
310 }
311 case GL_FIXED:
312 if (brw->gen >= 8 || brw->is_haswell)
313 return fixed_point_types[size];
314
315 /* This produces GL_FIXED inputs as values between INT32_MIN and
316 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
317 */
318 return int_types_scale[size];
319 /* See GL_ARB_vertex_type_2_10_10_10_rev.
320 * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
321 * like to use here, so upload everything as UINT and fix
322 * it in the shader
323 */
324 case GL_INT_2_10_10_10_REV:
325 assert(size == 4);
326 if (brw->gen >= 8 || brw->is_haswell) {
327 return glarray->Format == GL_BGRA
328 ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
329 : BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
330 }
331 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
332 case GL_UNSIGNED_INT_2_10_10_10_REV:
333 assert(size == 4);
334 if (brw->gen >= 8 || brw->is_haswell) {
335 return glarray->Format == GL_BGRA
336 ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
337 : BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
338 }
339 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
340 default: unreachable("not reached");
341 }
342 }
343 else {
344 /* See GL_ARB_vertex_type_2_10_10_10_rev.
345 * W/A: the hardware doesn't really support the formats we'd
346 * like to use here, so upload everything as UINT and fix
347 * it in the shader
348 */
349 if (glarray->Type == GL_INT_2_10_10_10_REV) {
350 assert(size == 4);
351 if (brw->gen >= 8 || brw->is_haswell) {
352 return glarray->Format == GL_BGRA
353 ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
354 : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
355 }
356 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
357 } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
358 assert(size == 4);
359 if (brw->gen >= 8 || brw->is_haswell) {
360 return glarray->Format == GL_BGRA
361 ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
362 : BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
363 }
364 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
365 }
366 assert(glarray->Format == GL_RGBA); /* sanity check */
367 switch (glarray->Type) {
368 case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
369 case GL_FLOAT: return float_types[size];
370 case GL_HALF_FLOAT:
371 if (brw->gen < 6 && size == 3)
372 return half_float_types[4];
373 else
374 return half_float_types[size];
375 case GL_INT: return int_types_scale[size];
376 case GL_SHORT: return short_types_scale[size];
377 case GL_BYTE: return byte_types_scale[size];
378 case GL_UNSIGNED_INT: return uint_types_scale[size];
379 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
380 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
381 case GL_FIXED:
382 if (brw->gen >= 8 || brw->is_haswell)
383 return fixed_point_types[size];
384
385 /* This produces GL_FIXED inputs as values between INT32_MIN and
386 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
387 */
388 return int_types_scale[size];
389 default: unreachable("not reached");
390 }
391 }
392 }
393
394 static void
395 copy_array_to_vbo_array(struct brw_context *brw,
396 struct brw_vertex_element *element,
397 int min, int max,
398 struct brw_vertex_buffer *buffer,
399 GLuint dst_stride)
400 {
401 const int src_stride = element->glarray->StrideB;
402
403 /* If the source stride is zero, we just want to upload the current
404 * attribute once and set the buffer's stride to 0. There's no need
405 * to replicate it out.
406 */
407 if (src_stride == 0) {
408 intel_upload_data(brw, element->glarray->Ptr,
409 element->glarray->_ElementSize,
410 element->glarray->_ElementSize,
411 &buffer->bo, &buffer->offset);
412
413 buffer->stride = 0;
414 buffer->size = element->glarray->_ElementSize;
415 return;
416 }
417
418 const unsigned char *src = element->glarray->Ptr + min * src_stride;
419 int count = max - min + 1;
420 GLuint size = count * dst_stride;
421 uint8_t *dst = intel_upload_space(brw, size, dst_stride,
422 &buffer->bo, &buffer->offset);
423
424 if (dst_stride == src_stride) {
425 memcpy(dst, src, size);
426 } else {
427 while (count--) {
428 memcpy(dst, src, dst_stride);
429 src += src_stride;
430 dst += dst_stride;
431 }
432 }
433 buffer->stride = dst_stride;
434 buffer->size = size;
435 }
436
437 void
438 brw_prepare_vertices(struct brw_context *brw)
439 {
440 struct gl_context *ctx = &brw->ctx;
441 /* BRW_NEW_VS_PROG_DATA */
442 const struct brw_vs_prog_data *vs_prog_data =
443 brw_vs_prog_data(brw->vs.base.prog_data);
444 GLbitfield64 vs_inputs = vs_prog_data->inputs_read;
445 const unsigned char *ptr = NULL;
446 GLuint interleaved = 0;
447 unsigned int min_index = brw->vb.min_index + brw->basevertex;
448 unsigned int max_index = brw->vb.max_index + brw->basevertex;
449 unsigned i;
450 int delta, j;
451
452 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
453 GLuint nr_uploads = 0;
454
455 /* _NEW_POLYGON
456 *
457 * On gen6+, edge flags don't end up in the VUE (either in or out of the
458 * VS). Instead, they're uploaded as the last vertex element, and the data
459 * is passed sideband through the fixed function units. So, we need to
460 * prepare the vertex buffer for it, but it's not present in inputs_read.
461 */
462 if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
463 ctx->Polygon.BackMode != GL_FILL)) {
464 vs_inputs |= VERT_BIT_EDGEFLAG;
465 }
466
467 if (0)
468 fprintf(stderr, "%s %d..%d\n", __func__, min_index, max_index);
469
470 /* Accumulate the list of enabled arrays. */
471 brw->vb.nr_enabled = 0;
472 while (vs_inputs) {
473 GLuint index = ffsll(vs_inputs) - 1;
474 struct brw_vertex_element *input = &brw->vb.inputs[index];
475
476 vs_inputs &= ~BITFIELD64_BIT(index);
477 brw->vb.enabled[brw->vb.nr_enabled++] = input;
478 }
479
480 if (brw->vb.nr_enabled == 0)
481 return;
482
483 if (brw->vb.nr_buffers)
484 return;
485
486 /* The range of data in a given buffer represented as [min, max) */
487 struct intel_buffer_object *enabled_buffer[VERT_ATTRIB_MAX];
488 uint32_t buffer_range_start[VERT_ATTRIB_MAX];
489 uint32_t buffer_range_end[VERT_ATTRIB_MAX];
490
491 for (i = j = 0; i < brw->vb.nr_enabled; i++) {
492 struct brw_vertex_element *input = brw->vb.enabled[i];
493 const struct gl_client_array *glarray = input->glarray;
494
495 if (_mesa_is_bufferobj(glarray->BufferObj)) {
496 struct intel_buffer_object *intel_buffer =
497 intel_buffer_object(glarray->BufferObj);
498
499 const uint32_t offset = (uintptr_t)glarray->Ptr;
500
501 /* Start with the worst case */
502 uint32_t start = 0;
503 uint32_t range = intel_buffer->Base.Size;
504 if (glarray->InstanceDivisor) {
505 if (brw->num_instances) {
506 start = offset + glarray->StrideB * brw->baseinstance;
507 range = (glarray->StrideB * ((brw->num_instances - 1) /
508 glarray->InstanceDivisor) +
509 glarray->_ElementSize);
510 }
511 } else {
512 if (brw->vb.index_bounds_valid) {
513 start = offset + min_index * glarray->StrideB;
514 range = (glarray->StrideB * (max_index - min_index) +
515 glarray->_ElementSize);
516 }
517 }
518
519 /* If we have a VB set to be uploaded for this buffer object
520 * already, reuse that VB state so that we emit fewer
521 * relocations.
522 */
523 unsigned k;
524 for (k = 0; k < i; k++) {
525 const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
526 if (glarray->BufferObj == other->BufferObj &&
527 glarray->StrideB == other->StrideB &&
528 glarray->InstanceDivisor == other->InstanceDivisor &&
529 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
530 {
531 input->buffer = brw->vb.enabled[k]->buffer;
532 input->offset = glarray->Ptr - other->Ptr;
533
534 buffer_range_start[input->buffer] =
535 MIN2(buffer_range_start[input->buffer], start);
536 buffer_range_end[input->buffer] =
537 MAX2(buffer_range_end[input->buffer], start + range);
538 break;
539 }
540 }
541 if (k == i) {
542 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
543
544 /* Named buffer object: Just reference its contents directly. */
545 buffer->offset = offset;
546 buffer->stride = glarray->StrideB;
547 buffer->step_rate = glarray->InstanceDivisor;
548 buffer->size = glarray->BufferObj->Size - offset;
549
550 enabled_buffer[j] = intel_buffer;
551 buffer_range_start[j] = start;
552 buffer_range_end[j] = start + range;
553
554 input->buffer = j++;
555 input->offset = 0;
556 }
557 } else {
558 /* Queue the buffer object up to be uploaded in the next pass,
559 * when we've decided if we're doing interleaved or not.
560 */
561 if (nr_uploads == 0) {
562 interleaved = glarray->StrideB;
563 ptr = glarray->Ptr;
564 }
565 else if (interleaved != glarray->StrideB ||
566 glarray->Ptr < ptr ||
567 (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
568 {
569 /* If our stride is different from the first attribute's stride,
570 * or if the first attribute's stride didn't cover our element,
571 * disable the interleaved upload optimization. The second case
572 * can most commonly occur in cases where there is a single vertex
573 * and, for example, the data is stored on the application's
574 * stack.
575 *
576 * NOTE: This will also disable the optimization in cases where
577 * the data is in a different order than the array indices.
578 * Something like:
579 *
580 * float data[...];
581 * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
582 * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
583 */
584 interleaved = 0;
585 }
586
587 upload[nr_uploads++] = input;
588 }
589 }
590
591 /* Now that we've set up all of the buffers, we walk through and reference
592 * each of them. We do this late so that we get the right size in each
593 * buffer and don't reference too little data.
594 */
595 for (i = 0; i < j; i++) {
596 struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
597 if (buffer->bo)
598 continue;
599
600 const uint32_t start = buffer_range_start[i];
601 const uint32_t range = buffer_range_end[i] - buffer_range_start[i];
602
603 buffer->bo = intel_bufferobj_buffer(brw, enabled_buffer[i], start, range);
604 drm_intel_bo_reference(buffer->bo);
605 }
606
607 /* If we need to upload all the arrays, then we can trim those arrays to
608 * only the used elements [min_index, max_index] so long as we adjust all
609 * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
610 */
611 brw->vb.start_vertex_bias = 0;
612 delta = min_index;
613 if (nr_uploads == brw->vb.nr_enabled) {
614 brw->vb.start_vertex_bias = -delta;
615 delta = 0;
616 }
617
618 /* Handle any arrays to be uploaded. */
619 if (nr_uploads > 1) {
620 if (interleaved) {
621 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
622 /* All uploads are interleaved, so upload the arrays together as
623 * interleaved. First, upload the contents and set up upload[0].
624 */
625 copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
626 buffer, interleaved);
627 buffer->offset -= delta * interleaved;
628 buffer->size += delta * interleaved;
629
630 for (i = 0; i < nr_uploads; i++) {
631 /* Then, just point upload[i] at upload[0]'s buffer. */
632 upload[i]->offset =
633 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
634 upload[i]->buffer = j;
635 }
636 j++;
637
638 nr_uploads = 0;
639 }
640 }
641 /* Upload non-interleaved arrays */
642 for (i = 0; i < nr_uploads; i++) {
643 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
644 if (upload[i]->glarray->InstanceDivisor == 0) {
645 copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
646 buffer, upload[i]->glarray->_ElementSize);
647 } else {
648 /* This is an instanced attribute, since its InstanceDivisor
649 * is not zero. Therefore, its data will be stepped after the
650 * instanced draw has been run InstanceDivisor times.
651 */
652 uint32_t instanced_attr_max_index =
653 (brw->num_instances - 1) / upload[i]->glarray->InstanceDivisor;
654 copy_array_to_vbo_array(brw, upload[i], 0, instanced_attr_max_index,
655 buffer, upload[i]->glarray->_ElementSize);
656 }
657 buffer->offset -= delta * buffer->stride;
658 buffer->size += delta * buffer->stride;
659 buffer->step_rate = upload[i]->glarray->InstanceDivisor;
660 upload[i]->buffer = j++;
661 upload[i]->offset = 0;
662 }
663
664 brw->vb.nr_buffers = j;
665 }
666
667 void
668 brw_prepare_shader_draw_parameters(struct brw_context *brw)
669 {
670 const struct brw_vs_prog_data *vs_prog_data =
671 brw_vs_prog_data(brw->vs.base.prog_data);
672
673 /* For non-indirect draws, upload gl_BaseVertex. */
674 if ((vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) &&
675 brw->draw.draw_params_bo == NULL) {
676 intel_upload_data(brw, &brw->draw.params, sizeof(brw->draw.params), 4,
677 &brw->draw.draw_params_bo,
678 &brw->draw.draw_params_offset);
679 }
680
681 if (vs_prog_data->uses_drawid) {
682 intel_upload_data(brw, &brw->draw.gl_drawid, sizeof(brw->draw.gl_drawid), 4,
683 &brw->draw.draw_id_bo,
684 &brw->draw.draw_id_offset);
685 }
686 }
687
688 /**
689 * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
690 */
691 uint32_t *
692 brw_emit_vertex_buffer_state(struct brw_context *brw,
693 unsigned buffer_nr,
694 drm_intel_bo *bo,
695 unsigned start_offset,
696 unsigned end_offset,
697 unsigned stride,
698 unsigned step_rate,
699 uint32_t *__map)
700 {
701 struct gl_context *ctx = &brw->ctx;
702 uint32_t dw0;
703
704 if (brw->gen >= 8) {
705 dw0 = buffer_nr << GEN6_VB0_INDEX_SHIFT;
706 } else if (brw->gen >= 6) {
707 dw0 = (buffer_nr << GEN6_VB0_INDEX_SHIFT) |
708 (step_rate ? GEN6_VB0_ACCESS_INSTANCEDATA
709 : GEN6_VB0_ACCESS_VERTEXDATA);
710 } else {
711 dw0 = (buffer_nr << BRW_VB0_INDEX_SHIFT) |
712 (step_rate ? BRW_VB0_ACCESS_INSTANCEDATA
713 : BRW_VB0_ACCESS_VERTEXDATA);
714 }
715
716 if (brw->gen >= 7)
717 dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
718
719 switch (brw->gen) {
720 case 7:
721 dw0 |= GEN7_MOCS_L3 << 16;
722 break;
723 case 8:
724 dw0 |= BDW_MOCS_WB << 16;
725 break;
726 case 9:
727 dw0 |= SKL_MOCS_WB << 16;
728 break;
729 }
730
731 WARN_ONCE(stride >= (brw->gen >= 5 ? 2048 : 2047),
732 "VBO stride %d too large, bad rendering may occur\n",
733 stride);
734 OUT_BATCH(dw0 | (stride << BRW_VB0_PITCH_SHIFT));
735 if (brw->gen >= 8) {
736 OUT_RELOC64(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
737 /* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
738 * Vertex Fetch (VF) Stage - State
739 *
740 * Instead of "VBState.StartingBufferAddress + VBState.MaxIndex x
741 * VBState.BufferPitch", the address of the byte immediately beyond the
742 * last valid byte of the buffer is determined by
743 * "VBState.StartingBufferAddress + VBState.BufferSize".
744 */
745 OUT_BATCH(end_offset - start_offset);
746 } else if (brw->gen >= 5) {
747 OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
748 /* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
749 * Vertex Fetch (VF) Stage - State
750 *
751 * Instead of "VBState.StartingBufferAddress + VBState.MaxIndex x
752 * VBState.BufferPitch", the address of the byte immediately beyond the
753 * last valid byte of the buffer is determined by
754 * "VBState.EndAddress + 1".
755 */
756 OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, end_offset - 1);
757 OUT_BATCH(step_rate);
758 } else {
759 OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
760 OUT_BATCH(0);
761 OUT_BATCH(step_rate);
762 }
763
764 return __map;
765 }
766
767 static void
768 brw_emit_vertices(struct brw_context *brw)
769 {
770 GLuint i;
771
772 brw_prepare_vertices(brw);
773 brw_prepare_shader_draw_parameters(brw);
774
775 brw_emit_query_begin(brw);
776
777 const struct brw_vs_prog_data *vs_prog_data =
778 brw_vs_prog_data(brw->vs.base.prog_data);
779
780 unsigned nr_elements = brw->vb.nr_enabled;
781 if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid ||
782 vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
783 ++nr_elements;
784 if (vs_prog_data->uses_drawid)
785 nr_elements++;
786
787 /* If the VS doesn't read any inputs (calculating vertex position from
788 * a state variable for some reason, for example), emit a single pad
789 * VERTEX_ELEMENT struct and bail.
790 *
791 * The stale VB state stays in place, but they don't do anything unless
792 * a VE loads from them.
793 */
794 if (nr_elements == 0) {
795 BEGIN_BATCH(3);
796 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
797 if (brw->gen >= 6) {
798 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
799 GEN6_VE0_VALID |
800 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
801 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
802 } else {
803 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
804 BRW_VE0_VALID |
805 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
806 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
807 }
808 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
809 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
810 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
811 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
812 ADVANCE_BATCH();
813 return;
814 }
815
816 /* Now emit VB and VEP state packets.
817 */
818
819 const bool uses_draw_params =
820 vs_prog_data->uses_basevertex ||
821 vs_prog_data->uses_baseinstance;
822 const unsigned nr_buffers = brw->vb.nr_buffers +
823 uses_draw_params + vs_prog_data->uses_drawid;
824
825 if (nr_buffers) {
826 if (brw->gen >= 6) {
827 assert(nr_buffers <= 33);
828 } else {
829 assert(nr_buffers <= 17);
830 }
831
832 BEGIN_BATCH(1 + 4 * nr_buffers);
833 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
834 for (i = 0; i < brw->vb.nr_buffers; i++) {
835 struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
836 /* Prior to Haswell and Bay Trail we have to use 4-component formats
837 * to fake 3-component ones. In particular, we do this for
838 * half-float and 8 and 16-bit integer formats. This means that the
839 * vertex element may poke over the end of the buffer by 2 bytes.
840 */
841 unsigned padding =
842 (brw->gen <= 7 && !brw->is_baytrail && !brw->is_haswell) * 2;
843 EMIT_VERTEX_BUFFER_STATE(brw, i, buffer->bo, buffer->offset,
844 buffer->offset + buffer->size + padding,
845 buffer->stride, buffer->step_rate);
846
847 }
848
849 if (uses_draw_params) {
850 EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers,
851 brw->draw.draw_params_bo,
852 brw->draw.draw_params_offset,
853 brw->draw.draw_params_bo->size,
854 0, /* stride */
855 0); /* step rate */
856 }
857
858 if (vs_prog_data->uses_drawid) {
859 EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers + 1,
860 brw->draw.draw_id_bo,
861 brw->draw.draw_id_offset,
862 brw->draw.draw_id_bo->size,
863 0, /* stride */
864 0); /* step rate */
865 }
866
867 ADVANCE_BATCH();
868 }
869
870 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
871 * for VertexID/InstanceID.
872 */
873 if (brw->gen >= 6) {
874 assert(nr_elements <= 34);
875 } else {
876 assert(nr_elements <= 18);
877 }
878
879 struct brw_vertex_element *gen6_edgeflag_input = NULL;
880
881 BEGIN_BATCH(1 + nr_elements * 2);
882 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
883 for (i = 0; i < brw->vb.nr_enabled; i++) {
884 struct brw_vertex_element *input = brw->vb.enabled[i];
885 uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
886 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
887 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
888 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
889 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
890
891 if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
892 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
893 * of in the VUE. We have to upload it sideband as the last vertex
894 * element according to the B-Spec.
895 */
896 if (brw->gen >= 6) {
897 gen6_edgeflag_input = input;
898 continue;
899 }
900 }
901
902 switch (input->glarray->Size) {
903 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
904 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
905 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
906 case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
907 : BRW_VE1_COMPONENT_STORE_1_FLT;
908 break;
909 }
910
911 if (brw->gen >= 6) {
912 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
913 GEN6_VE0_VALID |
914 (format << BRW_VE0_FORMAT_SHIFT) |
915 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
916 } else {
917 OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
918 BRW_VE0_VALID |
919 (format << BRW_VE0_FORMAT_SHIFT) |
920 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
921 }
922
923 if (brw->gen >= 5)
924 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
925 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
926 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
927 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
928 else
929 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
930 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
931 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
932 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
933 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
934 }
935
936 if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid ||
937 vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance) {
938 uint32_t dw0 = 0, dw1 = 0;
939 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_0;
940 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_0;
941 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_0;
942 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_0;
943
944 if (vs_prog_data->uses_basevertex)
945 comp0 = BRW_VE1_COMPONENT_STORE_SRC;
946
947 if (vs_prog_data->uses_baseinstance)
948 comp1 = BRW_VE1_COMPONENT_STORE_SRC;
949
950 if (vs_prog_data->uses_vertexid)
951 comp2 = BRW_VE1_COMPONENT_STORE_VID;
952
953 if (vs_prog_data->uses_instanceid)
954 comp3 = BRW_VE1_COMPONENT_STORE_IID;
955
956 dw1 = (comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
957 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
958 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
959 (comp3 << BRW_VE1_COMPONENT_3_SHIFT);
960
961 if (brw->gen >= 6) {
962 dw0 |= GEN6_VE0_VALID |
963 brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
964 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
965 } else {
966 dw0 |= BRW_VE0_VALID |
967 brw->vb.nr_buffers << BRW_VE0_INDEX_SHIFT |
968 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
969 dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
970 }
971
972 /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
973 * the format is ignored and the value is always int.
974 */
975
976 OUT_BATCH(dw0);
977 OUT_BATCH(dw1);
978 }
979
980 if (vs_prog_data->uses_drawid) {
981 uint32_t dw0 = 0, dw1 = 0;
982
983 dw1 = (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
984 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
985 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
986 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT);
987
988 if (brw->gen >= 6) {
989 dw0 |= GEN6_VE0_VALID |
990 ((brw->vb.nr_buffers + 1) << GEN6_VE0_INDEX_SHIFT) |
991 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
992 } else {
993 dw0 |= BRW_VE0_VALID |
994 ((brw->vb.nr_buffers + 1) << BRW_VE0_INDEX_SHIFT) |
995 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
996
997 dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
998 }
999
1000 OUT_BATCH(dw0);
1001 OUT_BATCH(dw1);
1002 }
1003
1004 if (brw->gen >= 6 && gen6_edgeflag_input) {
1005 uint32_t format =
1006 brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
1007
1008 OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
1009 GEN6_VE0_VALID |
1010 GEN6_VE0_EDGE_FLAG_ENABLE |
1011 (format << BRW_VE0_FORMAT_SHIFT) |
1012 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
1013 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
1014 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
1015 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
1016 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
1017 }
1018
1019 ADVANCE_BATCH();
1020 }
1021
1022 const struct brw_tracked_state brw_vertices = {
1023 .dirty = {
1024 .mesa = _NEW_POLYGON,
1025 .brw = BRW_NEW_BATCH |
1026 BRW_NEW_BLORP |
1027 BRW_NEW_VERTICES |
1028 BRW_NEW_VS_PROG_DATA,
1029 },
1030 .emit = brw_emit_vertices,
1031 };
1032
1033 static void
1034 brw_upload_indices(struct brw_context *brw)
1035 {
1036 struct gl_context *ctx = &brw->ctx;
1037 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
1038 GLuint ib_size;
1039 drm_intel_bo *old_bo = brw->ib.bo;
1040 struct gl_buffer_object *bufferobj;
1041 GLuint offset;
1042 GLuint ib_type_size;
1043
1044 if (index_buffer == NULL)
1045 return;
1046
1047 ib_type_size = _mesa_sizeof_type(index_buffer->type);
1048 ib_size = index_buffer->count ? ib_type_size * index_buffer->count :
1049 index_buffer->obj->Size;
1050 bufferobj = index_buffer->obj;
1051
1052 /* Turn into a proper VBO:
1053 */
1054 if (!_mesa_is_bufferobj(bufferobj)) {
1055 /* Get new bufferobj, offset:
1056 */
1057 intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
1058 &brw->ib.bo, &offset);
1059 brw->ib.size = brw->ib.bo->size;
1060 } else {
1061 offset = (GLuint) (unsigned long) index_buffer->ptr;
1062
1063 /* If the index buffer isn't aligned to its element size, we have to
1064 * rebase it into a temporary.
1065 */
1066 if ((ib_type_size - 1) & offset) {
1067 perf_debug("copying index buffer to a temporary to work around "
1068 "misaligned offset %d\n", offset);
1069
1070 GLubyte *map = ctx->Driver.MapBufferRange(ctx,
1071 offset,
1072 ib_size,
1073 GL_MAP_READ_BIT,
1074 bufferobj,
1075 MAP_INTERNAL);
1076
1077 intel_upload_data(brw, map, ib_size, ib_type_size,
1078 &brw->ib.bo, &offset);
1079 brw->ib.size = brw->ib.bo->size;
1080
1081 ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL);
1082 } else {
1083 drm_intel_bo *bo =
1084 intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
1085 offset, ib_size);
1086 if (bo != brw->ib.bo) {
1087 drm_intel_bo_unreference(brw->ib.bo);
1088 brw->ib.bo = bo;
1089 brw->ib.size = bufferobj->Size;
1090 drm_intel_bo_reference(bo);
1091 }
1092 }
1093 }
1094
1095 /* Use 3DPRIMITIVE's start_vertex_offset to avoid re-uploading
1096 * the index buffer state when we're just moving the start index
1097 * of our drawing.
1098 */
1099 brw->ib.start_vertex_offset = offset / ib_type_size;
1100
1101 if (brw->ib.bo != old_bo)
1102 brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1103
1104 if (index_buffer->type != brw->ib.type) {
1105 brw->ib.type = index_buffer->type;
1106 brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1107 }
1108 }
1109
1110 const struct brw_tracked_state brw_indices = {
1111 .dirty = {
1112 .mesa = 0,
1113 .brw = BRW_NEW_BLORP |
1114 BRW_NEW_INDICES,
1115 },
1116 .emit = brw_upload_indices,
1117 };
1118
1119 static void
1120 brw_emit_index_buffer(struct brw_context *brw)
1121 {
1122 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
1123 GLuint cut_index_setting;
1124
1125 if (index_buffer == NULL)
1126 return;
1127
1128 if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
1129 cut_index_setting = BRW_CUT_INDEX_ENABLE;
1130 } else {
1131 cut_index_setting = 0;
1132 }
1133
1134 BEGIN_BATCH(3);
1135 OUT_BATCH(CMD_INDEX_BUFFER << 16 |
1136 cut_index_setting |
1137 brw_get_index_type(index_buffer->type) |
1138 1);
1139 OUT_RELOC(brw->ib.bo,
1140 I915_GEM_DOMAIN_VERTEX, 0,
1141 0);
1142 OUT_RELOC(brw->ib.bo,
1143 I915_GEM_DOMAIN_VERTEX, 0,
1144 brw->ib.size - 1);
1145 ADVANCE_BATCH();
1146 }
1147
1148 const struct brw_tracked_state brw_index_buffer = {
1149 .dirty = {
1150 .mesa = 0,
1151 .brw = BRW_NEW_BATCH |
1152 BRW_NEW_BLORP |
1153 BRW_NEW_INDEX_BUFFER,
1154 },
1155 .emit = brw_emit_index_buffer,
1156 };