Merge commit 'origin/gallium-0.1'
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdlib.h>
29
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/state.h"
33 #include "main/api_validate.h"
34 #include "main/enums.h"
35
36 #include "brw_draw.h"
37 #include "brw_defines.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_fallback.h"
41
42 #include "intel_batchbuffer.h"
43 #include "intel_buffer_objects.h"
44 #include "intel_tex.h"
45
46 static GLuint double_types[5] = {
47 0,
48 BRW_SURFACEFORMAT_R64_FLOAT,
49 BRW_SURFACEFORMAT_R64G64_FLOAT,
50 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
51 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
52 };
53
54 static GLuint float_types[5] = {
55 0,
56 BRW_SURFACEFORMAT_R32_FLOAT,
57 BRW_SURFACEFORMAT_R32G32_FLOAT,
58 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
59 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
60 };
61
62 static GLuint uint_types_norm[5] = {
63 0,
64 BRW_SURFACEFORMAT_R32_UNORM,
65 BRW_SURFACEFORMAT_R32G32_UNORM,
66 BRW_SURFACEFORMAT_R32G32B32_UNORM,
67 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
68 };
69
70 static GLuint uint_types_scale[5] = {
71 0,
72 BRW_SURFACEFORMAT_R32_USCALED,
73 BRW_SURFACEFORMAT_R32G32_USCALED,
74 BRW_SURFACEFORMAT_R32G32B32_USCALED,
75 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
76 };
77
78 static GLuint int_types_norm[5] = {
79 0,
80 BRW_SURFACEFORMAT_R32_SNORM,
81 BRW_SURFACEFORMAT_R32G32_SNORM,
82 BRW_SURFACEFORMAT_R32G32B32_SNORM,
83 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
84 };
85
86 static GLuint int_types_scale[5] = {
87 0,
88 BRW_SURFACEFORMAT_R32_SSCALED,
89 BRW_SURFACEFORMAT_R32G32_SSCALED,
90 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
91 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
92 };
93
94 static GLuint ushort_types_norm[5] = {
95 0,
96 BRW_SURFACEFORMAT_R16_UNORM,
97 BRW_SURFACEFORMAT_R16G16_UNORM,
98 BRW_SURFACEFORMAT_R16G16B16_UNORM,
99 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
100 };
101
102 static GLuint ushort_types_scale[5] = {
103 0,
104 BRW_SURFACEFORMAT_R16_USCALED,
105 BRW_SURFACEFORMAT_R16G16_USCALED,
106 BRW_SURFACEFORMAT_R16G16B16_USCALED,
107 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
108 };
109
110 static GLuint short_types_norm[5] = {
111 0,
112 BRW_SURFACEFORMAT_R16_SNORM,
113 BRW_SURFACEFORMAT_R16G16_SNORM,
114 BRW_SURFACEFORMAT_R16G16B16_SNORM,
115 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
116 };
117
118 static GLuint short_types_scale[5] = {
119 0,
120 BRW_SURFACEFORMAT_R16_SSCALED,
121 BRW_SURFACEFORMAT_R16G16_SSCALED,
122 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
123 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
124 };
125
126 static GLuint ubyte_types_norm[5] = {
127 0,
128 BRW_SURFACEFORMAT_R8_UNORM,
129 BRW_SURFACEFORMAT_R8G8_UNORM,
130 BRW_SURFACEFORMAT_R8G8B8_UNORM,
131 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
132 };
133
134 static GLuint ubyte_types_scale[5] = {
135 0,
136 BRW_SURFACEFORMAT_R8_USCALED,
137 BRW_SURFACEFORMAT_R8G8_USCALED,
138 BRW_SURFACEFORMAT_R8G8B8_USCALED,
139 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
140 };
141
142 static GLuint byte_types_norm[5] = {
143 0,
144 BRW_SURFACEFORMAT_R8_SNORM,
145 BRW_SURFACEFORMAT_R8G8_SNORM,
146 BRW_SURFACEFORMAT_R8G8B8_SNORM,
147 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
148 };
149
150 static GLuint byte_types_scale[5] = {
151 0,
152 BRW_SURFACEFORMAT_R8_SSCALED,
153 BRW_SURFACEFORMAT_R8G8_SSCALED,
154 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
155 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
156 };
157
158
159 /**
160 * Given vertex array type/size/format/normalized info, return
161 * the appopriate hardware surface type.
162 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
163 */
164 static GLuint get_surface_type( GLenum type, GLuint size,
165 GLenum format, GLboolean normalized )
166 {
167 if (INTEL_DEBUG & DEBUG_VERTS)
168 _mesa_printf("type %s size %d normalized %d\n",
169 _mesa_lookup_enum_by_nr(type), size, normalized);
170
171 if (normalized) {
172 switch (type) {
173 case GL_DOUBLE: return double_types[size];
174 case GL_FLOAT: return float_types[size];
175 case GL_INT: return int_types_norm[size];
176 case GL_SHORT: return short_types_norm[size];
177 case GL_BYTE: return byte_types_norm[size];
178 case GL_UNSIGNED_INT: return uint_types_norm[size];
179 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
180 case GL_UNSIGNED_BYTE:
181 if (format == GL_BGRA) {
182 /* See GL_EXT_vertex_array_bgra */
183 assert(size == 4);
184 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
185 }
186 else {
187 return ubyte_types_norm[size];
188 }
189 default: assert(0); return 0;
190 }
191 }
192 else {
193 assert(format == GL_RGBA); /* sanity check */
194 switch (type) {
195 case GL_DOUBLE: return double_types[size];
196 case GL_FLOAT: return float_types[size];
197 case GL_INT: return int_types_scale[size];
198 case GL_SHORT: return short_types_scale[size];
199 case GL_BYTE: return byte_types_scale[size];
200 case GL_UNSIGNED_INT: return uint_types_scale[size];
201 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
202 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
203 default: assert(0); return 0;
204 }
205 }
206 }
207
208
209 static GLuint get_size( GLenum type )
210 {
211 switch (type) {
212 case GL_DOUBLE: return sizeof(GLdouble);
213 case GL_FLOAT: return sizeof(GLfloat);
214 case GL_INT: return sizeof(GLint);
215 case GL_SHORT: return sizeof(GLshort);
216 case GL_BYTE: return sizeof(GLbyte);
217 case GL_UNSIGNED_INT: return sizeof(GLuint);
218 case GL_UNSIGNED_SHORT: return sizeof(GLushort);
219 case GL_UNSIGNED_BYTE: return sizeof(GLubyte);
220 default: return 0;
221 }
222 }
223
224 static GLuint get_index_type(GLenum type)
225 {
226 switch (type) {
227 case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
228 case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
229 case GL_UNSIGNED_INT: return BRW_INDEX_DWORD;
230 default: assert(0); return 0;
231 }
232 }
233
234 static void wrap_buffers( struct brw_context *brw,
235 GLuint size )
236 {
237 if (size < BRW_UPLOAD_INIT_SIZE)
238 size = BRW_UPLOAD_INIT_SIZE;
239
240 brw->vb.upload.offset = 0;
241
242 if (brw->vb.upload.bo != NULL)
243 dri_bo_unreference(brw->vb.upload.bo);
244 brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
245 size, 1);
246
247 /* Set the internal VBO\ to no-backing-store. We only use them as a
248 * temporary within a brw_try_draw_prims while the lock is held.
249 */
250 /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH
251 FAKE TO PUSH THIS STUFF */
252 // if (!brw->intel.ttm)
253 // dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL);
254 }
255
256 static void get_space( struct brw_context *brw,
257 GLuint size,
258 dri_bo **bo_return,
259 GLuint *offset_return )
260 {
261 size = ALIGN(size, 64);
262
263 if (brw->vb.upload.bo == NULL ||
264 brw->vb.upload.offset + size > brw->vb.upload.bo->size) {
265 wrap_buffers(brw, size);
266 }
267
268 assert(*bo_return == NULL);
269 dri_bo_reference(brw->vb.upload.bo);
270 *bo_return = brw->vb.upload.bo;
271 *offset_return = brw->vb.upload.offset;
272 brw->vb.upload.offset += size;
273 }
274
275 static void
276 copy_array_to_vbo_array( struct brw_context *brw,
277 struct brw_vertex_element *element,
278 GLuint dst_stride)
279 {
280 GLuint size = element->count * dst_stride;
281
282 get_space(brw, size, &element->bo, &element->offset);
283
284 if (element->glarray->StrideB == 0) {
285 assert(element->count == 1);
286 element->stride = 0;
287 } else {
288 element->stride = dst_stride;
289 }
290
291 if (dst_stride == element->glarray->StrideB) {
292 dri_bo_subdata(element->bo,
293 element->offset,
294 size,
295 element->glarray->Ptr);
296 } else {
297 void *data;
298 char *dest;
299 const unsigned char *src = element->glarray->Ptr;
300 int i;
301
302 data = _mesa_malloc(dst_stride * element->count);
303 dest = data;
304 for (i = 0; i < element->count; i++) {
305 memcpy(dest, src, dst_stride);
306 src += element->glarray->StrideB;
307 dest += dst_stride;
308 }
309
310 dri_bo_subdata(element->bo,
311 element->offset,
312 size,
313 data);
314 _mesa_free(data);
315 }
316 }
317
318 static void brw_prepare_vertices(struct brw_context *brw)
319 {
320 GLcontext *ctx = &brw->intel.ctx;
321 struct intel_context *intel = intel_context(ctx);
322 GLuint tmp = brw->vs.prog_data->inputs_read;
323 GLuint i;
324 const unsigned char *ptr = NULL;
325 GLuint interleave = 0;
326 unsigned int min_index = brw->vb.min_index;
327 unsigned int max_index = brw->vb.max_index;
328
329 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
330 GLuint nr_enabled = 0;
331
332 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
333 GLuint nr_uploads = 0;
334
335 /* First build an array of pointers to ve's in vb.inputs_read
336 */
337 if (0)
338 _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
339
340 /* Accumulate the list of enabled arrays. */
341 while (tmp) {
342 GLuint i = _mesa_ffsll(tmp)-1;
343 struct brw_vertex_element *input = &brw->vb.inputs[i];
344
345 tmp &= ~(1<<i);
346 enabled[nr_enabled++] = input;
347 }
348
349 /* XXX: In the rare cases where this happens we fallback all
350 * the way to software rasterization, although a tnl fallback
351 * would be sufficient. I don't know of *any* real world
352 * cases with > 17 vertex attributes enabled, so it probably
353 * isn't an issue at this point.
354 */
355 if (nr_enabled >= BRW_VEP_MAX) {
356 intel->Fallback = 1;
357 return;
358 }
359
360 for (i = 0; i < nr_enabled; i++) {
361 struct brw_vertex_element *input = enabled[i];
362
363 input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
364 input->count = input->glarray->StrideB ? max_index + 1 - min_index : 1;
365
366 if (input->glarray->BufferObj->Name != 0) {
367 struct intel_buffer_object *intel_buffer =
368 intel_buffer_object(input->glarray->BufferObj);
369
370 /* Named buffer object: Just reference its contents directly. */
371 dri_bo_unreference(input->bo);
372 input->bo = intel_bufferobj_buffer(intel, intel_buffer,
373 INTEL_READ);
374 dri_bo_reference(input->bo);
375 input->offset = (unsigned long)input->glarray->Ptr;
376 input->stride = input->glarray->StrideB;
377 } else {
378 if (input->bo != NULL) {
379 /* Already-uploaded vertex data is present from a previous
380 * prepare_vertices, but we had to re-validate state due to
381 * check_aperture failing and a new batch being produced.
382 */
383 continue;
384 }
385
386 /* Queue the buffer object up to be uploaded in the next pass,
387 * when we've decided if we're doing interleaved or not.
388 */
389 if (i == 0) {
390 /* Position array not properly enabled:
391 */
392 if (input->glarray->StrideB == 0) {
393 intel->Fallback = 1;
394 return;
395 }
396
397 interleave = input->glarray->StrideB;
398 ptr = input->glarray->Ptr;
399 }
400 else if (interleave != input->glarray->StrideB ||
401 (const unsigned char *)input->glarray->Ptr - ptr < 0 ||
402 (const unsigned char *)input->glarray->Ptr - ptr > interleave)
403 {
404 interleave = 0;
405 }
406
407 upload[nr_uploads++] = input;
408
409 /* We rebase drawing to start at element zero only when
410 * varyings are not in vbos, which means we can end up
411 * uploading non-varying arrays (stride != 0) when min_index
412 * is zero. This doesn't matter as the amount to upload is
413 * the same for these arrays whether the draw call is rebased
414 * or not - we just have to upload the one element.
415 */
416 assert(min_index == 0 || input->glarray->StrideB == 0);
417 }
418 }
419
420 /* Handle any arrays to be uploaded. */
421 if (nr_uploads > 1 && interleave && interleave <= 256) {
422 /* All uploads are interleaved, so upload the arrays together as
423 * interleaved. First, upload the contents and set up upload[0].
424 */
425 copy_array_to_vbo_array(brw, upload[0], interleave);
426
427 for (i = 1; i < nr_uploads; i++) {
428 /* Then, just point upload[i] at upload[0]'s buffer. */
429 upload[i]->stride = interleave;
430 upload[i]->offset = upload[0]->offset +
431 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
432 upload[i]->bo = upload[0]->bo;
433 dri_bo_reference(upload[i]->bo);
434 }
435 }
436 else {
437 /* Upload non-interleaved arrays */
438 for (i = 0; i < nr_uploads; i++) {
439 copy_array_to_vbo_array(brw, upload[i], upload[i]->element_size);
440 }
441 }
442
443 brw_prepare_query_begin(brw);
444
445 for (i = 0; i < nr_enabled; i++) {
446 struct brw_vertex_element *input = enabled[i];
447
448 brw_add_validated_bo(brw, input->bo);
449 }
450 }
451
452 static void brw_emit_vertices(struct brw_context *brw)
453 {
454 GLcontext *ctx = &brw->intel.ctx;
455 struct intel_context *intel = intel_context(ctx);
456 GLuint tmp = brw->vs.prog_data->inputs_read;
457 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
458 GLuint i;
459 GLuint nr_enabled = 0;
460
461 /* Accumulate the list of enabled arrays. */
462 while (tmp) {
463 i = _mesa_ffsll(tmp)-1;
464 struct brw_vertex_element *input = &brw->vb.inputs[i];
465
466 tmp &= ~(1<<i);
467 enabled[nr_enabled++] = input;
468 }
469
470 brw_emit_query_begin(brw);
471
472 /* Now emit VB and VEP state packets.
473 *
474 * This still defines a hardware VB for each input, even if they
475 * are interleaved or from the same VBO. TBD if this makes a
476 * performance difference.
477 */
478 BEGIN_BATCH(1 + nr_enabled * 4, IGNORE_CLIPRECTS);
479 OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
480 ((1 + nr_enabled * 4) - 2));
481
482 for (i = 0; i < nr_enabled; i++) {
483 struct brw_vertex_element *input = enabled[i];
484
485 OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
486 BRW_VB0_ACCESS_VERTEXDATA |
487 (input->stride << BRW_VB0_PITCH_SHIFT));
488 OUT_RELOC(input->bo,
489 I915_GEM_DOMAIN_VERTEX, 0,
490 input->offset);
491 OUT_BATCH(brw->vb.max_index);
492 OUT_BATCH(0); /* Instance data step rate */
493 }
494 ADVANCE_BATCH();
495
496 BEGIN_BATCH(1 + nr_enabled * 2, IGNORE_CLIPRECTS);
497 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + nr_enabled * 2) - 2));
498 for (i = 0; i < nr_enabled; i++) {
499 struct brw_vertex_element *input = enabled[i];
500 uint32_t format = get_surface_type(input->glarray->Type,
501 input->glarray->Size,
502 input->glarray->Format,
503 input->glarray->Normalized);
504 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
505 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
506 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
507 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
508
509 switch (input->glarray->Size) {
510 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
511 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
512 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
513 case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT;
514 break;
515 }
516
517 OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
518 BRW_VE0_VALID |
519 (format << BRW_VE0_FORMAT_SHIFT) |
520 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
521 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
522 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
523 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
524 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
525 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
526 }
527 ADVANCE_BATCH();
528 }
529
530 const struct brw_tracked_state brw_vertices = {
531 .dirty = {
532 .mesa = 0,
533 .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
534 .cache = 0,
535 },
536 .prepare = brw_prepare_vertices,
537 .emit = brw_emit_vertices,
538 };
539
540 static void brw_prepare_indices(struct brw_context *brw)
541 {
542 GLcontext *ctx = &brw->intel.ctx;
543 struct intel_context *intel = &brw->intel;
544 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
545 GLuint ib_size;
546 dri_bo *bo = NULL;
547 struct gl_buffer_object *bufferobj;
548 GLuint offset;
549
550 if (index_buffer == NULL)
551 return;
552
553 ib_size = get_size(index_buffer->type) * index_buffer->count;
554 bufferobj = index_buffer->obj;;
555
556 /* Turn into a proper VBO:
557 */
558 if (!bufferobj->Name) {
559
560 /* Get new bufferobj, offset:
561 */
562 get_space(brw, ib_size, &bo, &offset);
563
564 /* Straight upload
565 */
566 dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
567 } else {
568 offset = (GLuint) (unsigned long) index_buffer->ptr;
569
570 /* If the index buffer isn't aligned to its element size, we have to
571 * rebase it into a temporary.
572 */
573 if ((get_size(index_buffer->type) - 1) & offset) {
574 GLubyte *map = ctx->Driver.MapBuffer(ctx,
575 GL_ELEMENT_ARRAY_BUFFER_ARB,
576 GL_DYNAMIC_DRAW_ARB,
577 bufferobj);
578 map += offset;
579
580 get_space(brw, ib_size, &bo, &offset);
581
582 dri_bo_subdata(bo, offset, ib_size, map);
583
584 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
585 } else {
586 bo = intel_bufferobj_buffer(intel, intel_buffer_object(bufferobj),
587 INTEL_READ);
588 dri_bo_reference(bo);
589 }
590 }
591
592 dri_bo_unreference(brw->ib.bo);
593 brw->ib.bo = bo;
594 brw->ib.offset = offset;
595
596 brw_add_validated_bo(brw, brw->ib.bo);
597 }
598
599 static void brw_emit_indices(struct brw_context *brw)
600 {
601 struct intel_context *intel = &brw->intel;
602 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
603 GLuint ib_size;
604
605 if (index_buffer == NULL)
606 return;
607
608 ib_size = get_size(index_buffer->type) * index_buffer->count;
609
610 /* Emit the indexbuffer packet:
611 */
612 {
613 struct brw_indexbuffer ib;
614
615 memset(&ib, 0, sizeof(ib));
616
617 ib.header.bits.opcode = CMD_INDEX_BUFFER;
618 ib.header.bits.length = sizeof(ib)/4 - 2;
619 ib.header.bits.index_format = get_index_type(index_buffer->type);
620 ib.header.bits.cut_index_enable = 0;
621
622
623 BEGIN_BATCH(4, IGNORE_CLIPRECTS);
624 OUT_BATCH( ib.header.dword );
625 OUT_RELOC(brw->ib.bo,
626 I915_GEM_DOMAIN_VERTEX, 0,
627 brw->ib.offset);
628 OUT_RELOC(brw->ib.bo,
629 I915_GEM_DOMAIN_VERTEX, 0,
630 brw->ib.offset + ib_size);
631 OUT_BATCH( 0 );
632 ADVANCE_BATCH();
633 }
634 }
635
636 const struct brw_tracked_state brw_indices = {
637 .dirty = {
638 .mesa = 0,
639 .brw = BRW_NEW_BATCH | BRW_NEW_INDICES,
640 .cache = 0,
641 },
642 .prepare = brw_prepare_indices,
643 .emit = brw_emit_indices,
644 };