i965: add support for ARB_half_float_vertex
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/glheader.h"
30 #include "main/bufferobj.h"
31 #include "main/context.h"
32 #include "main/state.h"
33 #include "main/api_validate.h"
34 #include "main/enums.h"
35
36 #include "brw_draw.h"
37 #include "brw_defines.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_fallback.h"
41
42 #include "intel_batchbuffer.h"
43 #include "intel_buffer_objects.h"
44 #include "intel_tex.h"
45
46 static GLuint double_types[5] = {
47 0,
48 BRW_SURFACEFORMAT_R64_FLOAT,
49 BRW_SURFACEFORMAT_R64G64_FLOAT,
50 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
51 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
52 };
53
54 static GLuint float_types[5] = {
55 0,
56 BRW_SURFACEFORMAT_R32_FLOAT,
57 BRW_SURFACEFORMAT_R32G32_FLOAT,
58 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
59 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
60 };
61
62 static GLuint half_float_types[5] = {
63 0,
64 BRW_SURFACEFORMAT_R16_FLOAT,
65 BRW_SURFACEFORMAT_R16G16_FLOAT,
66 0, /* can't seem to render this one */
67 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
68 };
69
70 static GLuint uint_types_norm[5] = {
71 0,
72 BRW_SURFACEFORMAT_R32_UNORM,
73 BRW_SURFACEFORMAT_R32G32_UNORM,
74 BRW_SURFACEFORMAT_R32G32B32_UNORM,
75 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
76 };
77
78 static GLuint uint_types_scale[5] = {
79 0,
80 BRW_SURFACEFORMAT_R32_USCALED,
81 BRW_SURFACEFORMAT_R32G32_USCALED,
82 BRW_SURFACEFORMAT_R32G32B32_USCALED,
83 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
84 };
85
86 static GLuint int_types_norm[5] = {
87 0,
88 BRW_SURFACEFORMAT_R32_SNORM,
89 BRW_SURFACEFORMAT_R32G32_SNORM,
90 BRW_SURFACEFORMAT_R32G32B32_SNORM,
91 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
92 };
93
94 static GLuint int_types_scale[5] = {
95 0,
96 BRW_SURFACEFORMAT_R32_SSCALED,
97 BRW_SURFACEFORMAT_R32G32_SSCALED,
98 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
99 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
100 };
101
102 static GLuint ushort_types_norm[5] = {
103 0,
104 BRW_SURFACEFORMAT_R16_UNORM,
105 BRW_SURFACEFORMAT_R16G16_UNORM,
106 BRW_SURFACEFORMAT_R16G16B16_UNORM,
107 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
108 };
109
110 static GLuint ushort_types_scale[5] = {
111 0,
112 BRW_SURFACEFORMAT_R16_USCALED,
113 BRW_SURFACEFORMAT_R16G16_USCALED,
114 BRW_SURFACEFORMAT_R16G16B16_USCALED,
115 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
116 };
117
118 static GLuint short_types_norm[5] = {
119 0,
120 BRW_SURFACEFORMAT_R16_SNORM,
121 BRW_SURFACEFORMAT_R16G16_SNORM,
122 BRW_SURFACEFORMAT_R16G16B16_SNORM,
123 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
124 };
125
126 static GLuint short_types_scale[5] = {
127 0,
128 BRW_SURFACEFORMAT_R16_SSCALED,
129 BRW_SURFACEFORMAT_R16G16_SSCALED,
130 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
131 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
132 };
133
134 static GLuint ubyte_types_norm[5] = {
135 0,
136 BRW_SURFACEFORMAT_R8_UNORM,
137 BRW_SURFACEFORMAT_R8G8_UNORM,
138 BRW_SURFACEFORMAT_R8G8B8_UNORM,
139 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
140 };
141
142 static GLuint ubyte_types_scale[5] = {
143 0,
144 BRW_SURFACEFORMAT_R8_USCALED,
145 BRW_SURFACEFORMAT_R8G8_USCALED,
146 BRW_SURFACEFORMAT_R8G8B8_USCALED,
147 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
148 };
149
150 static GLuint byte_types_norm[5] = {
151 0,
152 BRW_SURFACEFORMAT_R8_SNORM,
153 BRW_SURFACEFORMAT_R8G8_SNORM,
154 BRW_SURFACEFORMAT_R8G8B8_SNORM,
155 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
156 };
157
158 static GLuint byte_types_scale[5] = {
159 0,
160 BRW_SURFACEFORMAT_R8_SSCALED,
161 BRW_SURFACEFORMAT_R8G8_SSCALED,
162 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
163 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
164 };
165
166
167 /**
168 * Given vertex array type/size/format/normalized info, return
169 * the appopriate hardware surface type.
170 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
171 */
172 static GLuint get_surface_type( GLenum type, GLuint size,
173 GLenum format, GLboolean normalized )
174 {
175 if (INTEL_DEBUG & DEBUG_VERTS)
176 _mesa_printf("type %s size %d normalized %d\n",
177 _mesa_lookup_enum_by_nr(type), size, normalized);
178
179 if (normalized) {
180 switch (type) {
181 case GL_DOUBLE: return double_types[size];
182 case GL_FLOAT: return float_types[size];
183 case GL_HALF_FLOAT: return half_float_types[size];
184 case GL_INT: return int_types_norm[size];
185 case GL_SHORT: return short_types_norm[size];
186 case GL_BYTE: return byte_types_norm[size];
187 case GL_UNSIGNED_INT: return uint_types_norm[size];
188 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
189 case GL_UNSIGNED_BYTE:
190 if (format == GL_BGRA) {
191 /* See GL_EXT_vertex_array_bgra */
192 assert(size == 4);
193 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
194 }
195 else {
196 return ubyte_types_norm[size];
197 }
198 default: assert(0); return 0;
199 }
200 }
201 else {
202 assert(format == GL_RGBA); /* sanity check */
203 switch (type) {
204 case GL_DOUBLE: return double_types[size];
205 case GL_FLOAT: return float_types[size];
206 case GL_HALF_FLOAT: return half_float_types[size];
207 case GL_INT: return int_types_scale[size];
208 case GL_SHORT: return short_types_scale[size];
209 case GL_BYTE: return byte_types_scale[size];
210 case GL_UNSIGNED_INT: return uint_types_scale[size];
211 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
212 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
213 default: assert(0); return 0;
214 }
215 }
216 }
217
218
219 static GLuint get_size( GLenum type )
220 {
221 switch (type) {
222 case GL_DOUBLE: return sizeof(GLdouble);
223 case GL_FLOAT: return sizeof(GLfloat);
224 case GL_HALF_FLOAT: return sizeof(GLhalfARB);
225 case GL_INT: return sizeof(GLint);
226 case GL_SHORT: return sizeof(GLshort);
227 case GL_BYTE: return sizeof(GLbyte);
228 case GL_UNSIGNED_INT: return sizeof(GLuint);
229 case GL_UNSIGNED_SHORT: return sizeof(GLushort);
230 case GL_UNSIGNED_BYTE: return sizeof(GLubyte);
231 default: return 0;
232 }
233 }
234
235 static GLuint get_index_type(GLenum type)
236 {
237 switch (type) {
238 case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
239 case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
240 case GL_UNSIGNED_INT: return BRW_INDEX_DWORD;
241 default: assert(0); return 0;
242 }
243 }
244
245 static void wrap_buffers( struct brw_context *brw,
246 GLuint size )
247 {
248 if (size < BRW_UPLOAD_INIT_SIZE)
249 size = BRW_UPLOAD_INIT_SIZE;
250
251 brw->vb.upload.offset = 0;
252
253 if (brw->vb.upload.bo != NULL)
254 dri_bo_unreference(brw->vb.upload.bo);
255 brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
256 size, 1);
257 }
258
259 static void get_space( struct brw_context *brw,
260 GLuint size,
261 dri_bo **bo_return,
262 GLuint *offset_return )
263 {
264 size = ALIGN(size, 64);
265
266 if (brw->vb.upload.bo == NULL ||
267 brw->vb.upload.offset + size > brw->vb.upload.bo->size) {
268 wrap_buffers(brw, size);
269 }
270
271 assert(*bo_return == NULL);
272 dri_bo_reference(brw->vb.upload.bo);
273 *bo_return = brw->vb.upload.bo;
274 *offset_return = brw->vb.upload.offset;
275 brw->vb.upload.offset += size;
276 }
277
278 static void
279 copy_array_to_vbo_array( struct brw_context *brw,
280 struct brw_vertex_element *element,
281 GLuint dst_stride)
282 {
283 struct intel_context *intel = &brw->intel;
284 GLuint size = element->count * dst_stride;
285
286 get_space(brw, size, &element->bo, &element->offset);
287
288 if (element->glarray->StrideB == 0) {
289 assert(element->count == 1);
290 element->stride = 0;
291 } else {
292 element->stride = dst_stride;
293 }
294
295 if (dst_stride == element->glarray->StrideB) {
296 if (intel->intelScreen->kernel_exec_fencing) {
297 drm_intel_gem_bo_map_gtt(element->bo);
298 memcpy((char *)element->bo->virtual + element->offset,
299 element->glarray->Ptr, size);
300 drm_intel_gem_bo_unmap_gtt(element->bo);
301 } else {
302 dri_bo_subdata(element->bo,
303 element->offset,
304 size,
305 element->glarray->Ptr);
306 }
307 } else {
308 char *dest;
309 const unsigned char *src = element->glarray->Ptr;
310 int i;
311
312 if (intel->intelScreen->kernel_exec_fencing) {
313 drm_intel_gem_bo_map_gtt(element->bo);
314 dest = element->bo->virtual;
315 dest += element->offset;
316
317 for (i = 0; i < element->count; i++) {
318 memcpy(dest, src, dst_stride);
319 src += element->glarray->StrideB;
320 dest += dst_stride;
321 }
322
323 drm_intel_gem_bo_unmap_gtt(element->bo);
324 } else {
325 void *data;
326
327 data = _mesa_malloc(dst_stride * element->count);
328 dest = data;
329 for (i = 0; i < element->count; i++) {
330 memcpy(dest, src, dst_stride);
331 src += element->glarray->StrideB;
332 dest += dst_stride;
333 }
334
335 dri_bo_subdata(element->bo,
336 element->offset,
337 size,
338 data);
339
340 _mesa_free(data);
341 }
342 }
343 }
344
345 static void brw_prepare_vertices(struct brw_context *brw)
346 {
347 GLcontext *ctx = &brw->intel.ctx;
348 struct intel_context *intel = intel_context(ctx);
349 GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
350 GLuint i;
351 const unsigned char *ptr = NULL;
352 GLuint interleave = 0;
353 unsigned int min_index = brw->vb.min_index;
354 unsigned int max_index = brw->vb.max_index;
355
356 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
357 GLuint nr_uploads = 0;
358
359 /* First build an array of pointers to ve's in vb.inputs_read
360 */
361 if (0)
362 _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
363
364 /* Accumulate the list of enabled arrays. */
365 brw->vb.nr_enabled = 0;
366 while (vs_inputs) {
367 GLuint i = _mesa_ffsll(vs_inputs) - 1;
368 struct brw_vertex_element *input = &brw->vb.inputs[i];
369
370 vs_inputs &= ~(1 << i);
371 brw->vb.enabled[brw->vb.nr_enabled++] = input;
372 }
373
374 /* XXX: In the rare cases where this happens we fallback all
375 * the way to software rasterization, although a tnl fallback
376 * would be sufficient. I don't know of *any* real world
377 * cases with > 17 vertex attributes enabled, so it probably
378 * isn't an issue at this point.
379 */
380 if (brw->vb.nr_enabled >= BRW_VEP_MAX) {
381 intel->Fallback = GL_TRUE; /* boolean, not bitfield */
382 return;
383 }
384
385 for (i = 0; i < brw->vb.nr_enabled; i++) {
386 struct brw_vertex_element *input = brw->vb.enabled[i];
387
388 input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
389
390 if (_mesa_is_bufferobj(input->glarray->BufferObj)) {
391 struct intel_buffer_object *intel_buffer =
392 intel_buffer_object(input->glarray->BufferObj);
393
394 /* Named buffer object: Just reference its contents directly. */
395 dri_bo_unreference(input->bo);
396 input->bo = intel_bufferobj_buffer(intel, intel_buffer,
397 INTEL_READ);
398 dri_bo_reference(input->bo);
399 input->offset = (unsigned long)input->glarray->Ptr;
400 input->stride = input->glarray->StrideB;
401 input->count = input->glarray->_MaxElement;
402
403 /* This is a common place to reach if the user mistakenly supplies
404 * a pointer in place of a VBO offset. If we just let it go through,
405 * we may end up dereferencing a pointer beyond the bounds of the
406 * GTT. We would hope that the VBO's max_index would save us, but
407 * Mesa appears to hand us min/max values not clipped to the
408 * array object's _MaxElement, and _MaxElement frequently appears
409 * to be wrong anyway.
410 *
411 * The VBO spec allows application termination in this case, and it's
412 * probably a service to the poor programmer to do so rather than
413 * trying to just not render.
414 */
415 assert(input->offset < input->bo->size);
416 } else {
417 input->count = input->glarray->StrideB ? max_index + 1 - min_index : 1;
418 if (input->bo != NULL) {
419 /* Already-uploaded vertex data is present from a previous
420 * prepare_vertices, but we had to re-validate state due to
421 * check_aperture failing and a new batch being produced.
422 */
423 continue;
424 }
425
426 /* Queue the buffer object up to be uploaded in the next pass,
427 * when we've decided if we're doing interleaved or not.
428 */
429 if (input->attrib == VERT_ATTRIB_POS) {
430 /* Position array not properly enabled:
431 */
432 if (input->glarray->StrideB == 0) {
433 intel->Fallback = GL_TRUE; /* boolean, not bitfield */
434 return;
435 }
436
437 interleave = input->glarray->StrideB;
438 ptr = input->glarray->Ptr;
439 }
440 else if (interleave != input->glarray->StrideB ||
441 (const unsigned char *)input->glarray->Ptr - ptr < 0 ||
442 (const unsigned char *)input->glarray->Ptr - ptr > interleave)
443 {
444 interleave = 0;
445 }
446
447 upload[nr_uploads++] = input;
448
449 /* We rebase drawing to start at element zero only when
450 * varyings are not in vbos, which means we can end up
451 * uploading non-varying arrays (stride != 0) when min_index
452 * is zero. This doesn't matter as the amount to upload is
453 * the same for these arrays whether the draw call is rebased
454 * or not - we just have to upload the one element.
455 */
456 assert(min_index == 0 || input->glarray->StrideB == 0);
457 }
458 }
459
460 /* Handle any arrays to be uploaded. */
461 if (nr_uploads > 1 && interleave && interleave <= 256) {
462 /* All uploads are interleaved, so upload the arrays together as
463 * interleaved. First, upload the contents and set up upload[0].
464 */
465 copy_array_to_vbo_array(brw, upload[0], interleave);
466
467 for (i = 1; i < nr_uploads; i++) {
468 /* Then, just point upload[i] at upload[0]'s buffer. */
469 upload[i]->stride = interleave;
470 upload[i]->offset = upload[0]->offset +
471 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
472 upload[i]->bo = upload[0]->bo;
473 dri_bo_reference(upload[i]->bo);
474 }
475 }
476 else {
477 /* Upload non-interleaved arrays */
478 for (i = 0; i < nr_uploads; i++) {
479 copy_array_to_vbo_array(brw, upload[i], upload[i]->element_size);
480 }
481 }
482
483 brw_prepare_query_begin(brw);
484
485 for (i = 0; i < brw->vb.nr_enabled; i++) {
486 struct brw_vertex_element *input = brw->vb.enabled[i];
487
488 brw_add_validated_bo(brw, input->bo);
489 }
490 }
491
492 static void brw_emit_vertices(struct brw_context *brw)
493 {
494 GLcontext *ctx = &brw->intel.ctx;
495 struct intel_context *intel = intel_context(ctx);
496 GLuint i;
497
498 brw_emit_query_begin(brw);
499
500 /* If the VS doesn't read any inputs (calculating vertex position from
501 * a state variable for some reason, for example), emit a single pad
502 * VERTEX_ELEMENT struct and bail.
503 *
504 * The stale VB state stays in place, but they don't do anything unless
505 * a VE loads from them.
506 */
507 if (brw->vb.nr_enabled == 0) {
508 BEGIN_BATCH(3);
509 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
510 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
511 BRW_VE0_VALID |
512 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
513 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
514 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
515 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
516 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
517 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
518 ADVANCE_BATCH();
519 return;
520 }
521
522 /* Now emit VB and VEP state packets.
523 *
524 * This still defines a hardware VB for each input, even if they
525 * are interleaved or from the same VBO. TBD if this makes a
526 * performance difference.
527 */
528 BEGIN_BATCH(1 + brw->vb.nr_enabled * 4);
529 OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
530 ((1 + brw->vb.nr_enabled * 4) - 2));
531
532 for (i = 0; i < brw->vb.nr_enabled; i++) {
533 struct brw_vertex_element *input = brw->vb.enabled[i];
534
535 OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
536 BRW_VB0_ACCESS_VERTEXDATA |
537 (input->stride << BRW_VB0_PITCH_SHIFT));
538 OUT_RELOC(input->bo,
539 I915_GEM_DOMAIN_VERTEX, 0,
540 input->offset);
541 if (intel->is_ironlake) {
542 OUT_RELOC(input->bo,
543 I915_GEM_DOMAIN_VERTEX, 0,
544 input->bo->size - 1);
545 } else
546 OUT_BATCH(input->stride ? input->count : 0);
547 OUT_BATCH(0); /* Instance data step rate */
548 }
549 ADVANCE_BATCH();
550
551 BEGIN_BATCH(1 + brw->vb.nr_enabled * 2);
552 OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2));
553 for (i = 0; i < brw->vb.nr_enabled; i++) {
554 struct brw_vertex_element *input = brw->vb.enabled[i];
555 uint32_t format = get_surface_type(input->glarray->Type,
556 input->glarray->Size,
557 input->glarray->Format,
558 input->glarray->Normalized);
559 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
560 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
561 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
562 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
563
564 switch (input->glarray->Size) {
565 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
566 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
567 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
568 case 3: comp3 = BRW_VE1_COMPONENT_STORE_1_FLT;
569 break;
570 }
571
572 OUT_BATCH((i << BRW_VE0_INDEX_SHIFT) |
573 BRW_VE0_VALID |
574 (format << BRW_VE0_FORMAT_SHIFT) |
575 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
576
577 if (intel->is_ironlake)
578 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
579 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
580 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
581 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
582 else
583 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
584 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
585 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
586 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
587 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
588 }
589 ADVANCE_BATCH();
590 }
591
592 const struct brw_tracked_state brw_vertices = {
593 .dirty = {
594 .mesa = 0,
595 .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
596 .cache = 0,
597 },
598 .prepare = brw_prepare_vertices,
599 .emit = brw_emit_vertices,
600 };
601
602 static void brw_prepare_indices(struct brw_context *brw)
603 {
604 GLcontext *ctx = &brw->intel.ctx;
605 struct intel_context *intel = &brw->intel;
606 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
607 GLuint ib_size;
608 dri_bo *bo = NULL;
609 struct gl_buffer_object *bufferobj;
610 GLuint offset;
611 GLuint ib_type_size;
612
613 if (index_buffer == NULL)
614 return;
615
616 ib_type_size = get_size(index_buffer->type);
617 ib_size = ib_type_size * index_buffer->count;
618 bufferobj = index_buffer->obj;;
619
620 /* Turn into a proper VBO:
621 */
622 if (!_mesa_is_bufferobj(bufferobj)) {
623 brw->ib.start_vertex_offset = 0;
624
625 /* Get new bufferobj, offset:
626 */
627 get_space(brw, ib_size, &bo, &offset);
628
629 /* Straight upload
630 */
631 if (intel->intelScreen->kernel_exec_fencing) {
632 drm_intel_gem_bo_map_gtt(bo);
633 memcpy((char *)bo->virtual + offset, index_buffer->ptr, ib_size);
634 drm_intel_gem_bo_unmap_gtt(bo);
635 } else {
636 dri_bo_subdata(bo, offset, ib_size, index_buffer->ptr);
637 }
638 } else {
639 offset = (GLuint) (unsigned long) index_buffer->ptr;
640 brw->ib.start_vertex_offset = 0;
641
642 /* If the index buffer isn't aligned to its element size, we have to
643 * rebase it into a temporary.
644 */
645 if ((get_size(index_buffer->type) - 1) & offset) {
646 GLubyte *map = ctx->Driver.MapBuffer(ctx,
647 GL_ELEMENT_ARRAY_BUFFER_ARB,
648 GL_DYNAMIC_DRAW_ARB,
649 bufferobj);
650 map += offset;
651
652 get_space(brw, ib_size, &bo, &offset);
653
654 dri_bo_subdata(bo, offset, ib_size, map);
655
656 ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
657 } else {
658 bo = intel_bufferobj_buffer(intel, intel_buffer_object(bufferobj),
659 INTEL_READ);
660 dri_bo_reference(bo);
661
662 /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
663 * the index buffer state when we're just moving the start index
664 * of our drawing.
665 */
666 brw->ib.start_vertex_offset = offset / ib_type_size;
667 offset = 0;
668 ib_size = bo->size;
669 }
670 }
671
672 if (brw->ib.bo != bo ||
673 brw->ib.offset != offset ||
674 brw->ib.size != ib_size)
675 {
676 drm_intel_bo_unreference(brw->ib.bo);
677 brw->ib.bo = bo;
678 brw->ib.offset = offset;
679 brw->ib.size = ib_size;
680
681 brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
682 } else {
683 drm_intel_bo_unreference(bo);
684 }
685
686 brw_add_validated_bo(brw, brw->ib.bo);
687 }
688
689 const struct brw_tracked_state brw_indices = {
690 .dirty = {
691 .mesa = 0,
692 .brw = BRW_NEW_INDICES,
693 .cache = 0,
694 },
695 .prepare = brw_prepare_indices,
696 };
697
698 static void brw_emit_index_buffer(struct brw_context *brw)
699 {
700 struct intel_context *intel = &brw->intel;
701 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
702
703 if (index_buffer == NULL)
704 return;
705
706 /* Emit the indexbuffer packet:
707 */
708 {
709 struct brw_indexbuffer ib;
710
711 memset(&ib, 0, sizeof(ib));
712
713 ib.header.bits.opcode = CMD_INDEX_BUFFER;
714 ib.header.bits.length = sizeof(ib)/4 - 2;
715 ib.header.bits.index_format = get_index_type(index_buffer->type);
716 ib.header.bits.cut_index_enable = 0;
717
718 BEGIN_BATCH(4);
719 OUT_BATCH( ib.header.dword );
720 OUT_RELOC(brw->ib.bo,
721 I915_GEM_DOMAIN_VERTEX, 0,
722 brw->ib.offset);
723 OUT_RELOC(brw->ib.bo,
724 I915_GEM_DOMAIN_VERTEX, 0,
725 brw->ib.offset + brw->ib.size - 1);
726 OUT_BATCH( 0 );
727 ADVANCE_BATCH();
728 }
729 }
730
731 const struct brw_tracked_state brw_index_buffer = {
732 .dirty = {
733 .mesa = 0,
734 .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
735 .cache = 0,
736 },
737 .emit = brw_emit_index_buffer,
738 };