src/mesa/drivers/dri/i965/brw_draw_upload.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/bufferobj.h"
  27 #include "main/context.h"
  28 #include "main/enums.h"
  29 #include "main/macros.h"
  30 #include "main/glformats.h"
  31
  32 #include "brw_draw.h"
  33 #include "brw_defines.h"
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffer_objects.h"
  39
  40 static const GLuint double_types_float[5] = {
  41    0,
  42    BRW_SURFACEFORMAT_R64_FLOAT,
  43    BRW_SURFACEFORMAT_R64G64_FLOAT,
  44    BRW_SURFACEFORMAT_R64G64B64_FLOAT,
  45    BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
  46 };
  47
  48 static const GLuint double_types_passthru[5] = {
  49    0,
  50    BRW_SURFACEFORMAT_R64_PASSTHRU,
  51    BRW_SURFACEFORMAT_R64G64_PASSTHRU,
  52    BRW_SURFACEFORMAT_R64G64B64_PASSTHRU,
  53    BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU
  54 };
  55
  56 static const GLuint float_types[5] = {
  57    0,
  58    BRW_SURFACEFORMAT_R32_FLOAT,
  59    BRW_SURFACEFORMAT_R32G32_FLOAT,
  60    BRW_SURFACEFORMAT_R32G32B32_FLOAT,
  61    BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
  62 };
  63
  64 static const GLuint half_float_types[5] = {
  65    0,
  66    BRW_SURFACEFORMAT_R16_FLOAT,
  67    BRW_SURFACEFORMAT_R16G16_FLOAT,
  68    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
  69    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
  70 };
  71
  72 static const GLuint fixed_point_types[5] = {
  73    0,
  74    BRW_SURFACEFORMAT_R32_SFIXED,
  75    BRW_SURFACEFORMAT_R32G32_SFIXED,
  76    BRW_SURFACEFORMAT_R32G32B32_SFIXED,
  77    BRW_SURFACEFORMAT_R32G32B32A32_SFIXED,
  78 };
  79
  80 static const GLuint uint_types_direct[5] = {
  81    0,
  82    BRW_SURFACEFORMAT_R32_UINT,
  83    BRW_SURFACEFORMAT_R32G32_UINT,
  84    BRW_SURFACEFORMAT_R32G32B32_UINT,
  85    BRW_SURFACEFORMAT_R32G32B32A32_UINT
  86 };
  87
  88 static const GLuint uint_types_norm[5] = {
  89    0,
  90    BRW_SURFACEFORMAT_R32_UNORM,
  91    BRW_SURFACEFORMAT_R32G32_UNORM,
  92    BRW_SURFACEFORMAT_R32G32B32_UNORM,
  93    BRW_SURFACEFORMAT_R32G32B32A32_UNORM
  94 };
  95
  96 static const GLuint uint_types_scale[5] = {
  97    0,
  98    BRW_SURFACEFORMAT_R32_USCALED,
  99    BRW_SURFACEFORMAT_R32G32_USCALED,
 100    BRW_SURFACEFORMAT_R32G32B32_USCALED,
 101    BRW_SURFACEFORMAT_R32G32B32A32_USCALED
 102 };
 103
 104 static const GLuint int_types_direct[5] = {
 105    0,
 106    BRW_SURFACEFORMAT_R32_SINT,
 107    BRW_SURFACEFORMAT_R32G32_SINT,
 108    BRW_SURFACEFORMAT_R32G32B32_SINT,
 109    BRW_SURFACEFORMAT_R32G32B32A32_SINT
 110 };
 111
 112 static const GLuint int_types_norm[5] = {
 113    0,
 114    BRW_SURFACEFORMAT_R32_SNORM,
 115    BRW_SURFACEFORMAT_R32G32_SNORM,
 116    BRW_SURFACEFORMAT_R32G32B32_SNORM,
 117    BRW_SURFACEFORMAT_R32G32B32A32_SNORM
 118 };
 119
 120 static const GLuint int_types_scale[5] = {
 121    0,
 122    BRW_SURFACEFORMAT_R32_SSCALED,
 123    BRW_SURFACEFORMAT_R32G32_SSCALED,
 124    BRW_SURFACEFORMAT_R32G32B32_SSCALED,
 125    BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
 126 };
 127
 128 static const GLuint ushort_types_direct[5] = {
 129    0,
 130    BRW_SURFACEFORMAT_R16_UINT,
 131    BRW_SURFACEFORMAT_R16G16_UINT,
 132    BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 133    BRW_SURFACEFORMAT_R16G16B16A16_UINT
 134 };
 135
 136 static const GLuint ushort_types_norm[5] = {
 137    0,
 138    BRW_SURFACEFORMAT_R16_UNORM,
 139    BRW_SURFACEFORMAT_R16G16_UNORM,
 140    BRW_SURFACEFORMAT_R16G16B16_UNORM,
 141    BRW_SURFACEFORMAT_R16G16B16A16_UNORM
 142 };
 143
 144 static const GLuint ushort_types_scale[5] = {
 145    0,
 146    BRW_SURFACEFORMAT_R16_USCALED,
 147    BRW_SURFACEFORMAT_R16G16_USCALED,
 148    BRW_SURFACEFORMAT_R16G16B16_USCALED,
 149    BRW_SURFACEFORMAT_R16G16B16A16_USCALED
 150 };
 151
 152 static const GLuint short_types_direct[5] = {
 153    0,
 154    BRW_SURFACEFORMAT_R16_SINT,
 155    BRW_SURFACEFORMAT_R16G16_SINT,
 156    BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 157    BRW_SURFACEFORMAT_R16G16B16A16_SINT
 158 };
 159
 160 static const GLuint short_types_norm[5] = {
 161    0,
 162    BRW_SURFACEFORMAT_R16_SNORM,
 163    BRW_SURFACEFORMAT_R16G16_SNORM,
 164    BRW_SURFACEFORMAT_R16G16B16_SNORM,
 165    BRW_SURFACEFORMAT_R16G16B16A16_SNORM
 166 };
 167
 168 static const GLuint short_types_scale[5] = {
 169    0,
 170    BRW_SURFACEFORMAT_R16_SSCALED,
 171    BRW_SURFACEFORMAT_R16G16_SSCALED,
 172    BRW_SURFACEFORMAT_R16G16B16_SSCALED,
 173    BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
 174 };
 175
 176 static const GLuint ubyte_types_direct[5] = {
 177    0,
 178    BRW_SURFACEFORMAT_R8_UINT,
 179    BRW_SURFACEFORMAT_R8G8_UINT,
 180    BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 181    BRW_SURFACEFORMAT_R8G8B8A8_UINT
 182 };
 183
 184 static const GLuint ubyte_types_norm[5] = {
 185    0,
 186    BRW_SURFACEFORMAT_R8_UNORM,
 187    BRW_SURFACEFORMAT_R8G8_UNORM,
 188    BRW_SURFACEFORMAT_R8G8B8_UNORM,
 189    BRW_SURFACEFORMAT_R8G8B8A8_UNORM
 190 };
 191
 192 static const GLuint ubyte_types_scale[5] = {
 193    0,
 194    BRW_SURFACEFORMAT_R8_USCALED,
 195    BRW_SURFACEFORMAT_R8G8_USCALED,
 196    BRW_SURFACEFORMAT_R8G8B8_USCALED,
 197    BRW_SURFACEFORMAT_R8G8B8A8_USCALED
 198 };
 199
 200 static const GLuint byte_types_direct[5] = {
 201    0,
 202    BRW_SURFACEFORMAT_R8_SINT,
 203    BRW_SURFACEFORMAT_R8G8_SINT,
 204    BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 205    BRW_SURFACEFORMAT_R8G8B8A8_SINT
 206 };
 207
 208 static const GLuint byte_types_norm[5] = {
 209    0,
 210    BRW_SURFACEFORMAT_R8_SNORM,
 211    BRW_SURFACEFORMAT_R8G8_SNORM,
 212    BRW_SURFACEFORMAT_R8G8B8_SNORM,
 213    BRW_SURFACEFORMAT_R8G8B8A8_SNORM
 214 };
 215
 216 static const GLuint byte_types_scale[5] = {
 217    0,
 218    BRW_SURFACEFORMAT_R8_SSCALED,
 219    BRW_SURFACEFORMAT_R8G8_SSCALED,
 220    BRW_SURFACEFORMAT_R8G8B8_SSCALED,
 221    BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
 222 };
 223
 224 static GLuint
 225 double_types(struct brw_context *brw,
 226              int size,
 227              GLboolean doubles)
 228 {
 229    /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
 230     * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
 231     * 64-bit components are stored in the URB without any conversion."
 232     * Also included on BDW PRM, Volume 7, page 470, table "Source Element
 233     * Formats Supported in VF Unit"
 234     * Previous PRMs don't include those references.
 235     */
 236    return (brw->gen >= 8 && doubles
 237            ? double_types_passthru[size]
 238            : double_types_float[size]);
 239 }
 240
 241 /**
 242  * Given vertex array type/size/format/normalized info, return
 243  * the appopriate hardware surface type.
 244  * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
 245  */
 246 unsigned
 247 brw_get_vertex_surface_type(struct brw_context *brw,
 248                             const struct gl_client_array *glarray)
 249 {
 250    int size = glarray->Size;
 251
 252    if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
 253       fprintf(stderr, "type %s size %d normalized %d\n",
 254               _mesa_enum_to_string(glarray->Type),
 255               glarray->Size, glarray->Normalized);
 256
 257    if (glarray->Integer) {
 258       assert(glarray->Format == GL_RGBA); /* sanity check */
 259       switch (glarray->Type) {
 260       case GL_INT: return int_types_direct[size];
 261       case GL_SHORT: return short_types_direct[size];
 262       case GL_BYTE: return byte_types_direct[size];
 263       case GL_UNSIGNED_INT: return uint_types_direct[size];
 264       case GL_UNSIGNED_SHORT: return ushort_types_direct[size];
 265       case GL_UNSIGNED_BYTE: return ubyte_types_direct[size];
 266       default: unreachable("not reached");
 267       }
 268    } else if (glarray->Type == GL_UNSIGNED_INT_10F_11F_11F_REV) {
 269       return BRW_SURFACEFORMAT_R11G11B10_FLOAT;
 270    } else if (glarray->Normalized) {
 271       switch (glarray->Type) {
 272       case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
 273       case GL_FLOAT: return float_types[size];
 274       case GL_HALF_FLOAT: return half_float_types[size];
 275       case GL_INT: return int_types_norm[size];
 276       case GL_SHORT: return short_types_norm[size];
 277       case GL_BYTE: return byte_types_norm[size];
 278       case GL_UNSIGNED_INT: return uint_types_norm[size];
 279       case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
 280       case GL_UNSIGNED_BYTE:
 281          if (glarray->Format == GL_BGRA) {
 282             /* See GL_EXT_vertex_array_bgra */
 283             assert(size == 4);
 284             return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 285          }
 286          else {
 287             return ubyte_types_norm[size];
 288          }
 289       case GL_FIXED:
 290          if (brw->gen >= 8 || brw->is_haswell)
 291             return fixed_point_types[size];
 292
 293          /* This produces GL_FIXED inputs as values between INT32_MIN and
 294           * INT32_MAX, which will be scaled down by 1/65536 by the VS.
 295           */
 296          return int_types_scale[size];
 297       /* See GL_ARB_vertex_type_2_10_10_10_rev.
 298        * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
 299        * like to use here, so upload everything as UINT and fix
 300        * it in the shader
 301        */
 302       case GL_INT_2_10_10_10_REV:
 303          assert(size == 4);
 304          if (brw->gen >= 8 || brw->is_haswell) {
 305             return glarray->Format == GL_BGRA
 306                ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
 307                : BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
 308          }
 309          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 310       case GL_UNSIGNED_INT_2_10_10_10_REV:
 311          assert(size == 4);
 312          if (brw->gen >= 8 || brw->is_haswell) {
 313             return glarray->Format == GL_BGRA
 314                ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
 315                : BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
 316          }
 317          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 318       default: unreachable("not reached");
 319       }
 320    }
 321    else {
 322       /* See GL_ARB_vertex_type_2_10_10_10_rev.
 323        * W/A: the hardware doesn't really support the formats we'd
 324        * like to use here, so upload everything as UINT and fix
 325        * it in the shader
 326        */
 327       if (glarray->Type == GL_INT_2_10_10_10_REV) {
 328          assert(size == 4);
 329          if (brw->gen >= 8 || brw->is_haswell) {
 330             return glarray->Format == GL_BGRA
 331                ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
 332                : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
 333          }
 334          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 335       } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
 336          assert(size == 4);
 337          if (brw->gen >= 8 || brw->is_haswell) {
 338             return glarray->Format == GL_BGRA
 339                ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
 340                : BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
 341          }
 342          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 343       }
 344       assert(glarray->Format == GL_RGBA); /* sanity check */
 345       switch (glarray->Type) {
 346       case GL_DOUBLE: return double_types(brw, size, glarray->Doubles);
 347       case GL_FLOAT: return float_types[size];
 348       case GL_HALF_FLOAT: return half_float_types[size];
 349       case GL_INT: return int_types_scale[size];
 350       case GL_SHORT: return short_types_scale[size];
 351       case GL_BYTE: return byte_types_scale[size];
 352       case GL_UNSIGNED_INT: return uint_types_scale[size];
 353       case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
 354       case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
 355       case GL_FIXED:
 356          if (brw->gen >= 8 || brw->is_haswell)
 357             return fixed_point_types[size];
 358
 359          /* This produces GL_FIXED inputs as values between INT32_MIN and
 360           * INT32_MAX, which will be scaled down by 1/65536 by the VS.
 361           */
 362          return int_types_scale[size];
 363       default: unreachable("not reached");
 364       }
 365    }
 366 }
 367
 368 static void
 369 copy_array_to_vbo_array(struct brw_context *brw,
 370                         struct brw_vertex_element *element,
 371                         int min, int max,
 372                         struct brw_vertex_buffer *buffer,
 373                         GLuint dst_stride)
 374 {
 375    const int src_stride = element->glarray->StrideB;
 376
 377    /* If the source stride is zero, we just want to upload the current
 378     * attribute once and set the buffer's stride to 0.  There's no need
 379     * to replicate it out.
 380     */
 381    if (src_stride == 0) {
 382       intel_upload_data(brw, element->glarray->Ptr,
 383                         element->glarray->_ElementSize,
 384                         element->glarray->_ElementSize,
 385                         &buffer->bo, &buffer->offset);
 386
 387       buffer->stride = 0;
 388       return;
 389    }
 390
 391    const unsigned char *src = element->glarray->Ptr + min * src_stride;
 392    int count = max - min + 1;
 393    GLuint size = count * dst_stride;
 394    uint8_t *dst = intel_upload_space(brw, size, dst_stride,
 395                                      &buffer->bo, &buffer->offset);
 396
 397    if (dst_stride == src_stride) {
 398       memcpy(dst, src, size);
 399    } else {
 400       while (count--) {
 401          memcpy(dst, src, dst_stride);
 402          src += src_stride;
 403          dst += dst_stride;
 404       }
 405    }
 406    buffer->stride = dst_stride;
 407 }
 408
 409 void
 410 brw_prepare_vertices(struct brw_context *brw)
 411 {
 412    struct gl_context *ctx = &brw->ctx;
 413    /* BRW_NEW_VS_PROG_DATA */
 414    GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
 415    const unsigned char *ptr = NULL;
 416    GLuint interleaved = 0;
 417    unsigned int min_index = brw->vb.min_index + brw->basevertex;
 418    unsigned int max_index = brw->vb.max_index + brw->basevertex;
 419    unsigned i;
 420    int delta, j;
 421
 422    struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
 423    GLuint nr_uploads = 0;
 424
 425    /* _NEW_POLYGON
 426     *
 427     * On gen6+, edge flags don't end up in the VUE (either in or out of the
 428     * VS).  Instead, they're uploaded as the last vertex element, and the data
 429     * is passed sideband through the fixed function units.  So, we need to
 430     * prepare the vertex buffer for it, but it's not present in inputs_read.
 431     */
 432    if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
 433                            ctx->Polygon.BackMode != GL_FILL)) {
 434       vs_inputs |= VERT_BIT_EDGEFLAG;
 435    }
 436
 437    if (0)
 438       fprintf(stderr, "%s %d..%d\n", __func__, min_index, max_index);
 439
 440    /* Accumulate the list of enabled arrays. */
 441    brw->vb.nr_enabled = 0;
 442    while (vs_inputs) {
 443       GLuint index = ffsll(vs_inputs) - 1;
 444       struct brw_vertex_element *input = &brw->vb.inputs[index];
 445
 446       vs_inputs &= ~BITFIELD64_BIT(index);
 447       brw->vb.enabled[brw->vb.nr_enabled++] = input;
 448    }
 449
 450    if (brw->vb.nr_enabled == 0)
 451       return;
 452
 453    if (brw->vb.nr_buffers)
 454       return;
 455
 456    for (i = j = 0; i < brw->vb.nr_enabled; i++) {
 457       struct brw_vertex_element *input = brw->vb.enabled[i];
 458       const struct gl_client_array *glarray = input->glarray;
 459
 460       if (_mesa_is_bufferobj(glarray->BufferObj)) {
 461          struct intel_buffer_object *intel_buffer =
 462             intel_buffer_object(glarray->BufferObj);
 463          unsigned k;
 464
 465          /* If we have a VB set to be uploaded for this buffer object
 466           * already, reuse that VB state so that we emit fewer
 467           * relocations.
 468           */
 469          for (k = 0; k < i; k++) {
 470             const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
 471             if (glarray->BufferObj == other->BufferObj &&
 472                 glarray->StrideB == other->StrideB &&
 473                 glarray->InstanceDivisor == other->InstanceDivisor &&
 474                 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
 475             {
 476                input->buffer = brw->vb.enabled[k]->buffer;
 477                input->offset = glarray->Ptr - other->Ptr;
 478                break;
 479             }
 480          }
 481          if (k == i) {
 482             struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 483
 484             /* Named buffer object: Just reference its contents directly. */
 485             buffer->offset = (uintptr_t)glarray->Ptr;
 486             buffer->stride = glarray->StrideB;
 487             buffer->step_rate = glarray->InstanceDivisor;
 488
 489             uint32_t offset, size;
 490             if (glarray->InstanceDivisor) {
 491                offset = buffer->offset;
 492                size = (buffer->stride * ((brw->num_instances /
 493                                           glarray->InstanceDivisor) - 1) +
 494                        glarray->_ElementSize);
 495             } else {
 496                if (!brw->vb.index_bounds_valid) {
 497                   offset = 0;
 498                   size = intel_buffer->Base.Size;
 499                } else {
 500                   offset = buffer->offset + min_index * buffer->stride;
 501                   size = (buffer->stride * (max_index - min_index) +
 502                           glarray->_ElementSize);
 503                }
 504             }
 505             buffer->bo = intel_bufferobj_buffer(brw, intel_buffer,
 506                                                 offset, size);
 507             drm_intel_bo_reference(buffer->bo);
 508
 509             input->buffer = j++;
 510             input->offset = 0;
 511          }
 512
 513          /* This is a common place to reach if the user mistakenly supplies
 514           * a pointer in place of a VBO offset.  If we just let it go through,
 515           * we may end up dereferencing a pointer beyond the bounds of the
 516           * GTT.
 517           *
 518           * The VBO spec allows application termination in this case, and it's
 519           * probably a service to the poor programmer to do so rather than
 520           * trying to just not render.
 521           */
 522          assert(input->offset < brw->vb.buffers[input->buffer].bo->size);
 523       } else {
 524          /* Queue the buffer object up to be uploaded in the next pass,
 525           * when we've decided if we're doing interleaved or not.
 526           */
 527          if (nr_uploads == 0) {
 528             interleaved = glarray->StrideB;
 529             ptr = glarray->Ptr;
 530          }
 531          else if (interleaved != glarray->StrideB ||
 532                   glarray->Ptr < ptr ||
 533                   (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
 534          {
 535             /* If our stride is different from the first attribute's stride,
 536              * or if the first attribute's stride didn't cover our element,
 537              * disable the interleaved upload optimization.  The second case
 538              * can most commonly occur in cases where there is a single vertex
 539              * and, for example, the data is stored on the application's
 540              * stack.
 541              *
 542              * NOTE: This will also disable the optimization in cases where
 543              * the data is in a different order than the array indices.
 544              * Something like:
 545              *
 546              *     float data[...];
 547              *     glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
 548              *     glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
 549              */
 550             interleaved = 0;
 551          }
 552
 553          upload[nr_uploads++] = input;
 554       }
 555    }
 556
 557    /* If we need to upload all the arrays, then we can trim those arrays to
 558     * only the used elements [min_index, max_index] so long as we adjust all
 559     * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
 560     */
 561    brw->vb.start_vertex_bias = 0;
 562    delta = min_index;
 563    if (nr_uploads == brw->vb.nr_enabled) {
 564       brw->vb.start_vertex_bias = -delta;
 565       delta = 0;
 566    }
 567
 568    /* Handle any arrays to be uploaded. */
 569    if (nr_uploads > 1) {
 570       if (interleaved) {
 571          struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 572          /* All uploads are interleaved, so upload the arrays together as
 573           * interleaved.  First, upload the contents and set up upload[0].
 574           */
 575          copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
 576                                  buffer, interleaved);
 577          buffer->offset -= delta * interleaved;
 578
 579          for (i = 0; i < nr_uploads; i++) {
 580             /* Then, just point upload[i] at upload[0]'s buffer. */
 581             upload[i]->offset =
 582                ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
 583             upload[i]->buffer = j;
 584          }
 585          j++;
 586
 587          nr_uploads = 0;
 588       }
 589    }
 590    /* Upload non-interleaved arrays */
 591    for (i = 0; i < nr_uploads; i++) {
 592       struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 593       if (upload[i]->glarray->InstanceDivisor == 0) {
 594          copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
 595                                  buffer, upload[i]->glarray->_ElementSize);
 596       } else {
 597          /* This is an instanced attribute, since its InstanceDivisor
 598           * is not zero. Therefore, its data will be stepped after the
 599           * instanced draw has been run InstanceDivisor times.
 600           */
 601          uint32_t instanced_attr_max_index =
 602             (brw->num_instances - 1) / upload[i]->glarray->InstanceDivisor;
 603          copy_array_to_vbo_array(brw, upload[i], 0, instanced_attr_max_index,
 604                                  buffer, upload[i]->glarray->_ElementSize);
 605       }
 606       buffer->offset -= delta * buffer->stride;
 607       buffer->step_rate = upload[i]->glarray->InstanceDivisor;
 608       upload[i]->buffer = j++;
 609       upload[i]->offset = 0;
 610    }
 611
 612    brw->vb.nr_buffers = j;
 613 }
 614
 615 void
 616 brw_prepare_shader_draw_parameters(struct brw_context *brw)
 617 {
 618    /* For non-indirect draws, upload gl_BaseVertex. */
 619    if ((brw->vs.prog_data->uses_basevertex ||
 620         brw->vs.prog_data->uses_baseinstance) &&
 621        brw->draw.draw_params_bo == NULL) {
 622       intel_upload_data(brw, &brw->draw.params, sizeof(brw->draw.params), 4,
 623                         &brw->draw.draw_params_bo,
 624                         &brw->draw.draw_params_offset);
 625    }
 626
 627    if (brw->vs.prog_data->uses_drawid) {
 628       intel_upload_data(brw, &brw->draw.gl_drawid, sizeof(brw->draw.gl_drawid), 4,
 629                         &brw->draw.draw_id_bo,
 630                         &brw->draw.draw_id_offset);
 631    }
 632 }
 633
 634 /**
 635  * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
 636  */
 637 static uint32_t *
 638 emit_vertex_buffer_state(struct brw_context *brw,
 639                          unsigned buffer_nr,
 640                          drm_intel_bo *bo,
 641                          unsigned bo_ending_address,
 642                          unsigned bo_offset,
 643                          unsigned stride,
 644                          unsigned step_rate,
 645                          uint32_t *__map)
 646 {
 647    struct gl_context *ctx = &brw->ctx;
 648    uint32_t dw0;
 649
 650    if (brw->gen >= 6) {
 651       dw0 = (buffer_nr << GEN6_VB0_INDEX_SHIFT) |
 652             (step_rate ? GEN6_VB0_ACCESS_INSTANCEDATA
 653                        : GEN6_VB0_ACCESS_VERTEXDATA);
 654    } else {
 655       dw0 = (buffer_nr << BRW_VB0_INDEX_SHIFT) |
 656             (step_rate ? BRW_VB0_ACCESS_INSTANCEDATA
 657                        : BRW_VB0_ACCESS_VERTEXDATA);
 658    }
 659
 660    if (brw->gen >= 7)
 661       dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 662
 663    if (brw->gen == 7)
 664       dw0 |= GEN7_MOCS_L3 << 16;
 665
 666    WARN_ONCE(stride >= (brw->gen >= 5 ? 2048 : 2047),
 667              "VBO stride %d too large, bad rendering may occur\n",
 668              stride);
 669    OUT_BATCH(dw0 | (stride << BRW_VB0_PITCH_SHIFT));
 670    OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_offset);
 671    if (brw->gen >= 5) {
 672       OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, bo_ending_address);
 673    } else {
 674       OUT_BATCH(0);
 675    }
 676    OUT_BATCH(step_rate);
 677
 678    return __map;
 679 }
 680 #define EMIT_VERTEX_BUFFER_STATE(...) __map = emit_vertex_buffer_state(__VA_ARGS__, __map)
 681
 682 static void
 683 brw_emit_vertices(struct brw_context *brw)
 684 {
 685    GLuint i;
 686
 687    brw_prepare_vertices(brw);
 688    brw_prepare_shader_draw_parameters(brw);
 689
 690    brw_emit_query_begin(brw);
 691
 692    unsigned nr_elements = brw->vb.nr_enabled;
 693    if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid ||
 694        brw->vs.prog_data->uses_basevertex || brw->vs.prog_data->uses_baseinstance)
 695       ++nr_elements;
 696    if (brw->vs.prog_data->uses_drawid)
 697       nr_elements++;
 698
 699    /* If the VS doesn't read any inputs (calculating vertex position from
 700     * a state variable for some reason, for example), emit a single pad
 701     * VERTEX_ELEMENT struct and bail.
 702     *
 703     * The stale VB state stays in place, but they don't do anything unless
 704     * a VE loads from them.
 705     */
 706    if (nr_elements == 0) {
 707       BEGIN_BATCH(3);
 708       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
 709       if (brw->gen >= 6) {
 710          OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
 711                    GEN6_VE0_VALID |
 712                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 713                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 714       } else {
 715          OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
 716                    BRW_VE0_VALID |
 717                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 718                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 719       }
 720       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 721                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 722                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 723                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
 724       ADVANCE_BATCH();
 725       return;
 726    }
 727
 728    /* Now emit VB and VEP state packets.
 729     */
 730
 731    const bool uses_draw_params =
 732       brw->vs.prog_data->uses_basevertex ||
 733       brw->vs.prog_data->uses_baseinstance;
 734    const unsigned nr_buffers = brw->vb.nr_buffers +
 735       uses_draw_params + brw->vs.prog_data->uses_drawid;
 736
 737    if (nr_buffers) {
 738       if (brw->gen >= 6) {
 739          assert(nr_buffers <= 33);
 740       } else {
 741          assert(nr_buffers <= 17);
 742       }
 743
 744       BEGIN_BATCH(1 + 4 * nr_buffers);
 745       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4 * nr_buffers - 1));
 746       for (i = 0; i < brw->vb.nr_buffers; i++) {
 747          struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
 748          EMIT_VERTEX_BUFFER_STATE(brw, i, buffer->bo, buffer->bo->size - 1,
 749                                   buffer->offset, buffer->stride,
 750                                   buffer->step_rate);
 751
 752       }
 753
 754       if (uses_draw_params) {
 755          EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers,
 756                                   brw->draw.draw_params_bo,
 757                                   brw->draw.draw_params_bo->size - 1,
 758                                   brw->draw.draw_params_offset,
 759                                   0,  /* stride */
 760                                   0); /* step rate */
 761       }
 762
 763       if (brw->vs.prog_data->uses_drawid) {
 764          EMIT_VERTEX_BUFFER_STATE(brw, brw->vb.nr_buffers + 1,
 765                                   brw->draw.draw_id_bo,
 766                                   brw->draw.draw_id_bo->size - 1,
 767                                   brw->draw.draw_id_offset,
 768                                   0,  /* stride */
 769                                   0); /* step rate */
 770       }
 771
 772       ADVANCE_BATCH();
 773    }
 774
 775    /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
 776     * for VertexID/InstanceID.
 777     */
 778    if (brw->gen >= 6) {
 779       assert(nr_elements <= 34);
 780    } else {
 781       assert(nr_elements <= 18);
 782    }
 783
 784    struct brw_vertex_element *gen6_edgeflag_input = NULL;
 785
 786    BEGIN_BATCH(1 + nr_elements * 2);
 787    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
 788    for (i = 0; i < brw->vb.nr_enabled; i++) {
 789       struct brw_vertex_element *input = brw->vb.enabled[i];
 790       uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
 791       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 792       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 793       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
 794       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
 795
 796       if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
 797          /* Gen6+ passes edgeflag as sideband along with the vertex, instead
 798           * of in the VUE.  We have to upload it sideband as the last vertex
 799           * element according to the B-Spec.
 800           */
 801          if (brw->gen >= 6) {
 802             gen6_edgeflag_input = input;
 803             continue;
 804          }
 805       }
 806
 807       switch (input->glarray->Size) {
 808       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
 809       case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
 810       case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
 811       case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
 812                                               : BRW_VE1_COMPONENT_STORE_1_FLT;
 813          break;
 814       }
 815
 816       if (brw->gen >= 6) {
 817          OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
 818                    GEN6_VE0_VALID |
 819                    (format << BRW_VE0_FORMAT_SHIFT) |
 820                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 821       } else {
 822          OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
 823                    BRW_VE0_VALID |
 824                    (format << BRW_VE0_FORMAT_SHIFT) |
 825                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 826       }
 827
 828       if (brw->gen >= 5)
 829           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 830                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 831                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 832                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
 833       else
 834           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 835                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 836                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 837                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
 838                     ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
 839    }
 840
 841    if (brw->vs.prog_data->uses_vertexid || brw->vs.prog_data->uses_instanceid ||
 842        brw->vs.prog_data->uses_basevertex || brw->vs.prog_data->uses_baseinstance) {
 843       uint32_t dw0 = 0, dw1 = 0;
 844       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_0;
 845       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_0;
 846       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_0;
 847       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_0;
 848
 849       if (brw->vs.prog_data->uses_basevertex)
 850          comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 851
 852       if (brw->vs.prog_data->uses_baseinstance)
 853          comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 854
 855       if (brw->vs.prog_data->uses_vertexid)
 856          comp2 = BRW_VE1_COMPONENT_STORE_VID;
 857
 858       if (brw->vs.prog_data->uses_instanceid)
 859          comp3 = BRW_VE1_COMPONENT_STORE_IID;
 860
 861       dw1 = (comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 862             (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 863             (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 864             (comp3 << BRW_VE1_COMPONENT_3_SHIFT);
 865
 866       if (brw->gen >= 6) {
 867          dw0 |= GEN6_VE0_VALID |
 868                 brw->vb.nr_buffers << GEN6_VE0_INDEX_SHIFT |
 869                 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
 870       } else {
 871          dw0 |= BRW_VE0_VALID |
 872                 brw->vb.nr_buffers << BRW_VE0_INDEX_SHIFT |
 873                 BRW_SURFACEFORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
 874          dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
 875       }
 876
 877       /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
 878        * the format is ignored and the value is always int.
 879        */
 880
 881       OUT_BATCH(dw0);
 882       OUT_BATCH(dw1);
 883    }
 884
 885    if (brw->vs.prog_data->uses_drawid) {
 886       uint32_t dw0 = 0, dw1 = 0;
 887
 888       dw1 = (BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 889             (BRW_VE1_COMPONENT_STORE_0   << BRW_VE1_COMPONENT_1_SHIFT) |
 890             (BRW_VE1_COMPONENT_STORE_0   << BRW_VE1_COMPONENT_2_SHIFT) |
 891             (BRW_VE1_COMPONENT_STORE_0   << BRW_VE1_COMPONENT_3_SHIFT);
 892
 893       if (brw->gen >= 6) {
 894          dw0 |= GEN6_VE0_VALID |
 895                 ((brw->vb.nr_buffers + 1) << GEN6_VE0_INDEX_SHIFT) |
 896                 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
 897       } else {
 898          dw0 |= BRW_VE0_VALID |
 899                 ((brw->vb.nr_buffers + 1) << BRW_VE0_INDEX_SHIFT) |
 900                 (BRW_SURFACEFORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
 901
 902          dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
 903       }
 904
 905       OUT_BATCH(dw0);
 906       OUT_BATCH(dw1);
 907    }
 908
 909    if (brw->gen >= 6 && gen6_edgeflag_input) {
 910       uint32_t format =
 911          brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
 912
 913       OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
 914                 GEN6_VE0_VALID |
 915                 GEN6_VE0_EDGE_FLAG_ENABLE |
 916                 (format << BRW_VE0_FORMAT_SHIFT) |
 917                 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 918       OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 919                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 920                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 921                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 922    }
 923
 924    ADVANCE_BATCH();
 925 }
 926
 927 const struct brw_tracked_state brw_vertices = {
 928    .dirty = {
 929       .mesa = _NEW_POLYGON,
 930       .brw = BRW_NEW_BATCH |
 931              BRW_NEW_BLORP |
 932              BRW_NEW_VERTICES |
 933              BRW_NEW_VS_PROG_DATA,
 934    },
 935    .emit = brw_emit_vertices,
 936 };
 937
 938 static void
 939 brw_upload_indices(struct brw_context *brw)
 940 {
 941    struct gl_context *ctx = &brw->ctx;
 942    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 943    GLuint ib_size;
 944    drm_intel_bo *old_bo = brw->ib.bo;
 945    struct gl_buffer_object *bufferobj;
 946    GLuint offset;
 947    GLuint ib_type_size;
 948
 949    if (index_buffer == NULL)
 950       return;
 951
 952    ib_type_size = _mesa_sizeof_type(index_buffer->type);
 953    ib_size = ib_type_size * index_buffer->count;
 954    bufferobj = index_buffer->obj;
 955
 956    /* Turn into a proper VBO:
 957     */
 958    if (!_mesa_is_bufferobj(bufferobj)) {
 959       /* Get new bufferobj, offset:
 960        */
 961       intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
 962                         &brw->ib.bo, &offset);
 963    } else {
 964       offset = (GLuint) (unsigned long) index_buffer->ptr;
 965
 966       /* If the index buffer isn't aligned to its element size, we have to
 967        * rebase it into a temporary.
 968        */
 969       if ((ib_type_size - 1) & offset) {
 970          perf_debug("copying index buffer to a temporary to work around "
 971                     "misaligned offset %d\n", offset);
 972
 973          GLubyte *map = ctx->Driver.MapBufferRange(ctx,
 974                                                    offset,
 975                                                    ib_size,
 976                                                    GL_MAP_READ_BIT,
 977                                                    bufferobj,
 978                                                    MAP_INTERNAL);
 979
 980          intel_upload_data(brw, map, ib_size, ib_type_size,
 981                            &brw->ib.bo, &offset);
 982
 983          ctx->Driver.UnmapBuffer(ctx, bufferobj, MAP_INTERNAL);
 984       } else {
 985          drm_intel_bo *bo =
 986             intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
 987                                    offset, ib_size);
 988          if (bo != brw->ib.bo) {
 989             drm_intel_bo_unreference(brw->ib.bo);
 990             brw->ib.bo = bo;
 991             drm_intel_bo_reference(bo);
 992          }
 993       }
 994    }
 995
 996    /* Use 3DPRIMITIVE's start_vertex_offset to avoid re-uploading
 997     * the index buffer state when we're just moving the start index
 998     * of our drawing.
 999     */
1000    brw->ib.start_vertex_offset = offset / ib_type_size;
1001
1002    if (brw->ib.bo != old_bo)
1003       brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1004
1005    if (index_buffer->type != brw->ib.type) {
1006       brw->ib.type = index_buffer->type;
1007       brw->ctx.NewDriverState |= BRW_NEW_INDEX_BUFFER;
1008    }
1009 }
1010
1011 const struct brw_tracked_state brw_indices = {
1012    .dirty = {
1013       .mesa = 0,
1014       .brw = BRW_NEW_BLORP |
1015              BRW_NEW_INDICES,
1016    },
1017    .emit = brw_upload_indices,
1018 };
1019
1020 static void
1021 brw_emit_index_buffer(struct brw_context *brw)
1022 {
1023    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
1024    GLuint cut_index_setting;
1025
1026    if (index_buffer == NULL)
1027       return;
1028
1029    if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
1030       cut_index_setting = BRW_CUT_INDEX_ENABLE;
1031    } else {
1032       cut_index_setting = 0;
1033    }
1034
1035    BEGIN_BATCH(3);
1036    OUT_BATCH(CMD_INDEX_BUFFER << 16 |
1037              cut_index_setting |
1038              brw_get_index_type(index_buffer->type) |
1039              1);
1040    OUT_RELOC(brw->ib.bo,
1041              I915_GEM_DOMAIN_VERTEX, 0,
1042              0);
1043    OUT_RELOC(brw->ib.bo,
1044              I915_GEM_DOMAIN_VERTEX, 0,
1045              brw->ib.bo->size - 1);
1046    ADVANCE_BATCH();
1047 }
1048
1049 const struct brw_tracked_state brw_index_buffer = {
1050    .dirty = {
1051       .mesa = 0,
1052       .brw = BRW_NEW_BATCH |
1053              BRW_NEW_BLORP |
1054              BRW_NEW_INDEX_BUFFER,
1055    },
1056    .emit = brw_emit_index_buffer,
1057 };