i965: Move brw_emit_query_begin() to the render ring prelude.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "main/glheader.h"
29 #include "main/bufferobj.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/glformats.h"
34
35 #include "brw_draw.h"
36 #include "brw_defines.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39
40 #include "intel_batchbuffer.h"
41 #include "intel_buffer_objects.h"
42
43 static GLuint double_types[5] = {
44 0,
45 BRW_SURFACEFORMAT_R64_FLOAT,
46 BRW_SURFACEFORMAT_R64G64_FLOAT,
47 BRW_SURFACEFORMAT_R64G64B64_FLOAT,
48 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
49 };
50
51 static GLuint float_types[5] = {
52 0,
53 BRW_SURFACEFORMAT_R32_FLOAT,
54 BRW_SURFACEFORMAT_R32G32_FLOAT,
55 BRW_SURFACEFORMAT_R32G32B32_FLOAT,
56 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
57 };
58
59 static GLuint half_float_types[5] = {
60 0,
61 BRW_SURFACEFORMAT_R16_FLOAT,
62 BRW_SURFACEFORMAT_R16G16_FLOAT,
63 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
64 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
65 };
66
67 static GLuint fixed_point_types[5] = {
68 0,
69 BRW_SURFACEFORMAT_R32_SFIXED,
70 BRW_SURFACEFORMAT_R32G32_SFIXED,
71 BRW_SURFACEFORMAT_R32G32B32_SFIXED,
72 BRW_SURFACEFORMAT_R32G32B32A32_SFIXED,
73 };
74
75 static GLuint uint_types_direct[5] = {
76 0,
77 BRW_SURFACEFORMAT_R32_UINT,
78 BRW_SURFACEFORMAT_R32G32_UINT,
79 BRW_SURFACEFORMAT_R32G32B32_UINT,
80 BRW_SURFACEFORMAT_R32G32B32A32_UINT
81 };
82
83 static GLuint uint_types_norm[5] = {
84 0,
85 BRW_SURFACEFORMAT_R32_UNORM,
86 BRW_SURFACEFORMAT_R32G32_UNORM,
87 BRW_SURFACEFORMAT_R32G32B32_UNORM,
88 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
89 };
90
91 static GLuint uint_types_scale[5] = {
92 0,
93 BRW_SURFACEFORMAT_R32_USCALED,
94 BRW_SURFACEFORMAT_R32G32_USCALED,
95 BRW_SURFACEFORMAT_R32G32B32_USCALED,
96 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
97 };
98
99 static GLuint int_types_direct[5] = {
100 0,
101 BRW_SURFACEFORMAT_R32_SINT,
102 BRW_SURFACEFORMAT_R32G32_SINT,
103 BRW_SURFACEFORMAT_R32G32B32_SINT,
104 BRW_SURFACEFORMAT_R32G32B32A32_SINT
105 };
106
107 static GLuint int_types_norm[5] = {
108 0,
109 BRW_SURFACEFORMAT_R32_SNORM,
110 BRW_SURFACEFORMAT_R32G32_SNORM,
111 BRW_SURFACEFORMAT_R32G32B32_SNORM,
112 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
113 };
114
115 static GLuint int_types_scale[5] = {
116 0,
117 BRW_SURFACEFORMAT_R32_SSCALED,
118 BRW_SURFACEFORMAT_R32G32_SSCALED,
119 BRW_SURFACEFORMAT_R32G32B32_SSCALED,
120 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
121 };
122
123 static GLuint ushort_types_direct[5] = {
124 0,
125 BRW_SURFACEFORMAT_R16_UINT,
126 BRW_SURFACEFORMAT_R16G16_UINT,
127 BRW_SURFACEFORMAT_R16G16B16A16_UINT,
128 BRW_SURFACEFORMAT_R16G16B16A16_UINT
129 };
130
131 static GLuint ushort_types_norm[5] = {
132 0,
133 BRW_SURFACEFORMAT_R16_UNORM,
134 BRW_SURFACEFORMAT_R16G16_UNORM,
135 BRW_SURFACEFORMAT_R16G16B16_UNORM,
136 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
137 };
138
139 static GLuint ushort_types_scale[5] = {
140 0,
141 BRW_SURFACEFORMAT_R16_USCALED,
142 BRW_SURFACEFORMAT_R16G16_USCALED,
143 BRW_SURFACEFORMAT_R16G16B16_USCALED,
144 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
145 };
146
147 static GLuint short_types_direct[5] = {
148 0,
149 BRW_SURFACEFORMAT_R16_SINT,
150 BRW_SURFACEFORMAT_R16G16_SINT,
151 BRW_SURFACEFORMAT_R16G16B16A16_SINT,
152 BRW_SURFACEFORMAT_R16G16B16A16_SINT
153 };
154
155 static GLuint short_types_norm[5] = {
156 0,
157 BRW_SURFACEFORMAT_R16_SNORM,
158 BRW_SURFACEFORMAT_R16G16_SNORM,
159 BRW_SURFACEFORMAT_R16G16B16_SNORM,
160 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
161 };
162
163 static GLuint short_types_scale[5] = {
164 0,
165 BRW_SURFACEFORMAT_R16_SSCALED,
166 BRW_SURFACEFORMAT_R16G16_SSCALED,
167 BRW_SURFACEFORMAT_R16G16B16_SSCALED,
168 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
169 };
170
171 static GLuint ubyte_types_direct[5] = {
172 0,
173 BRW_SURFACEFORMAT_R8_UINT,
174 BRW_SURFACEFORMAT_R8G8_UINT,
175 BRW_SURFACEFORMAT_R8G8B8A8_UINT,
176 BRW_SURFACEFORMAT_R8G8B8A8_UINT
177 };
178
179 static GLuint ubyte_types_norm[5] = {
180 0,
181 BRW_SURFACEFORMAT_R8_UNORM,
182 BRW_SURFACEFORMAT_R8G8_UNORM,
183 BRW_SURFACEFORMAT_R8G8B8_UNORM,
184 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
185 };
186
187 static GLuint ubyte_types_scale[5] = {
188 0,
189 BRW_SURFACEFORMAT_R8_USCALED,
190 BRW_SURFACEFORMAT_R8G8_USCALED,
191 BRW_SURFACEFORMAT_R8G8B8_USCALED,
192 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
193 };
194
195 static GLuint byte_types_direct[5] = {
196 0,
197 BRW_SURFACEFORMAT_R8_SINT,
198 BRW_SURFACEFORMAT_R8G8_SINT,
199 BRW_SURFACEFORMAT_R8G8B8A8_SINT,
200 BRW_SURFACEFORMAT_R8G8B8A8_SINT
201 };
202
203 static GLuint byte_types_norm[5] = {
204 0,
205 BRW_SURFACEFORMAT_R8_SNORM,
206 BRW_SURFACEFORMAT_R8G8_SNORM,
207 BRW_SURFACEFORMAT_R8G8B8_SNORM,
208 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
209 };
210
211 static GLuint byte_types_scale[5] = {
212 0,
213 BRW_SURFACEFORMAT_R8_SSCALED,
214 BRW_SURFACEFORMAT_R8G8_SSCALED,
215 BRW_SURFACEFORMAT_R8G8B8_SSCALED,
216 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
217 };
218
219
220 /**
221 * Given vertex array type/size/format/normalized info, return
222 * the appopriate hardware surface type.
223 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
224 */
225 unsigned
226 brw_get_vertex_surface_type(struct brw_context *brw,
227 const struct gl_client_array *glarray)
228 {
229 int size = glarray->Size;
230
231 if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
232 printf("type %s size %d normalized %d\n",
233 _mesa_lookup_enum_by_nr(glarray->Type),
234 glarray->Size, glarray->Normalized);
235
236 if (glarray->Integer) {
237 assert(glarray->Format == GL_RGBA); /* sanity check */
238 switch (glarray->Type) {
239 case GL_INT: return int_types_direct[size];
240 case GL_SHORT: return short_types_direct[size];
241 case GL_BYTE: return byte_types_direct[size];
242 case GL_UNSIGNED_INT: return uint_types_direct[size];
243 case GL_UNSIGNED_SHORT: return ushort_types_direct[size];
244 case GL_UNSIGNED_BYTE: return ubyte_types_direct[size];
245 default: assert(0); return 0;
246 }
247 } else if (glarray->Type == GL_UNSIGNED_INT_10F_11F_11F_REV) {
248 return BRW_SURFACEFORMAT_R11G11B10_FLOAT;
249 } else if (glarray->Normalized) {
250 switch (glarray->Type) {
251 case GL_DOUBLE: return double_types[size];
252 case GL_FLOAT: return float_types[size];
253 case GL_HALF_FLOAT: return half_float_types[size];
254 case GL_INT: return int_types_norm[size];
255 case GL_SHORT: return short_types_norm[size];
256 case GL_BYTE: return byte_types_norm[size];
257 case GL_UNSIGNED_INT: return uint_types_norm[size];
258 case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
259 case GL_UNSIGNED_BYTE:
260 if (glarray->Format == GL_BGRA) {
261 /* See GL_EXT_vertex_array_bgra */
262 assert(size == 4);
263 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
264 }
265 else {
266 return ubyte_types_norm[size];
267 }
268 case GL_FIXED:
269 if (brw->gen >= 8 || brw->is_haswell)
270 return fixed_point_types[size];
271
272 /* This produces GL_FIXED inputs as values between INT32_MIN and
273 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
274 */
275 return int_types_scale[size];
276 /* See GL_ARB_vertex_type_2_10_10_10_rev.
277 * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
278 * like to use here, so upload everything as UINT and fix
279 * it in the shader
280 */
281 case GL_INT_2_10_10_10_REV:
282 assert(size == 4);
283 if (brw->gen >= 8 || brw->is_haswell) {
284 return glarray->Format == GL_BGRA
285 ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
286 : BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
287 }
288 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
289 case GL_UNSIGNED_INT_2_10_10_10_REV:
290 assert(size == 4);
291 if (brw->gen >= 8 || brw->is_haswell) {
292 return glarray->Format == GL_BGRA
293 ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
294 : BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
295 }
296 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
297 default: assert(0); return 0;
298 }
299 }
300 else {
301 /* See GL_ARB_vertex_type_2_10_10_10_rev.
302 * W/A: the hardware doesn't really support the formats we'd
303 * like to use here, so upload everything as UINT and fix
304 * it in the shader
305 */
306 if (glarray->Type == GL_INT_2_10_10_10_REV) {
307 assert(size == 4);
308 if (brw->gen >= 8 || brw->is_haswell) {
309 return glarray->Format == GL_BGRA
310 ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
311 : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
312 }
313 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
314 } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
315 assert(size == 4);
316 if (brw->gen >= 8 || brw->is_haswell) {
317 return glarray->Format == GL_BGRA
318 ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
319 : BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
320 }
321 return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
322 }
323 assert(glarray->Format == GL_RGBA); /* sanity check */
324 switch (glarray->Type) {
325 case GL_DOUBLE: return double_types[size];
326 case GL_FLOAT: return float_types[size];
327 case GL_HALF_FLOAT: return half_float_types[size];
328 case GL_INT: return int_types_scale[size];
329 case GL_SHORT: return short_types_scale[size];
330 case GL_BYTE: return byte_types_scale[size];
331 case GL_UNSIGNED_INT: return uint_types_scale[size];
332 case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
333 case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
334 case GL_FIXED:
335 if (brw->gen >= 8 || brw->is_haswell)
336 return fixed_point_types[size];
337
338 /* This produces GL_FIXED inputs as values between INT32_MIN and
339 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
340 */
341 return int_types_scale[size];
342 default: assert(0); return 0;
343 }
344 }
345 }
346
347 unsigned
348 brw_get_index_type(GLenum type)
349 {
350 switch (type) {
351 case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
352 case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
353 case GL_UNSIGNED_INT: return BRW_INDEX_DWORD;
354 default: assert(0); return 0;
355 }
356 }
357
358 static void
359 copy_array_to_vbo_array(struct brw_context *brw,
360 struct brw_vertex_element *element,
361 int min, int max,
362 struct brw_vertex_buffer *buffer,
363 GLuint dst_stride)
364 {
365 const int src_stride = element->glarray->StrideB;
366
367 /* If the source stride is zero, we just want to upload the current
368 * attribute once and set the buffer's stride to 0. There's no need
369 * to replicate it out.
370 */
371 if (src_stride == 0) {
372 intel_upload_data(brw, element->glarray->Ptr,
373 element->glarray->_ElementSize,
374 element->glarray->_ElementSize,
375 &buffer->bo, &buffer->offset);
376
377 buffer->stride = 0;
378 return;
379 }
380
381 const unsigned char *src = element->glarray->Ptr + min * src_stride;
382 int count = max - min + 1;
383 GLuint size = count * dst_stride;
384
385 if (dst_stride == src_stride) {
386 intel_upload_data(brw, src, size, dst_stride,
387 &buffer->bo, &buffer->offset);
388 } else {
389 char * const map = intel_upload_map(brw, size, dst_stride);
390 char *dst = map;
391
392 while (count--) {
393 memcpy(dst, src, dst_stride);
394 src += src_stride;
395 dst += dst_stride;
396 }
397 intel_upload_unmap(brw, map, size, dst_stride,
398 &buffer->bo, &buffer->offset);
399 }
400 buffer->stride = dst_stride;
401 }
402
403 static void brw_prepare_vertices(struct brw_context *brw)
404 {
405 struct gl_context *ctx = &brw->ctx;
406 /* CACHE_NEW_VS_PROG */
407 GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
408 const unsigned char *ptr = NULL;
409 GLuint interleaved = 0;
410 unsigned int min_index = brw->vb.min_index + brw->basevertex;
411 unsigned int max_index = brw->vb.max_index + brw->basevertex;
412 int delta, i, j;
413
414 struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
415 GLuint nr_uploads = 0;
416
417 /* _NEW_POLYGON
418 *
419 * On gen6+, edge flags don't end up in the VUE (either in or out of the
420 * VS). Instead, they're uploaded as the last vertex element, and the data
421 * is passed sideband through the fixed function units. So, we need to
422 * prepare the vertex buffer for it, but it's not present in inputs_read.
423 */
424 if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
425 ctx->Polygon.BackMode != GL_FILL)) {
426 vs_inputs |= VERT_BIT_EDGEFLAG;
427 }
428
429 if (0)
430 printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
431
432 /* Accumulate the list of enabled arrays. */
433 brw->vb.nr_enabled = 0;
434 while (vs_inputs) {
435 GLuint i = ffsll(vs_inputs) - 1;
436 struct brw_vertex_element *input = &brw->vb.inputs[i];
437
438 vs_inputs &= ~BITFIELD64_BIT(i);
439 brw->vb.enabled[brw->vb.nr_enabled++] = input;
440 }
441
442 if (brw->vb.nr_enabled == 0)
443 return;
444
445 if (brw->vb.nr_buffers)
446 return;
447
448 for (i = j = 0; i < brw->vb.nr_enabled; i++) {
449 struct brw_vertex_element *input = brw->vb.enabled[i];
450 const struct gl_client_array *glarray = input->glarray;
451
452 if (_mesa_is_bufferobj(glarray->BufferObj)) {
453 struct intel_buffer_object *intel_buffer =
454 intel_buffer_object(glarray->BufferObj);
455 int k;
456
457 /* If we have a VB set to be uploaded for this buffer object
458 * already, reuse that VB state so that we emit fewer
459 * relocations.
460 */
461 for (k = 0; k < i; k++) {
462 const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
463 if (glarray->BufferObj == other->BufferObj &&
464 glarray->StrideB == other->StrideB &&
465 glarray->InstanceDivisor == other->InstanceDivisor &&
466 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
467 {
468 input->buffer = brw->vb.enabled[k]->buffer;
469 input->offset = glarray->Ptr - other->Ptr;
470 break;
471 }
472 }
473 if (k == i) {
474 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
475
476 /* Named buffer object: Just reference its contents directly. */
477 buffer->offset = (uintptr_t)glarray->Ptr;
478 buffer->stride = glarray->StrideB;
479 buffer->step_rate = glarray->InstanceDivisor;
480
481 uint32_t offset, size;
482 if (glarray->InstanceDivisor) {
483 offset = buffer->offset;
484 size = (buffer->stride * ((brw->num_instances /
485 glarray->InstanceDivisor) - 1) +
486 glarray->_ElementSize);
487 } else {
488 if (min_index == -1) {
489 offset = 0;
490 size = intel_buffer->Base.Size;
491 } else {
492 offset = buffer->offset + min_index * buffer->stride;
493 size = (buffer->stride * (max_index - min_index) +
494 glarray->_ElementSize);
495 }
496 }
497 buffer->bo = intel_bufferobj_buffer(brw, intel_buffer,
498 offset, size);
499 drm_intel_bo_reference(buffer->bo);
500
501 input->buffer = j++;
502 input->offset = 0;
503 }
504
505 /* This is a common place to reach if the user mistakenly supplies
506 * a pointer in place of a VBO offset. If we just let it go through,
507 * we may end up dereferencing a pointer beyond the bounds of the
508 * GTT. We would hope that the VBO's max_index would save us, but
509 * Mesa appears to hand us min/max values not clipped to the
510 * array object's _MaxElement, and _MaxElement frequently appears
511 * to be wrong anyway.
512 *
513 * The VBO spec allows application termination in this case, and it's
514 * probably a service to the poor programmer to do so rather than
515 * trying to just not render.
516 */
517 assert(input->offset < brw->vb.buffers[input->buffer].bo->size);
518 } else {
519 /* Queue the buffer object up to be uploaded in the next pass,
520 * when we've decided if we're doing interleaved or not.
521 */
522 if (nr_uploads == 0) {
523 interleaved = glarray->StrideB;
524 ptr = glarray->Ptr;
525 }
526 else if (interleaved != glarray->StrideB ||
527 glarray->Ptr < ptr ||
528 (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
529 {
530 /* If our stride is different from the first attribute's stride,
531 * or if the first attribute's stride didn't cover our element,
532 * disable the interleaved upload optimization. The second case
533 * can most commonly occur in cases where there is a single vertex
534 * and, for example, the data is stored on the application's
535 * stack.
536 *
537 * NOTE: This will also disable the optimization in cases where
538 * the data is in a different order than the array indices.
539 * Something like:
540 *
541 * float data[...];
542 * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
543 * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
544 */
545 interleaved = 0;
546 }
547
548 upload[nr_uploads++] = input;
549 }
550 }
551
552 /* If we need to upload all the arrays, then we can trim those arrays to
553 * only the used elements [min_index, max_index] so long as we adjust all
554 * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
555 */
556 brw->vb.start_vertex_bias = 0;
557 delta = min_index;
558 if (nr_uploads == brw->vb.nr_enabled) {
559 brw->vb.start_vertex_bias = -delta;
560 delta = 0;
561 }
562
563 /* Handle any arrays to be uploaded. */
564 if (nr_uploads > 1) {
565 if (interleaved) {
566 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
567 /* All uploads are interleaved, so upload the arrays together as
568 * interleaved. First, upload the contents and set up upload[0].
569 */
570 copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
571 buffer, interleaved);
572 buffer->offset -= delta * interleaved;
573
574 for (i = 0; i < nr_uploads; i++) {
575 /* Then, just point upload[i] at upload[0]'s buffer. */
576 upload[i]->offset =
577 ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
578 upload[i]->buffer = j;
579 }
580 j++;
581
582 nr_uploads = 0;
583 }
584 }
585 /* Upload non-interleaved arrays */
586 for (i = 0; i < nr_uploads; i++) {
587 struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
588 if (upload[i]->glarray->InstanceDivisor == 0) {
589 copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
590 buffer, upload[i]->glarray->_ElementSize);
591 } else {
592 /* This is an instanced attribute, since its InstanceDivisor
593 * is not zero. Therefore, its data will be stepped after the
594 * instanced draw has been run InstanceDivisor times.
595 */
596 uint32_t instanced_attr_max_index =
597 (brw->num_instances - 1) / upload[i]->glarray->InstanceDivisor;
598 copy_array_to_vbo_array(brw, upload[i], 0, instanced_attr_max_index,
599 buffer, upload[i]->glarray->_ElementSize);
600 }
601 buffer->offset -= delta * buffer->stride;
602 buffer->step_rate = upload[i]->glarray->InstanceDivisor;
603 upload[i]->buffer = j++;
604 upload[i]->offset = 0;
605 }
606
607 brw->vb.nr_buffers = j;
608 }
609
610 static void brw_emit_vertices(struct brw_context *brw)
611 {
612 struct gl_context *ctx = &brw->ctx;
613 GLuint i, nr_elements;
614
615 brw_prepare_vertices(brw);
616
617 nr_elements = brw->vb.nr_enabled + brw->vs.prog_data->uses_vertexid;
618
619 /* If the VS doesn't read any inputs (calculating vertex position from
620 * a state variable for some reason, for example), emit a single pad
621 * VERTEX_ELEMENT struct and bail.
622 *
623 * The stale VB state stays in place, but they don't do anything unless
624 * a VE loads from them.
625 */
626 if (nr_elements == 0) {
627 BEGIN_BATCH(3);
628 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
629 if (brw->gen >= 6) {
630 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
631 GEN6_VE0_VALID |
632 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
633 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
634 } else {
635 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
636 BRW_VE0_VALID |
637 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
638 (0 << BRW_VE0_SRC_OFFSET_SHIFT));
639 }
640 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
641 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
642 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
643 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
644 CACHED_BATCH();
645 return;
646 }
647
648 /* Now emit VB and VEP state packets.
649 */
650
651 if (brw->vb.nr_buffers) {
652 if (brw->gen >= 6) {
653 assert(brw->vb.nr_buffers <= 33);
654 } else {
655 assert(brw->vb.nr_buffers <= 17);
656 }
657
658 BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
659 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
660 for (i = 0; i < brw->vb.nr_buffers; i++) {
661 struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
662 uint32_t dw0;
663
664 if (brw->gen >= 6) {
665 dw0 = buffer->step_rate
666 ? GEN6_VB0_ACCESS_INSTANCEDATA
667 : GEN6_VB0_ACCESS_VERTEXDATA;
668 dw0 |= i << GEN6_VB0_INDEX_SHIFT;
669 } else {
670 dw0 = buffer->step_rate
671 ? BRW_VB0_ACCESS_INSTANCEDATA
672 : BRW_VB0_ACCESS_VERTEXDATA;
673 dw0 |= i << BRW_VB0_INDEX_SHIFT;
674 }
675
676 if (brw->gen >= 7)
677 dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
678
679 if (brw->gen == 7)
680 dw0 |= GEN7_MOCS_L3 << 16;
681
682 WARN_ONCE(buffer->stride >= (brw->gen >= 5 ? 2048 : 2047),
683 "VBO stride %d too large, bad rendering may occur\n",
684 buffer->stride);
685 OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
686 OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
687 if (brw->gen >= 5) {
688 OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1);
689 } else
690 OUT_BATCH(0);
691 OUT_BATCH(buffer->step_rate);
692 }
693 ADVANCE_BATCH();
694 }
695
696 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
697 * for VertexID/InstanceID.
698 */
699 if (brw->gen >= 6) {
700 assert(nr_elements <= 34);
701 } else {
702 assert(nr_elements <= 18);
703 }
704
705 struct brw_vertex_element *gen6_edgeflag_input = NULL;
706
707 BEGIN_BATCH(1 + nr_elements * 2);
708 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
709 for (i = 0; i < brw->vb.nr_enabled; i++) {
710 struct brw_vertex_element *input = brw->vb.enabled[i];
711 uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
712 uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
713 uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
714 uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
715 uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
716
717 /* The gen4 driver expects edgeflag to come in as a float, and passes
718 * that float on to the tests in the clipper. Mesa's current vertex
719 * attribute value for EdgeFlag is stored as a float, which works out.
720 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
721 * integer ubyte. Just rewrite that to convert to a float.
722 */
723 if (input->attrib == VERT_ATTRIB_EDGEFLAG) {
724 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
725 * of in the VUE. We have to upload it sideband as the last vertex
726 * element according to the B-Spec.
727 */
728 if (brw->gen >= 6) {
729 gen6_edgeflag_input = input;
730 continue;
731 }
732
733 if (format == BRW_SURFACEFORMAT_R8_UINT)
734 format = BRW_SURFACEFORMAT_R8_SSCALED;
735 }
736
737 switch (input->glarray->Size) {
738 case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
739 case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
740 case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
741 case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
742 : BRW_VE1_COMPONENT_STORE_1_FLT;
743 break;
744 }
745
746 if (brw->gen >= 6) {
747 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
748 GEN6_VE0_VALID |
749 (format << BRW_VE0_FORMAT_SHIFT) |
750 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
751 } else {
752 OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
753 BRW_VE0_VALID |
754 (format << BRW_VE0_FORMAT_SHIFT) |
755 (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
756 }
757
758 if (brw->gen >= 5)
759 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
760 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
761 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
762 (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
763 else
764 OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
765 (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
766 (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
767 (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
768 ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
769 }
770
771 if (brw->gen >= 6 && gen6_edgeflag_input) {
772 uint32_t format =
773 brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
774
775 OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
776 GEN6_VE0_VALID |
777 GEN6_VE0_EDGE_FLAG_ENABLE |
778 (format << BRW_VE0_FORMAT_SHIFT) |
779 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
780 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
781 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
782 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
783 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
784 }
785
786 if (brw->vs.prog_data->uses_vertexid) {
787 uint32_t dw0 = 0, dw1 = 0;
788
789 dw1 = ((BRW_VE1_COMPONENT_STORE_VID << BRW_VE1_COMPONENT_0_SHIFT) |
790 (BRW_VE1_COMPONENT_STORE_IID << BRW_VE1_COMPONENT_1_SHIFT) |
791 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
792 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
793
794 if (brw->gen >= 6) {
795 dw0 |= GEN6_VE0_VALID;
796 } else {
797 dw0 |= BRW_VE0_VALID;
798 dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
799 }
800
801 /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
802 * the format is ignored and the value is always int.
803 */
804
805 OUT_BATCH(dw0);
806 OUT_BATCH(dw1);
807 }
808
809 CACHED_BATCH();
810 }
811
812 const struct brw_tracked_state brw_vertices = {
813 .dirty = {
814 .mesa = _NEW_POLYGON,
815 .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
816 .cache = CACHE_NEW_VS_PROG,
817 },
818 .emit = brw_emit_vertices,
819 };
820
821 static void brw_upload_indices(struct brw_context *brw)
822 {
823 struct gl_context *ctx = &brw->ctx;
824 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
825 GLuint ib_size;
826 drm_intel_bo *bo = NULL;
827 struct gl_buffer_object *bufferobj;
828 GLuint offset;
829 GLuint ib_type_size;
830
831 if (index_buffer == NULL)
832 return;
833
834 ib_type_size = _mesa_sizeof_type(index_buffer->type);
835 ib_size = ib_type_size * index_buffer->count;
836 bufferobj = index_buffer->obj;
837
838 /* Turn into a proper VBO:
839 */
840 if (!_mesa_is_bufferobj(bufferobj)) {
841
842 /* Get new bufferobj, offset:
843 */
844 intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
845 &bo, &offset);
846 brw->ib.start_vertex_offset = offset / ib_type_size;
847 } else {
848 offset = (GLuint) (unsigned long) index_buffer->ptr;
849
850 /* If the index buffer isn't aligned to its element size, we have to
851 * rebase it into a temporary.
852 */
853 if ((ib_type_size - 1) & offset) {
854 perf_debug("copying index buffer to a temporary to work around "
855 "misaligned offset %d\n", offset);
856
857 GLubyte *map = ctx->Driver.MapBufferRange(ctx,
858 offset,
859 ib_size,
860 GL_MAP_READ_BIT,
861 bufferobj);
862
863 intel_upload_data(brw, map, ib_size, ib_type_size, &bo, &offset);
864 brw->ib.start_vertex_offset = offset / ib_type_size;
865
866 ctx->Driver.UnmapBuffer(ctx, bufferobj);
867 } else {
868 /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
869 * the index buffer state when we're just moving the start index
870 * of our drawing.
871 */
872 brw->ib.start_vertex_offset = offset / ib_type_size;
873
874 bo = intel_bufferobj_buffer(brw, intel_buffer_object(bufferobj),
875 offset, ib_size);
876 drm_intel_bo_reference(bo);
877 }
878 }
879
880 if (brw->ib.bo != bo) {
881 drm_intel_bo_unreference(brw->ib.bo);
882 brw->ib.bo = bo;
883
884 brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
885 } else {
886 drm_intel_bo_unreference(bo);
887 }
888
889 if (index_buffer->type != brw->ib.type) {
890 brw->ib.type = index_buffer->type;
891 brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
892 }
893 }
894
895 const struct brw_tracked_state brw_indices = {
896 .dirty = {
897 .mesa = 0,
898 .brw = BRW_NEW_INDICES,
899 .cache = 0,
900 },
901 .emit = brw_upload_indices,
902 };
903
904 static void brw_emit_index_buffer(struct brw_context *brw)
905 {
906 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
907 GLuint cut_index_setting;
908
909 if (index_buffer == NULL)
910 return;
911
912 if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
913 cut_index_setting = BRW_CUT_INDEX_ENABLE;
914 } else {
915 cut_index_setting = 0;
916 }
917
918 BEGIN_BATCH(3);
919 OUT_BATCH(CMD_INDEX_BUFFER << 16 |
920 cut_index_setting |
921 brw_get_index_type(index_buffer->type) << 8 |
922 1);
923 OUT_RELOC(brw->ib.bo,
924 I915_GEM_DOMAIN_VERTEX, 0,
925 0);
926 OUT_RELOC(brw->ib.bo,
927 I915_GEM_DOMAIN_VERTEX, 0,
928 brw->ib.bo->size - 1);
929 ADVANCE_BATCH();
930 }
931
932 const struct brw_tracked_state brw_index_buffer = {
933 .dirty = {
934 .mesa = 0,
935 .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
936 .cache = 0,
937 },
938 .emit = brw_emit_index_buffer,
939 };