src/mesa/drivers/dri/i965/brw_draw_upload.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/bufferobj.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/macros.h"
  33 #include "main/glformats.h"
  34
  35 #include "brw_draw.h"
  36 #include "brw_defines.h"
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39
  40 #include "intel_batchbuffer.h"
  41 #include "intel_buffer_objects.h"
  42
  43 static GLuint double_types[5] = {
  44    0,
  45    BRW_SURFACEFORMAT_R64_FLOAT,
  46    BRW_SURFACEFORMAT_R64G64_FLOAT,
  47    BRW_SURFACEFORMAT_R64G64B64_FLOAT,
  48    BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
  49 };
  50
  51 static GLuint float_types[5] = {
  52    0,
  53    BRW_SURFACEFORMAT_R32_FLOAT,
  54    BRW_SURFACEFORMAT_R32G32_FLOAT,
  55    BRW_SURFACEFORMAT_R32G32B32_FLOAT,
  56    BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
  57 };
  58
  59 static GLuint half_float_types[5] = {
  60    0,
  61    BRW_SURFACEFORMAT_R16_FLOAT,
  62    BRW_SURFACEFORMAT_R16G16_FLOAT,
  63    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT,
  64    BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
  65 };
  66
  67 static GLuint fixed_point_types[5] = {
  68    0,
  69    BRW_SURFACEFORMAT_R32_SFIXED,
  70    BRW_SURFACEFORMAT_R32G32_SFIXED,
  71    BRW_SURFACEFORMAT_R32G32B32_SFIXED,
  72    BRW_SURFACEFORMAT_R32G32B32A32_SFIXED,
  73 };
  74
  75 static GLuint uint_types_direct[5] = {
  76    0,
  77    BRW_SURFACEFORMAT_R32_UINT,
  78    BRW_SURFACEFORMAT_R32G32_UINT,
  79    BRW_SURFACEFORMAT_R32G32B32_UINT,
  80    BRW_SURFACEFORMAT_R32G32B32A32_UINT
  81 };
  82
  83 static GLuint uint_types_norm[5] = {
  84    0,
  85    BRW_SURFACEFORMAT_R32_UNORM,
  86    BRW_SURFACEFORMAT_R32G32_UNORM,
  87    BRW_SURFACEFORMAT_R32G32B32_UNORM,
  88    BRW_SURFACEFORMAT_R32G32B32A32_UNORM
  89 };
  90
  91 static GLuint uint_types_scale[5] = {
  92    0,
  93    BRW_SURFACEFORMAT_R32_USCALED,
  94    BRW_SURFACEFORMAT_R32G32_USCALED,
  95    BRW_SURFACEFORMAT_R32G32B32_USCALED,
  96    BRW_SURFACEFORMAT_R32G32B32A32_USCALED
  97 };
  98
  99 static GLuint int_types_direct[5] = {
 100    0,
 101    BRW_SURFACEFORMAT_R32_SINT,
 102    BRW_SURFACEFORMAT_R32G32_SINT,
 103    BRW_SURFACEFORMAT_R32G32B32_SINT,
 104    BRW_SURFACEFORMAT_R32G32B32A32_SINT
 105 };
 106
 107 static GLuint int_types_norm[5] = {
 108    0,
 109    BRW_SURFACEFORMAT_R32_SNORM,
 110    BRW_SURFACEFORMAT_R32G32_SNORM,
 111    BRW_SURFACEFORMAT_R32G32B32_SNORM,
 112    BRW_SURFACEFORMAT_R32G32B32A32_SNORM
 113 };
 114
 115 static GLuint int_types_scale[5] = {
 116    0,
 117    BRW_SURFACEFORMAT_R32_SSCALED,
 118    BRW_SURFACEFORMAT_R32G32_SSCALED,
 119    BRW_SURFACEFORMAT_R32G32B32_SSCALED,
 120    BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
 121 };
 122
 123 static GLuint ushort_types_direct[5] = {
 124    0,
 125    BRW_SURFACEFORMAT_R16_UINT,
 126    BRW_SURFACEFORMAT_R16G16_UINT,
 127    BRW_SURFACEFORMAT_R16G16B16A16_UINT,
 128    BRW_SURFACEFORMAT_R16G16B16A16_UINT
 129 };
 130
 131 static GLuint ushort_types_norm[5] = {
 132    0,
 133    BRW_SURFACEFORMAT_R16_UNORM,
 134    BRW_SURFACEFORMAT_R16G16_UNORM,
 135    BRW_SURFACEFORMAT_R16G16B16_UNORM,
 136    BRW_SURFACEFORMAT_R16G16B16A16_UNORM
 137 };
 138
 139 static GLuint ushort_types_scale[5] = {
 140    0,
 141    BRW_SURFACEFORMAT_R16_USCALED,
 142    BRW_SURFACEFORMAT_R16G16_USCALED,
 143    BRW_SURFACEFORMAT_R16G16B16_USCALED,
 144    BRW_SURFACEFORMAT_R16G16B16A16_USCALED
 145 };
 146
 147 static GLuint short_types_direct[5] = {
 148    0,
 149    BRW_SURFACEFORMAT_R16_SINT,
 150    BRW_SURFACEFORMAT_R16G16_SINT,
 151    BRW_SURFACEFORMAT_R16G16B16A16_SINT,
 152    BRW_SURFACEFORMAT_R16G16B16A16_SINT
 153 };
 154
 155 static GLuint short_types_norm[5] = {
 156    0,
 157    BRW_SURFACEFORMAT_R16_SNORM,
 158    BRW_SURFACEFORMAT_R16G16_SNORM,
 159    BRW_SURFACEFORMAT_R16G16B16_SNORM,
 160    BRW_SURFACEFORMAT_R16G16B16A16_SNORM
 161 };
 162
 163 static GLuint short_types_scale[5] = {
 164    0,
 165    BRW_SURFACEFORMAT_R16_SSCALED,
 166    BRW_SURFACEFORMAT_R16G16_SSCALED,
 167    BRW_SURFACEFORMAT_R16G16B16_SSCALED,
 168    BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
 169 };
 170
 171 static GLuint ubyte_types_direct[5] = {
 172    0,
 173    BRW_SURFACEFORMAT_R8_UINT,
 174    BRW_SURFACEFORMAT_R8G8_UINT,
 175    BRW_SURFACEFORMAT_R8G8B8A8_UINT,
 176    BRW_SURFACEFORMAT_R8G8B8A8_UINT
 177 };
 178
 179 static GLuint ubyte_types_norm[5] = {
 180    0,
 181    BRW_SURFACEFORMAT_R8_UNORM,
 182    BRW_SURFACEFORMAT_R8G8_UNORM,
 183    BRW_SURFACEFORMAT_R8G8B8_UNORM,
 184    BRW_SURFACEFORMAT_R8G8B8A8_UNORM
 185 };
 186
 187 static GLuint ubyte_types_scale[5] = {
 188    0,
 189    BRW_SURFACEFORMAT_R8_USCALED,
 190    BRW_SURFACEFORMAT_R8G8_USCALED,
 191    BRW_SURFACEFORMAT_R8G8B8_USCALED,
 192    BRW_SURFACEFORMAT_R8G8B8A8_USCALED
 193 };
 194
 195 static GLuint byte_types_direct[5] = {
 196    0,
 197    BRW_SURFACEFORMAT_R8_SINT,
 198    BRW_SURFACEFORMAT_R8G8_SINT,
 199    BRW_SURFACEFORMAT_R8G8B8A8_SINT,
 200    BRW_SURFACEFORMAT_R8G8B8A8_SINT
 201 };
 202
 203 static GLuint byte_types_norm[5] = {
 204    0,
 205    BRW_SURFACEFORMAT_R8_SNORM,
 206    BRW_SURFACEFORMAT_R8G8_SNORM,
 207    BRW_SURFACEFORMAT_R8G8B8_SNORM,
 208    BRW_SURFACEFORMAT_R8G8B8A8_SNORM
 209 };
 210
 211 static GLuint byte_types_scale[5] = {
 212    0,
 213    BRW_SURFACEFORMAT_R8_SSCALED,
 214    BRW_SURFACEFORMAT_R8G8_SSCALED,
 215    BRW_SURFACEFORMAT_R8G8B8_SSCALED,
 216    BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
 217 };
 218
 219
 220 /**
 221  * Given vertex array type/size/format/normalized info, return
 222  * the appopriate hardware surface type.
 223  * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
 224  */
 225 static unsigned
 226 get_surface_type(struct brw_context *brw,
 227                  const struct gl_client_array *glarray)
 228 {
 229    struct intel_context *intel = &brw->intel;
 230    int size = glarray->Size;
 231
 232    if (unlikely(INTEL_DEBUG & DEBUG_VERTS))
 233       printf("type %s size %d normalized %d\n",
 234              _mesa_lookup_enum_by_nr(glarray->Type),
 235              glarray->Size, glarray->Normalized);
 236
 237    if (glarray->Integer) {
 238       assert(glarray->Format == GL_RGBA); /* sanity check */
 239       switch (glarray->Type) {
 240       case GL_INT: return int_types_direct[size];
 241       case GL_SHORT: return short_types_direct[size];
 242       case GL_BYTE: return byte_types_direct[size];
 243       case GL_UNSIGNED_INT: return uint_types_direct[size];
 244       case GL_UNSIGNED_SHORT: return ushort_types_direct[size];
 245       case GL_UNSIGNED_BYTE: return ubyte_types_direct[size];
 246       default: assert(0); return 0;
 247       }
 248    } else if (glarray->Normalized) {
 249       switch (glarray->Type) {
 250       case GL_DOUBLE: return double_types[size];
 251       case GL_FLOAT: return float_types[size];
 252       case GL_HALF_FLOAT: return half_float_types[size];
 253       case GL_INT: return int_types_norm[size];
 254       case GL_SHORT: return short_types_norm[size];
 255       case GL_BYTE: return byte_types_norm[size];
 256       case GL_UNSIGNED_INT: return uint_types_norm[size];
 257       case GL_UNSIGNED_SHORT: return ushort_types_norm[size];
 258       case GL_UNSIGNED_BYTE:
 259          if (glarray->Format == GL_BGRA) {
 260             /* See GL_EXT_vertex_array_bgra */
 261             assert(size == 4);
 262             return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 263          }
 264          else {
 265             return ubyte_types_norm[size];
 266          }
 267       case GL_FIXED:
 268          if (intel->gen >= 8 || intel->is_haswell)
 269             return fixed_point_types[size];
 270
 271          /* This produces GL_FIXED inputs as values between INT32_MIN and
 272           * INT32_MAX, which will be scaled down by 1/65536 by the VS.
 273           */
 274          return int_types_scale[size];
 275       /* See GL_ARB_vertex_type_2_10_10_10_rev.
 276        * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
 277        * like to use here, so upload everything as UINT and fix
 278        * it in the shader
 279        */
 280       case GL_INT_2_10_10_10_REV:
 281          assert(size == 4);
 282          if (intel->gen >= 8 || intel->is_haswell) {
 283             return glarray->Format == GL_BGRA
 284                ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
 285                : BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
 286          }
 287          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 288       case GL_UNSIGNED_INT_2_10_10_10_REV:
 289          assert(size == 4);
 290          if (intel->gen >= 8 || intel->is_haswell) {
 291             return glarray->Format == GL_BGRA
 292                ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
 293                : BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
 294          }
 295          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 296       default: assert(0); return 0;
 297       }
 298    }
 299    else {
 300       /* See GL_ARB_vertex_type_2_10_10_10_rev.
 301        * W/A: the hardware doesn't really support the formats we'd
 302        * like to use here, so upload everything as UINT and fix
 303        * it in the shader
 304        */
 305       if (glarray->Type == GL_INT_2_10_10_10_REV) {
 306          assert(size == 4);
 307          if (intel->gen >= 8 || intel->is_haswell) {
 308             return glarray->Format == GL_BGRA
 309                ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
 310                : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
 311          }
 312          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 313       } else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
 314          assert(size == 4);
 315          if (intel->gen >= 8 || intel->is_haswell) {
 316             return glarray->Format == GL_BGRA
 317                ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
 318                : BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
 319          }
 320          return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
 321       }
 322       assert(glarray->Format == GL_RGBA); /* sanity check */
 323       switch (glarray->Type) {
 324       case GL_DOUBLE: return double_types[size];
 325       case GL_FLOAT: return float_types[size];
 326       case GL_HALF_FLOAT: return half_float_types[size];
 327       case GL_INT: return int_types_scale[size];
 328       case GL_SHORT: return short_types_scale[size];
 329       case GL_BYTE: return byte_types_scale[size];
 330       case GL_UNSIGNED_INT: return uint_types_scale[size];
 331       case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
 332       case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
 333       case GL_FIXED:
 334          if (intel->gen >= 8 || intel->is_haswell)
 335             return fixed_point_types[size];
 336
 337          /* This produces GL_FIXED inputs as values between INT32_MIN and
 338           * INT32_MAX, which will be scaled down by 1/65536 by the VS.
 339           */
 340          return int_types_scale[size];
 341       default: assert(0); return 0;
 342       }
 343    }
 344 }
 345
 346 static GLuint get_index_type(GLenum type)
 347 {
 348    switch (type) {
 349    case GL_UNSIGNED_BYTE:  return BRW_INDEX_BYTE;
 350    case GL_UNSIGNED_SHORT: return BRW_INDEX_WORD;
 351    case GL_UNSIGNED_INT:   return BRW_INDEX_DWORD;
 352    default: assert(0); return 0;
 353    }
 354 }
 355
 356 static void
 357 copy_array_to_vbo_array(struct brw_context *brw,
 358                         struct brw_vertex_element *element,
 359                         int min, int max,
 360                         struct brw_vertex_buffer *buffer,
 361                         GLuint dst_stride)
 362 {
 363    const int src_stride = element->glarray->StrideB;
 364
 365    /* If the source stride is zero, we just want to upload the current
 366     * attribute once and set the buffer's stride to 0.  There's no need
 367     * to replicate it out.
 368     */
 369    if (src_stride == 0) {
 370       intel_upload_data(brw, element->glarray->Ptr,
 371                         element->glarray->_ElementSize,
 372                         element->glarray->_ElementSize,
 373                         &buffer->bo, &buffer->offset);
 374
 375       buffer->stride = 0;
 376       return;
 377    }
 378
 379    const unsigned char *src = element->glarray->Ptr + min * src_stride;
 380    int count = max - min + 1;
 381    GLuint size = count * dst_stride;
 382
 383    if (dst_stride == src_stride) {
 384       intel_upload_data(brw, src, size, dst_stride,
 385                         &buffer->bo, &buffer->offset);
 386    } else {
 387       char * const map = intel_upload_map(brw, size, dst_stride);
 388       char *dst = map;
 389
 390       while (count--) {
 391          memcpy(dst, src, dst_stride);
 392          src += src_stride;
 393          dst += dst_stride;
 394       }
 395       intel_upload_unmap(brw, map, size, dst_stride,
 396                          &buffer->bo, &buffer->offset);
 397    }
 398    buffer->stride = dst_stride;
 399 }
 400
 401 static void brw_prepare_vertices(struct brw_context *brw)
 402 {
 403    struct gl_context *ctx = &brw->intel.ctx;
 404    struct intel_context *intel = intel_context(ctx);
 405    /* CACHE_NEW_VS_PROG */
 406    GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
 407    const unsigned char *ptr = NULL;
 408    GLuint interleaved = 0;
 409    unsigned int min_index = brw->vb.min_index + brw->basevertex;
 410    unsigned int max_index = brw->vb.max_index + brw->basevertex;
 411    int delta, i, j;
 412
 413    struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
 414    GLuint nr_uploads = 0;
 415
 416    /* _NEW_POLYGON
 417     *
 418     * On gen6+, edge flags don't end up in the VUE (either in or out of the
 419     * VS).  Instead, they're uploaded as the last vertex element, and the data
 420     * is passed sideband through the fixed function units.  So, we need to
 421     * prepare the vertex buffer for it, but it's not present in inputs_read.
 422     */
 423    if (intel->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
 424                            ctx->Polygon.BackMode != GL_FILL)) {
 425       vs_inputs |= VERT_BIT_EDGEFLAG;
 426    }
 427
 428    if (0)
 429       printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
 430
 431    /* Accumulate the list of enabled arrays. */
 432    brw->vb.nr_enabled = 0;
 433    while (vs_inputs) {
 434       GLuint i = ffsll(vs_inputs) - 1;
 435       struct brw_vertex_element *input = &brw->vb.inputs[i];
 436
 437       vs_inputs &= ~BITFIELD64_BIT(i);
 438       brw->vb.enabled[brw->vb.nr_enabled++] = input;
 439    }
 440
 441    if (brw->vb.nr_enabled == 0)
 442       return;
 443
 444    if (brw->vb.nr_buffers)
 445       return;
 446
 447    for (i = j = 0; i < brw->vb.nr_enabled; i++) {
 448       struct brw_vertex_element *input = brw->vb.enabled[i];
 449       const struct gl_client_array *glarray = input->glarray;
 450
 451       if (_mesa_is_bufferobj(glarray->BufferObj)) {
 452          struct intel_buffer_object *intel_buffer =
 453             intel_buffer_object(glarray->BufferObj);
 454          int k;
 455
 456          /* If we have a VB set to be uploaded for this buffer object
 457           * already, reuse that VB state so that we emit fewer
 458           * relocations.
 459           */
 460          for (k = 0; k < i; k++) {
 461             const struct gl_client_array *other = brw->vb.enabled[k]->glarray;
 462             if (glarray->BufferObj == other->BufferObj &&
 463                 glarray->StrideB == other->StrideB &&
 464                 glarray->InstanceDivisor == other->InstanceDivisor &&
 465                 (uintptr_t)(glarray->Ptr - other->Ptr) < glarray->StrideB)
 466             {
 467                input->buffer = brw->vb.enabled[k]->buffer;
 468                input->offset = glarray->Ptr - other->Ptr;
 469                break;
 470             }
 471          }
 472          if (k == i) {
 473             struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 474
 475             /* Named buffer object: Just reference its contents directly. */
 476             buffer->bo = intel_bufferobj_source(brw,
 477                                                 intel_buffer, 1,
 478                                                 &buffer->offset);
 479             drm_intel_bo_reference(buffer->bo);
 480             buffer->offset += (uintptr_t)glarray->Ptr;
 481             buffer->stride = glarray->StrideB;
 482             buffer->step_rate = glarray->InstanceDivisor;
 483
 484             input->buffer = j++;
 485             input->offset = 0;
 486          }
 487
 488          /* This is a common place to reach if the user mistakenly supplies
 489           * a pointer in place of a VBO offset.  If we just let it go through,
 490           * we may end up dereferencing a pointer beyond the bounds of the
 491           * GTT.  We would hope that the VBO's max_index would save us, but
 492           * Mesa appears to hand us min/max values not clipped to the
 493           * array object's _MaxElement, and _MaxElement frequently appears
 494           * to be wrong anyway.
 495           *
 496           * The VBO spec allows application termination in this case, and it's
 497           * probably a service to the poor programmer to do so rather than
 498           * trying to just not render.
 499           */
 500          assert(input->offset < brw->vb.buffers[input->buffer].bo->size);
 501       } else {
 502          /* Queue the buffer object up to be uploaded in the next pass,
 503           * when we've decided if we're doing interleaved or not.
 504           */
 505          if (nr_uploads == 0) {
 506             interleaved = glarray->StrideB;
 507             ptr = glarray->Ptr;
 508          }
 509          else if (interleaved != glarray->StrideB ||
 510                   glarray->Ptr < ptr ||
 511                   (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
 512          {
 513             /* If our stride is different from the first attribute's stride,
 514              * or if the first attribute's stride didn't cover our element,
 515              * disable the interleaved upload optimization.  The second case
 516              * can most commonly occur in cases where there is a single vertex
 517              * and, for example, the data is stored on the application's
 518              * stack.
 519              *
 520              * NOTE: This will also disable the optimization in cases where
 521              * the data is in a different order than the array indices.
 522              * Something like:
 523              *
 524              *     float data[...];
 525              *     glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
 526              *     glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
 527              */
 528             interleaved = 0;
 529          }
 530
 531          upload[nr_uploads++] = input;
 532       }
 533    }
 534
 535    /* If we need to upload all the arrays, then we can trim those arrays to
 536     * only the used elements [min_index, max_index] so long as we adjust all
 537     * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
 538     */
 539    brw->vb.start_vertex_bias = 0;
 540    delta = min_index;
 541    if (nr_uploads == brw->vb.nr_enabled) {
 542       brw->vb.start_vertex_bias = -delta;
 543       delta = 0;
 544    }
 545
 546    /* Handle any arrays to be uploaded. */
 547    if (nr_uploads > 1) {
 548       if (interleaved) {
 549          struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 550          /* All uploads are interleaved, so upload the arrays together as
 551           * interleaved.  First, upload the contents and set up upload[0].
 552           */
 553          copy_array_to_vbo_array(brw, upload[0], min_index, max_index,
 554                                  buffer, interleaved);
 555          buffer->offset -= delta * interleaved;
 556
 557          for (i = 0; i < nr_uploads; i++) {
 558             /* Then, just point upload[i] at upload[0]'s buffer. */
 559             upload[i]->offset =
 560                ((const unsigned char *)upload[i]->glarray->Ptr - ptr);
 561             upload[i]->buffer = j;
 562          }
 563          j++;
 564
 565          nr_uploads = 0;
 566       }
 567    }
 568    /* Upload non-interleaved arrays */
 569    for (i = 0; i < nr_uploads; i++) {
 570       struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
 571       if (upload[i]->glarray->InstanceDivisor == 0) {
 572          copy_array_to_vbo_array(brw, upload[i], min_index, max_index,
 573                                  buffer, upload[i]->glarray->_ElementSize);
 574       } else {
 575          /* This is an instanced attribute, since its InstanceDivisor
 576           * is not zero. Therefore, its data will be stepped after the
 577           * instanced draw has been run InstanceDivisor times.
 578           */
 579          uint32_t instanced_attr_max_index =
 580             (brw->num_instances - 1) / upload[i]->glarray->InstanceDivisor;
 581          copy_array_to_vbo_array(brw, upload[i], 0, instanced_attr_max_index,
 582                                  buffer, upload[i]->glarray->_ElementSize);
 583       }
 584       buffer->offset -= delta * buffer->stride;
 585       buffer->step_rate = upload[i]->glarray->InstanceDivisor;
 586       upload[i]->buffer = j++;
 587       upload[i]->offset = 0;
 588    }
 589
 590    brw->vb.nr_buffers = j;
 591 }
 592
 593 static void brw_emit_vertices(struct brw_context *brw)
 594 {
 595    struct gl_context *ctx = &brw->intel.ctx;
 596    struct intel_context *intel = intel_context(ctx);
 597    GLuint i, nr_elements;
 598
 599    brw_prepare_vertices(brw);
 600
 601    brw_emit_query_begin(brw);
 602
 603    nr_elements = brw->vb.nr_enabled + brw->vs.prog_data->uses_vertexid;
 604
 605    /* If the VS doesn't read any inputs (calculating vertex position from
 606     * a state variable for some reason, for example), emit a single pad
 607     * VERTEX_ELEMENT struct and bail.
 608     *
 609     * The stale VB state stays in place, but they don't do anything unless
 610     * a VE loads from them.
 611     */
 612    if (nr_elements == 0) {
 613       BEGIN_BATCH(3);
 614       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
 615       if (intel->gen >= 6) {
 616          OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
 617                    GEN6_VE0_VALID |
 618                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 619                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 620       } else {
 621          OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
 622                    BRW_VE0_VALID |
 623                    (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
 624                    (0 << BRW_VE0_SRC_OFFSET_SHIFT));
 625       }
 626       OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
 627                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 628                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 629                 (BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
 630       CACHED_BATCH();
 631       return;
 632    }
 633
 634    /* Now emit VB and VEP state packets.
 635     */
 636
 637    if (brw->vb.nr_buffers) {
 638       if (intel->gen >= 6) {
 639          assert(brw->vb.nr_buffers <= 33);
 640       } else {
 641          assert(brw->vb.nr_buffers <= 17);
 642       }
 643
 644       BEGIN_BATCH(1 + 4*brw->vb.nr_buffers);
 645       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (4*brw->vb.nr_buffers - 1));
 646       for (i = 0; i < brw->vb.nr_buffers; i++) {
 647          struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
 648          uint32_t dw0;
 649
 650          if (intel->gen >= 6) {
 651             dw0 = buffer->step_rate
 652                      ? GEN6_VB0_ACCESS_INSTANCEDATA
 653                      : GEN6_VB0_ACCESS_VERTEXDATA;
 654             dw0 |= i << GEN6_VB0_INDEX_SHIFT;
 655          } else {
 656             dw0 = buffer->step_rate
 657                      ? BRW_VB0_ACCESS_INSTANCEDATA
 658                      : BRW_VB0_ACCESS_VERTEXDATA;
 659             dw0 |= i << BRW_VB0_INDEX_SHIFT;
 660          }
 661
 662          if (intel->gen >= 7)
 663             dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 664
 665          OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
 666          OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
 667          if (intel->gen >= 5) {
 668             OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1);
 669          } else
 670             OUT_BATCH(0);
 671          OUT_BATCH(buffer->step_rate);
 672       }
 673       ADVANCE_BATCH();
 674    }
 675
 676    /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
 677     * for VertexID/InstanceID.
 678     */
 679    if (intel->gen >= 6) {
 680       assert(nr_elements <= 34);
 681    } else {
 682       assert(nr_elements <= 18);
 683    }
 684
 685    struct brw_vertex_element *gen6_edgeflag_input = NULL;
 686
 687    BEGIN_BATCH(1 + nr_elements * 2);
 688    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
 689    for (i = 0; i < brw->vb.nr_enabled; i++) {
 690       struct brw_vertex_element *input = brw->vb.enabled[i];
 691       uint32_t format = get_surface_type(brw, input->glarray);
 692       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
 693       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
 694       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
 695       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
 696
 697       /* The gen4 driver expects edgeflag to come in as a float, and passes
 698        * that float on to the tests in the clipper.  Mesa's current vertex
 699        * attribute value for EdgeFlag is stored as a float, which works out.
 700        * glEdgeFlagPointer, on the other hand, gives us an unnormalized
 701        * integer ubyte.  Just rewrite that to convert to a float.
 702        */
 703       if (input->attrib == VERT_ATTRIB_EDGEFLAG) {
 704          /* Gen6+ passes edgeflag as sideband along with the vertex, instead
 705           * of in the VUE.  We have to upload it sideband as the last vertex
 706           * element according to the B-Spec.
 707           */
 708          if (intel->gen >= 6) {
 709             gen6_edgeflag_input = input;
 710             continue;
 711          }
 712
 713          if (format == BRW_SURFACEFORMAT_R8_UINT)
 714             format = BRW_SURFACEFORMAT_R8_SSCALED;
 715       }
 716
 717       switch (input->glarray->Size) {
 718       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
 719       case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
 720       case 2: comp2 = BRW_VE1_COMPONENT_STORE_0;
 721       case 3: comp3 = input->glarray->Integer ? BRW_VE1_COMPONENT_STORE_1_INT
 722                                               : BRW_VE1_COMPONENT_STORE_1_FLT;
 723          break;
 724       }
 725
 726       if (intel->gen >= 6) {
 727          OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
 728                    GEN6_VE0_VALID |
 729                    (format << BRW_VE0_FORMAT_SHIFT) |
 730                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 731       } else {
 732          OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
 733                    BRW_VE0_VALID |
 734                    (format << BRW_VE0_FORMAT_SHIFT) |
 735                    (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 736       }
 737
 738       if (intel->gen >= 5)
 739           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 740                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 741                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 742                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT));
 743       else
 744           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
 745                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
 746                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
 747                     (comp3 << BRW_VE1_COMPONENT_3_SHIFT) |
 748                     ((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
 749    }
 750
 751    if (intel->gen >= 6 && gen6_edgeflag_input) {
 752       uint32_t format = get_surface_type(brw, gen6_edgeflag_input->glarray);
 753
 754       OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
 755                 GEN6_VE0_VALID |
 756                 GEN6_VE0_EDGE_FLAG_ENABLE |
 757                 (format << BRW_VE0_FORMAT_SHIFT) |
 758                 (gen6_edgeflag_input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
 759       OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT) |
 760                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
 761                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 762                 (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 763    }
 764
 765    if (brw->vs.prog_data->uses_vertexid) {
 766       uint32_t dw0 = 0, dw1 = 0;
 767
 768       dw1 = ((BRW_VE1_COMPONENT_STORE_VID << BRW_VE1_COMPONENT_0_SHIFT) |
 769              (BRW_VE1_COMPONENT_STORE_IID << BRW_VE1_COMPONENT_1_SHIFT) |
 770              (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
 771              (BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
 772
 773       if (intel->gen >= 6) {
 774          dw0 |= GEN6_VE0_VALID;
 775       } else {
 776          dw0 |= BRW_VE0_VALID;
 777          dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
 778       }
 779
 780       /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
 781        * the format is ignored and the value is always int.
 782        */
 783
 784       OUT_BATCH(dw0);
 785       OUT_BATCH(dw1);
 786    }
 787
 788    CACHED_BATCH();
 789 }
 790
 791 const struct brw_tracked_state brw_vertices = {
 792    .dirty = {
 793       .mesa = _NEW_POLYGON,
 794       .brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
 795       .cache = CACHE_NEW_VS_PROG,
 796    },
 797    .emit = brw_emit_vertices,
 798 };
 799
 800 static void brw_upload_indices(struct brw_context *brw)
 801 {
 802    struct gl_context *ctx = &brw->intel.ctx;
 803    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 804    GLuint ib_size;
 805    drm_intel_bo *bo = NULL;
 806    struct gl_buffer_object *bufferobj;
 807    GLuint offset;
 808    GLuint ib_type_size;
 809
 810    if (index_buffer == NULL)
 811       return;
 812
 813    ib_type_size = _mesa_sizeof_type(index_buffer->type);
 814    ib_size = ib_type_size * index_buffer->count;
 815    bufferobj = index_buffer->obj;
 816
 817    /* Turn into a proper VBO:
 818     */
 819    if (!_mesa_is_bufferobj(bufferobj)) {
 820
 821       /* Get new bufferobj, offset:
 822        */
 823       intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
 824                         &bo, &offset);
 825       brw->ib.start_vertex_offset = offset / ib_type_size;
 826    } else {
 827       offset = (GLuint) (unsigned long) index_buffer->ptr;
 828
 829       /* If the index buffer isn't aligned to its element size, we have to
 830        * rebase it into a temporary.
 831        */
 832        if ((ib_type_size - 1) & offset) {
 833           perf_debug("copying index buffer to a temporary to work around "
 834                      "misaligned offset %d\n", offset);
 835
 836           GLubyte *map = ctx->Driver.MapBufferRange(ctx,
 837                                                     offset,
 838                                                     ib_size,
 839                                                     GL_MAP_READ_BIT,
 840                                                     bufferobj);
 841
 842           intel_upload_data(brw, map, ib_size, ib_type_size, &bo, &offset);
 843           brw->ib.start_vertex_offset = offset / ib_type_size;
 844
 845           ctx->Driver.UnmapBuffer(ctx, bufferobj);
 846        } else {
 847           /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading
 848            * the index buffer state when we're just moving the start index
 849            * of our drawing.
 850            */
 851           brw->ib.start_vertex_offset = offset / ib_type_size;
 852
 853           bo = intel_bufferobj_source(brw,
 854                                       intel_buffer_object(bufferobj),
 855                                       ib_type_size,
 856                                       &offset);
 857           drm_intel_bo_reference(bo);
 858
 859           brw->ib.start_vertex_offset += offset / ib_type_size;
 860        }
 861    }
 862
 863    if (brw->ib.bo != bo) {
 864       drm_intel_bo_unreference(brw->ib.bo);
 865       brw->ib.bo = bo;
 866
 867       brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
 868    } else {
 869       drm_intel_bo_unreference(bo);
 870    }
 871
 872    if (index_buffer->type != brw->ib.type) {
 873       brw->ib.type = index_buffer->type;
 874       brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
 875    }
 876 }
 877
 878 const struct brw_tracked_state brw_indices = {
 879    .dirty = {
 880       .mesa = 0,
 881       .brw = BRW_NEW_INDICES,
 882       .cache = 0,
 883    },
 884    .emit = brw_upload_indices,
 885 };
 886
 887 static void brw_emit_index_buffer(struct brw_context *brw)
 888 {
 889    struct intel_context *intel = &brw->intel;
 890    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
 891    GLuint cut_index_setting;
 892
 893    if (index_buffer == NULL)
 894       return;
 895
 896    if (brw->prim_restart.enable_cut_index && !intel->is_haswell) {
 897       cut_index_setting = BRW_CUT_INDEX_ENABLE;
 898    } else {
 899       cut_index_setting = 0;
 900    }
 901
 902    BEGIN_BATCH(3);
 903    OUT_BATCH(CMD_INDEX_BUFFER << 16 |
 904              cut_index_setting |
 905              get_index_type(index_buffer->type) << 8 |
 906              1);
 907    OUT_RELOC(brw->ib.bo,
 908              I915_GEM_DOMAIN_VERTEX, 0,
 909              0);
 910    OUT_RELOC(brw->ib.bo,
 911              I915_GEM_DOMAIN_VERTEX, 0,
 912              brw->ib.bo->size - 1);
 913    ADVANCE_BATCH();
 914 }
 915
 916 const struct brw_tracked_state brw_index_buffer = {
 917    .dirty = {
 918       .mesa = 0,
 919       .brw = BRW_NEW_BATCH | BRW_NEW_INDEX_BUFFER,
 920       .cache = 0,
 921    },
 922    .emit = brw_emit_index_buffer,
 923 };