2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/bufferobj.h"
27 #include "main/context.h"
28 #include "main/enums.h"
29 #include "main/macros.h"
30 #include "main/glformats.h"
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_buffer_objects.h"
40 static const GLuint double_types_float
[5] = {
42 BRW_SURFACEFORMAT_R64_FLOAT
,
43 BRW_SURFACEFORMAT_R64G64_FLOAT
,
44 BRW_SURFACEFORMAT_R64G64B64_FLOAT
,
45 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
48 static const GLuint double_types_passthru
[5] = {
50 BRW_SURFACEFORMAT_R64_PASSTHRU
,
51 BRW_SURFACEFORMAT_R64G64_PASSTHRU
,
52 BRW_SURFACEFORMAT_R64G64B64_PASSTHRU
,
53 BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU
56 static const GLuint float_types
[5] = {
58 BRW_SURFACEFORMAT_R32_FLOAT
,
59 BRW_SURFACEFORMAT_R32G32_FLOAT
,
60 BRW_SURFACEFORMAT_R32G32B32_FLOAT
,
61 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
64 static const GLuint half_float_types
[5] = {
66 BRW_SURFACEFORMAT_R16_FLOAT
,
67 BRW_SURFACEFORMAT_R16G16_FLOAT
,
68 BRW_SURFACEFORMAT_R16G16B16_FLOAT
,
69 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
72 static const GLuint fixed_point_types
[5] = {
74 BRW_SURFACEFORMAT_R32_SFIXED
,
75 BRW_SURFACEFORMAT_R32G32_SFIXED
,
76 BRW_SURFACEFORMAT_R32G32B32_SFIXED
,
77 BRW_SURFACEFORMAT_R32G32B32A32_SFIXED
,
80 static const GLuint uint_types_direct
[5] = {
82 BRW_SURFACEFORMAT_R32_UINT
,
83 BRW_SURFACEFORMAT_R32G32_UINT
,
84 BRW_SURFACEFORMAT_R32G32B32_UINT
,
85 BRW_SURFACEFORMAT_R32G32B32A32_UINT
88 static const GLuint uint_types_norm
[5] = {
90 BRW_SURFACEFORMAT_R32_UNORM
,
91 BRW_SURFACEFORMAT_R32G32_UNORM
,
92 BRW_SURFACEFORMAT_R32G32B32_UNORM
,
93 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
96 static const GLuint uint_types_scale
[5] = {
98 BRW_SURFACEFORMAT_R32_USCALED
,
99 BRW_SURFACEFORMAT_R32G32_USCALED
,
100 BRW_SURFACEFORMAT_R32G32B32_USCALED
,
101 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
104 static const GLuint int_types_direct
[5] = {
106 BRW_SURFACEFORMAT_R32_SINT
,
107 BRW_SURFACEFORMAT_R32G32_SINT
,
108 BRW_SURFACEFORMAT_R32G32B32_SINT
,
109 BRW_SURFACEFORMAT_R32G32B32A32_SINT
112 static const GLuint int_types_norm
[5] = {
114 BRW_SURFACEFORMAT_R32_SNORM
,
115 BRW_SURFACEFORMAT_R32G32_SNORM
,
116 BRW_SURFACEFORMAT_R32G32B32_SNORM
,
117 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
120 static const GLuint int_types_scale
[5] = {
122 BRW_SURFACEFORMAT_R32_SSCALED
,
123 BRW_SURFACEFORMAT_R32G32_SSCALED
,
124 BRW_SURFACEFORMAT_R32G32B32_SSCALED
,
125 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
128 static const GLuint ushort_types_direct
[5] = {
130 BRW_SURFACEFORMAT_R16_UINT
,
131 BRW_SURFACEFORMAT_R16G16_UINT
,
132 BRW_SURFACEFORMAT_R16G16B16_UINT
,
133 BRW_SURFACEFORMAT_R16G16B16A16_UINT
136 static const GLuint ushort_types_norm
[5] = {
138 BRW_SURFACEFORMAT_R16_UNORM
,
139 BRW_SURFACEFORMAT_R16G16_UNORM
,
140 BRW_SURFACEFORMAT_R16G16B16_UNORM
,
141 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
144 static const GLuint ushort_types_scale
[5] = {
146 BRW_SURFACEFORMAT_R16_USCALED
,
147 BRW_SURFACEFORMAT_R16G16_USCALED
,
148 BRW_SURFACEFORMAT_R16G16B16_USCALED
,
149 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
152 static const GLuint short_types_direct
[5] = {
154 BRW_SURFACEFORMAT_R16_SINT
,
155 BRW_SURFACEFORMAT_R16G16_SINT
,
156 BRW_SURFACEFORMAT_R16G16B16_SINT
,
157 BRW_SURFACEFORMAT_R16G16B16A16_SINT
160 static const GLuint short_types_norm
[5] = {
162 BRW_SURFACEFORMAT_R16_SNORM
,
163 BRW_SURFACEFORMAT_R16G16_SNORM
,
164 BRW_SURFACEFORMAT_R16G16B16_SNORM
,
165 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
168 static const GLuint short_types_scale
[5] = {
170 BRW_SURFACEFORMAT_R16_SSCALED
,
171 BRW_SURFACEFORMAT_R16G16_SSCALED
,
172 BRW_SURFACEFORMAT_R16G16B16_SSCALED
,
173 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
176 static const GLuint ubyte_types_direct
[5] = {
178 BRW_SURFACEFORMAT_R8_UINT
,
179 BRW_SURFACEFORMAT_R8G8_UINT
,
180 BRW_SURFACEFORMAT_R8G8B8_UINT
,
181 BRW_SURFACEFORMAT_R8G8B8A8_UINT
184 static const GLuint ubyte_types_norm
[5] = {
186 BRW_SURFACEFORMAT_R8_UNORM
,
187 BRW_SURFACEFORMAT_R8G8_UNORM
,
188 BRW_SURFACEFORMAT_R8G8B8_UNORM
,
189 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
192 static const GLuint ubyte_types_scale
[5] = {
194 BRW_SURFACEFORMAT_R8_USCALED
,
195 BRW_SURFACEFORMAT_R8G8_USCALED
,
196 BRW_SURFACEFORMAT_R8G8B8_USCALED
,
197 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
200 static const GLuint byte_types_direct
[5] = {
202 BRW_SURFACEFORMAT_R8_SINT
,
203 BRW_SURFACEFORMAT_R8G8_SINT
,
204 BRW_SURFACEFORMAT_R8G8B8_SINT
,
205 BRW_SURFACEFORMAT_R8G8B8A8_SINT
208 static const GLuint byte_types_norm
[5] = {
210 BRW_SURFACEFORMAT_R8_SNORM
,
211 BRW_SURFACEFORMAT_R8G8_SNORM
,
212 BRW_SURFACEFORMAT_R8G8B8_SNORM
,
213 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
216 static const GLuint byte_types_scale
[5] = {
218 BRW_SURFACEFORMAT_R8_SSCALED
,
219 BRW_SURFACEFORMAT_R8G8_SSCALED
,
220 BRW_SURFACEFORMAT_R8G8B8_SSCALED
,
221 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
225 double_types(struct brw_context
*brw
,
229 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
230 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
231 * 64-bit components are stored in the URB without any conversion."
232 * Also included on BDW PRM, Volume 7, page 470, table "Source Element
233 * Formats Supported in VF Unit"
234 * Previous PRMs don't include those references.
236 return (brw
->gen
>= 8 && doubles
237 ? double_types_passthru
[size
]
238 : double_types_float
[size
]);
242 * Given vertex array type/size/format/normalized info, return
243 * the appopriate hardware surface type.
244 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
247 brw_get_vertex_surface_type(struct brw_context
*brw
,
248 const struct gl_vertex_array
*glarray
)
250 int size
= glarray
->Size
;
251 const bool is_ivybridge_or_older
=
252 brw
->gen
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
;
254 if (unlikely(INTEL_DEBUG
& DEBUG_VERTS
))
255 fprintf(stderr
, "type %s size %d normalized %d\n",
256 _mesa_enum_to_string(glarray
->Type
),
257 glarray
->Size
, glarray
->Normalized
);
259 if (glarray
->Integer
) {
260 assert(glarray
->Format
== GL_RGBA
); /* sanity check */
261 switch (glarray
->Type
) {
262 case GL_INT
: return int_types_direct
[size
];
264 if (is_ivybridge_or_older
&& size
== 3)
265 return short_types_direct
[4];
267 return short_types_direct
[size
];
269 if (is_ivybridge_or_older
&& size
== 3)
270 return byte_types_direct
[4];
272 return byte_types_direct
[size
];
273 case GL_UNSIGNED_INT
: return uint_types_direct
[size
];
274 case GL_UNSIGNED_SHORT
:
275 if (is_ivybridge_or_older
&& size
== 3)
276 return ushort_types_direct
[4];
278 return ushort_types_direct
[size
];
279 case GL_UNSIGNED_BYTE
:
280 if (is_ivybridge_or_older
&& size
== 3)
281 return ubyte_types_direct
[4];
283 return ubyte_types_direct
[size
];
284 default: unreachable("not reached");
286 } else if (glarray
->Type
== GL_UNSIGNED_INT_10F_11F_11F_REV
) {
287 return BRW_SURFACEFORMAT_R11G11B10_FLOAT
;
288 } else if (glarray
->Normalized
) {
289 switch (glarray
->Type
) {
290 case GL_DOUBLE
: return double_types(brw
, size
, glarray
->Doubles
);
291 case GL_FLOAT
: return float_types
[size
];
293 case GL_HALF_FLOAT_OES
:
294 if (brw
->gen
< 6 && size
== 3)
295 return half_float_types
[4];
297 return half_float_types
[size
];
298 case GL_INT
: return int_types_norm
[size
];
299 case GL_SHORT
: return short_types_norm
[size
];
300 case GL_BYTE
: return byte_types_norm
[size
];
301 case GL_UNSIGNED_INT
: return uint_types_norm
[size
];
302 case GL_UNSIGNED_SHORT
: return ushort_types_norm
[size
];
303 case GL_UNSIGNED_BYTE
:
304 if (glarray
->Format
== GL_BGRA
) {
305 /* See GL_EXT_vertex_array_bgra */
307 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
310 return ubyte_types_norm
[size
];
313 if (brw
->gen
>= 8 || brw
->is_haswell
)
314 return fixed_point_types
[size
];
316 /* This produces GL_FIXED inputs as values between INT32_MIN and
317 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
319 return int_types_scale
[size
];
320 /* See GL_ARB_vertex_type_2_10_10_10_rev.
321 * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
322 * like to use here, so upload everything as UINT and fix
325 case GL_INT_2_10_10_10_REV
:
327 if (brw
->gen
>= 8 || brw
->is_haswell
) {
328 return glarray
->Format
== GL_BGRA
329 ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
330 : BRW_SURFACEFORMAT_R10G10B10A2_SNORM
;
332 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
333 case GL_UNSIGNED_INT_2_10_10_10_REV
:
335 if (brw
->gen
>= 8 || brw
->is_haswell
) {
336 return glarray
->Format
== GL_BGRA
337 ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
338 : BRW_SURFACEFORMAT_R10G10B10A2_UNORM
;
340 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
341 default: unreachable("not reached");
345 /* See GL_ARB_vertex_type_2_10_10_10_rev.
346 * W/A: the hardware doesn't really support the formats we'd
347 * like to use here, so upload everything as UINT and fix
350 if (glarray
->Type
== GL_INT_2_10_10_10_REV
) {
352 if (brw
->gen
>= 8 || brw
->is_haswell
) {
353 return glarray
->Format
== GL_BGRA
354 ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
355 : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED
;
357 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
358 } else if (glarray
->Type
== GL_UNSIGNED_INT_2_10_10_10_REV
) {
360 if (brw
->gen
>= 8 || brw
->is_haswell
) {
361 return glarray
->Format
== GL_BGRA
362 ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
363 : BRW_SURFACEFORMAT_R10G10B10A2_USCALED
;
365 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
367 assert(glarray
->Format
== GL_RGBA
); /* sanity check */
368 switch (glarray
->Type
) {
369 case GL_DOUBLE
: return double_types(brw
, size
, glarray
->Doubles
);
370 case GL_FLOAT
: return float_types
[size
];
372 case GL_HALF_FLOAT_OES
:
373 if (brw
->gen
< 6 && size
== 3)
374 return half_float_types
[4];
376 return half_float_types
[size
];
377 case GL_INT
: return int_types_scale
[size
];
378 case GL_SHORT
: return short_types_scale
[size
];
379 case GL_BYTE
: return byte_types_scale
[size
];
380 case GL_UNSIGNED_INT
: return uint_types_scale
[size
];
381 case GL_UNSIGNED_SHORT
: return ushort_types_scale
[size
];
382 case GL_UNSIGNED_BYTE
: return ubyte_types_scale
[size
];
384 if (brw
->gen
>= 8 || brw
->is_haswell
)
385 return fixed_point_types
[size
];
387 /* This produces GL_FIXED inputs as values between INT32_MIN and
388 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
390 return int_types_scale
[size
];
391 default: unreachable("not reached");
397 copy_array_to_vbo_array(struct brw_context
*brw
,
398 struct brw_vertex_element
*element
,
400 struct brw_vertex_buffer
*buffer
,
403 const int src_stride
= element
->glarray
->StrideB
;
405 /* If the source stride is zero, we just want to upload the current
406 * attribute once and set the buffer's stride to 0. There's no need
407 * to replicate it out.
409 if (src_stride
== 0) {
410 intel_upload_data(brw
, element
->glarray
->Ptr
,
411 element
->glarray
->_ElementSize
,
412 element
->glarray
->_ElementSize
,
413 &buffer
->bo
, &buffer
->offset
);
416 buffer
->size
= element
->glarray
->_ElementSize
;
420 const unsigned char *src
= element
->glarray
->Ptr
+ min
* src_stride
;
421 int count
= max
- min
+ 1;
422 GLuint size
= count
* dst_stride
;
423 uint8_t *dst
= intel_upload_space(brw
, size
, dst_stride
,
424 &buffer
->bo
, &buffer
->offset
);
426 /* The GL 4.5 spec says:
427 * "If any enabled array’s buffer binding is zero when DrawArrays or
428 * one of the other drawing commands defined in section 10.4 is called,
429 * the result is undefined."
431 * In this case, let's the dst with undefined values
434 if (dst_stride
== src_stride
) {
435 memcpy(dst
, src
, size
);
438 memcpy(dst
, src
, dst_stride
);
444 buffer
->stride
= dst_stride
;
449 brw_prepare_vertices(struct brw_context
*brw
)
451 struct gl_context
*ctx
= &brw
->ctx
;
452 /* BRW_NEW_VS_PROG_DATA */
453 const struct brw_vs_prog_data
*vs_prog_data
=
454 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
455 GLbitfield64 vs_inputs
= vs_prog_data
->inputs_read
;
456 const unsigned char *ptr
= NULL
;
457 GLuint interleaved
= 0;
458 unsigned int min_index
= brw
->vb
.min_index
+ brw
->basevertex
;
459 unsigned int max_index
= brw
->vb
.max_index
+ brw
->basevertex
;
463 struct brw_vertex_element
*upload
[VERT_ATTRIB_MAX
];
464 GLuint nr_uploads
= 0;
468 * On gen6+, edge flags don't end up in the VUE (either in or out of the
469 * VS). Instead, they're uploaded as the last vertex element, and the data
470 * is passed sideband through the fixed function units. So, we need to
471 * prepare the vertex buffer for it, but it's not present in inputs_read.
473 if (brw
->gen
>= 6 && (ctx
->Polygon
.FrontMode
!= GL_FILL
||
474 ctx
->Polygon
.BackMode
!= GL_FILL
)) {
475 vs_inputs
|= VERT_BIT_EDGEFLAG
;
479 fprintf(stderr
, "%s %d..%d\n", __func__
, min_index
, max_index
);
481 /* Accumulate the list of enabled arrays. */
482 brw
->vb
.nr_enabled
= 0;
484 GLuint index
= ffsll(vs_inputs
) - 1;
485 struct brw_vertex_element
*input
= &brw
->vb
.inputs
[index
];
486 input
->is_dual_slot
= brw
->gen
>= 8 &&
487 (vs_prog_data
->double_inputs_read
& BITFIELD64_BIT(index
)) != 0;
488 vs_inputs
&= ~BITFIELD64_BIT(index
);
489 brw
->vb
.enabled
[brw
->vb
.nr_enabled
++] = input
;
492 if (brw
->vb
.nr_enabled
== 0)
495 if (brw
->vb
.nr_buffers
)
498 /* The range of data in a given buffer represented as [min, max) */
499 struct intel_buffer_object
*enabled_buffer
[VERT_ATTRIB_MAX
];
500 uint32_t buffer_range_start
[VERT_ATTRIB_MAX
];
501 uint32_t buffer_range_end
[VERT_ATTRIB_MAX
];
503 for (i
= j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
504 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
505 const struct gl_vertex_array
*glarray
= input
->glarray
;
507 if (_mesa_is_bufferobj(glarray
->BufferObj
)) {
508 struct intel_buffer_object
*intel_buffer
=
509 intel_buffer_object(glarray
->BufferObj
);
511 const uint32_t offset
= (uintptr_t)glarray
->Ptr
;
513 /* Start with the worst case */
515 uint32_t range
= intel_buffer
->Base
.Size
;
516 if (glarray
->InstanceDivisor
) {
517 if (brw
->num_instances
) {
518 start
= offset
+ glarray
->StrideB
* brw
->baseinstance
;
519 range
= (glarray
->StrideB
* ((brw
->num_instances
- 1) /
520 glarray
->InstanceDivisor
) +
521 glarray
->_ElementSize
);
524 if (brw
->vb
.index_bounds_valid
) {
525 start
= offset
+ min_index
* glarray
->StrideB
;
526 range
= (glarray
->StrideB
* (max_index
- min_index
) +
527 glarray
->_ElementSize
);
531 /* If we have a VB set to be uploaded for this buffer object
532 * already, reuse that VB state so that we emit fewer
536 for (k
= 0; k
< i
; k
++) {
537 const struct gl_vertex_array
*other
= brw
->vb
.enabled
[k
]->glarray
;
538 if (glarray
->BufferObj
== other
->BufferObj
&&
539 glarray
->StrideB
== other
->StrideB
&&
540 glarray
->InstanceDivisor
== other
->InstanceDivisor
&&
541 (uintptr_t)(glarray
->Ptr
- other
->Ptr
) < glarray
->StrideB
)
543 input
->buffer
= brw
->vb
.enabled
[k
]->buffer
;
544 input
->offset
= glarray
->Ptr
- other
->Ptr
;
546 buffer_range_start
[input
->buffer
] =
547 MIN2(buffer_range_start
[input
->buffer
], start
);
548 buffer_range_end
[input
->buffer
] =
549 MAX2(buffer_range_end
[input
->buffer
], start
+ range
);
554 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
556 /* Named buffer object: Just reference its contents directly. */
557 buffer
->offset
= offset
;
558 buffer
->stride
= glarray
->StrideB
;
559 buffer
->step_rate
= glarray
->InstanceDivisor
;
560 buffer
->size
= glarray
->BufferObj
->Size
- offset
;
562 enabled_buffer
[j
] = intel_buffer
;
563 buffer_range_start
[j
] = start
;
564 buffer_range_end
[j
] = start
+ range
;
570 /* Queue the buffer object up to be uploaded in the next pass,
571 * when we've decided if we're doing interleaved or not.
573 if (nr_uploads
== 0) {
574 interleaved
= glarray
->StrideB
;
577 else if (interleaved
!= glarray
->StrideB
||
578 glarray
->Ptr
< ptr
||
579 (uintptr_t)(glarray
->Ptr
- ptr
) + glarray
->_ElementSize
> interleaved
)
581 /* If our stride is different from the first attribute's stride,
582 * or if the first attribute's stride didn't cover our element,
583 * disable the interleaved upload optimization. The second case
584 * can most commonly occur in cases where there is a single vertex
585 * and, for example, the data is stored on the application's
588 * NOTE: This will also disable the optimization in cases where
589 * the data is in a different order than the array indices.
593 * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
594 * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
599 upload
[nr_uploads
++] = input
;
603 /* Now that we've set up all of the buffers, we walk through and reference
604 * each of them. We do this late so that we get the right size in each
605 * buffer and don't reference too little data.
607 for (i
= 0; i
< j
; i
++) {
608 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
612 const uint32_t start
= buffer_range_start
[i
];
613 const uint32_t range
= buffer_range_end
[i
] - buffer_range_start
[i
];
615 buffer
->bo
= intel_bufferobj_buffer(brw
, enabled_buffer
[i
], start
, range
);
616 drm_intel_bo_reference(buffer
->bo
);
619 /* If we need to upload all the arrays, then we can trim those arrays to
620 * only the used elements [min_index, max_index] so long as we adjust all
621 * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
623 brw
->vb
.start_vertex_bias
= 0;
625 if (nr_uploads
== brw
->vb
.nr_enabled
) {
626 brw
->vb
.start_vertex_bias
= -delta
;
630 /* Handle any arrays to be uploaded. */
631 if (nr_uploads
> 1) {
633 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
634 /* All uploads are interleaved, so upload the arrays together as
635 * interleaved. First, upload the contents and set up upload[0].
637 copy_array_to_vbo_array(brw
, upload
[0], min_index
, max_index
,
638 buffer
, interleaved
);
639 buffer
->offset
-= delta
* interleaved
;
640 buffer
->size
+= delta
* interleaved
;
642 for (i
= 0; i
< nr_uploads
; i
++) {
643 /* Then, just point upload[i] at upload[0]'s buffer. */
645 ((const unsigned char *)upload
[i
]->glarray
->Ptr
- ptr
);
646 upload
[i
]->buffer
= j
;
653 /* Upload non-interleaved arrays */
654 for (i
= 0; i
< nr_uploads
; i
++) {
655 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
656 if (upload
[i
]->glarray
->InstanceDivisor
== 0) {
657 copy_array_to_vbo_array(brw
, upload
[i
], min_index
, max_index
,
658 buffer
, upload
[i
]->glarray
->_ElementSize
);
660 /* This is an instanced attribute, since its InstanceDivisor
661 * is not zero. Therefore, its data will be stepped after the
662 * instanced draw has been run InstanceDivisor times.
664 uint32_t instanced_attr_max_index
=
665 (brw
->num_instances
- 1) / upload
[i
]->glarray
->InstanceDivisor
;
666 copy_array_to_vbo_array(brw
, upload
[i
], 0, instanced_attr_max_index
,
667 buffer
, upload
[i
]->glarray
->_ElementSize
);
669 buffer
->offset
-= delta
* buffer
->stride
;
670 buffer
->size
+= delta
* buffer
->stride
;
671 buffer
->step_rate
= upload
[i
]->glarray
->InstanceDivisor
;
672 upload
[i
]->buffer
= j
++;
673 upload
[i
]->offset
= 0;
676 brw
->vb
.nr_buffers
= j
;
680 brw_prepare_shader_draw_parameters(struct brw_context
*brw
)
682 const struct brw_vs_prog_data
*vs_prog_data
=
683 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
685 /* For non-indirect draws, upload gl_BaseVertex. */
686 if ((vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) &&
687 brw
->draw
.draw_params_bo
== NULL
) {
688 intel_upload_data(brw
, &brw
->draw
.params
, sizeof(brw
->draw
.params
), 4,
689 &brw
->draw
.draw_params_bo
,
690 &brw
->draw
.draw_params_offset
);
693 if (vs_prog_data
->uses_drawid
) {
694 intel_upload_data(brw
, &brw
->draw
.gl_drawid
, sizeof(brw
->draw
.gl_drawid
), 4,
695 &brw
->draw
.draw_id_bo
,
696 &brw
->draw
.draw_id_offset
);
701 * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
704 brw_emit_vertex_buffer_state(struct brw_context
*brw
,
707 unsigned start_offset
,
713 struct gl_context
*ctx
= &brw
->ctx
;
717 dw0
= buffer_nr
<< GEN6_VB0_INDEX_SHIFT
;
718 } else if (brw
->gen
>= 6) {
719 dw0
= (buffer_nr
<< GEN6_VB0_INDEX_SHIFT
) |
720 (step_rate
? GEN6_VB0_ACCESS_INSTANCEDATA
721 : GEN6_VB0_ACCESS_VERTEXDATA
);
723 dw0
= (buffer_nr
<< BRW_VB0_INDEX_SHIFT
) |
724 (step_rate
? BRW_VB0_ACCESS_INSTANCEDATA
725 : BRW_VB0_ACCESS_VERTEXDATA
);
729 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
733 dw0
|= GEN7_MOCS_L3
<< 16;
736 dw0
|= BDW_MOCS_WB
<< 16;
739 dw0
|= SKL_MOCS_WB
<< 16;
743 WARN_ONCE(stride
>= (brw
->gen
>= 5 ? 2048 : 2047),
744 "VBO stride %d too large, bad rendering may occur\n",
746 OUT_BATCH(dw0
| (stride
<< BRW_VB0_PITCH_SHIFT
));
748 OUT_RELOC64(bo
, I915_GEM_DOMAIN_VERTEX
, 0, start_offset
);
749 /* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
750 * Vertex Fetch (VF) Stage - State
752 * Instead of "VBState.StartingBufferAddress + VBState.MaxIndex x
753 * VBState.BufferPitch", the address of the byte immediately beyond the
754 * last valid byte of the buffer is determined by
755 * "VBState.StartingBufferAddress + VBState.BufferSize".
757 OUT_BATCH(end_offset
- start_offset
);
758 } else if (brw
->gen
>= 5) {
759 OUT_RELOC(bo
, I915_GEM_DOMAIN_VERTEX
, 0, start_offset
);
760 /* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
761 * Vertex Fetch (VF) Stage - State
763 * Instead of "VBState.StartingBufferAddress + VBState.MaxIndex x
764 * VBState.BufferPitch", the address of the byte immediately beyond the
765 * last valid byte of the buffer is determined by
766 * "VBState.EndAddress + 1".
768 OUT_RELOC(bo
, I915_GEM_DOMAIN_VERTEX
, 0, end_offset
- 1);
769 OUT_BATCH(step_rate
);
771 OUT_RELOC(bo
, I915_GEM_DOMAIN_VERTEX
, 0, start_offset
);
773 OUT_BATCH(step_rate
);
780 brw_emit_vertices(struct brw_context
*brw
)
784 brw_prepare_vertices(brw
);
785 brw_prepare_shader_draw_parameters(brw
);
787 brw_emit_query_begin(brw
);
789 const struct brw_vs_prog_data
*vs_prog_data
=
790 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
792 unsigned nr_elements
= brw
->vb
.nr_enabled
;
793 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
794 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
796 if (vs_prog_data
->uses_drawid
)
799 /* If the VS doesn't read any inputs (calculating vertex position from
800 * a state variable for some reason, for example), emit a single pad
801 * VERTEX_ELEMENT struct and bail.
803 * The stale VB state stays in place, but they don't do anything unless
804 * a VE loads from them.
806 if (nr_elements
== 0) {
808 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | 1);
810 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT
) |
812 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
813 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
815 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT
) |
817 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
818 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
820 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
821 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
822 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
823 (BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
));
828 /* Now emit VB and VEP state packets.
831 const bool uses_draw_params
=
832 vs_prog_data
->uses_basevertex
||
833 vs_prog_data
->uses_baseinstance
;
834 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
835 uses_draw_params
+ vs_prog_data
->uses_drawid
;
839 assert(nr_buffers
<= 33);
841 assert(nr_buffers
<= 17);
844 BEGIN_BATCH(1 + 4 * nr_buffers
);
845 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (4 * nr_buffers
- 1));
846 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
847 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
848 /* Prior to Haswell and Bay Trail we have to use 4-component formats
849 * to fake 3-component ones. In particular, we do this for
850 * half-float and 8 and 16-bit integer formats. This means that the
851 * vertex element may poke over the end of the buffer by 2 bytes.
854 (brw
->gen
<= 7 && !brw
->is_baytrail
&& !brw
->is_haswell
) * 2;
855 EMIT_VERTEX_BUFFER_STATE(brw
, i
, buffer
->bo
, buffer
->offset
,
856 buffer
->offset
+ buffer
->size
+ padding
,
857 buffer
->stride
, buffer
->step_rate
);
861 if (uses_draw_params
) {
862 EMIT_VERTEX_BUFFER_STATE(brw
, brw
->vb
.nr_buffers
,
863 brw
->draw
.draw_params_bo
,
864 brw
->draw
.draw_params_offset
,
865 brw
->draw
.draw_params_bo
->size
,
870 if (vs_prog_data
->uses_drawid
) {
871 EMIT_VERTEX_BUFFER_STATE(brw
, brw
->vb
.nr_buffers
+ 1,
872 brw
->draw
.draw_id_bo
,
873 brw
->draw
.draw_id_offset
,
874 brw
->draw
.draw_id_bo
->size
,
882 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
883 * for VertexID/InstanceID.
886 assert(nr_elements
<= 34);
888 assert(nr_elements
<= 18);
891 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
893 BEGIN_BATCH(1 + nr_elements
* 2);
894 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (2 * nr_elements
- 1));
895 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
896 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
897 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
898 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
899 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
900 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_SRC
;
901 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_SRC
;
903 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
904 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
905 * of in the VUE. We have to upload it sideband as the last vertex
906 * element according to the B-Spec.
909 gen6_edgeflag_input
= input
;
914 switch (input
->glarray
->Size
) {
915 case 0: comp0
= BRW_VE1_COMPONENT_STORE_0
;
916 case 1: comp1
= BRW_VE1_COMPONENT_STORE_0
;
917 case 2: comp2
= BRW_VE1_COMPONENT_STORE_0
;
918 case 3: comp3
= input
->glarray
->Integer
? BRW_VE1_COMPONENT_STORE_1_INT
919 : BRW_VE1_COMPONENT_STORE_1_FLT
;
924 OUT_BATCH((input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
926 (format
<< BRW_VE0_FORMAT_SHIFT
) |
927 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
929 OUT_BATCH((input
->buffer
<< BRW_VE0_INDEX_SHIFT
) |
931 (format
<< BRW_VE0_FORMAT_SHIFT
) |
932 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
936 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
937 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
938 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
939 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
));
941 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
942 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
943 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
944 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
) |
945 ((i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
));
948 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
949 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
950 uint32_t dw0
= 0, dw1
= 0;
951 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_0
;
952 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_0
;
953 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_0
;
954 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_0
;
956 if (vs_prog_data
->uses_basevertex
)
957 comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
959 if (vs_prog_data
->uses_baseinstance
)
960 comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
962 if (vs_prog_data
->uses_vertexid
)
963 comp2
= BRW_VE1_COMPONENT_STORE_VID
;
965 if (vs_prog_data
->uses_instanceid
)
966 comp3
= BRW_VE1_COMPONENT_STORE_IID
;
968 dw1
= (comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
969 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
970 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
971 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
);
974 dw0
|= GEN6_VE0_VALID
|
975 brw
->vb
.nr_buffers
<< GEN6_VE0_INDEX_SHIFT
|
976 BRW_SURFACEFORMAT_R32G32_UINT
<< BRW_VE0_FORMAT_SHIFT
;
978 dw0
|= BRW_VE0_VALID
|
979 brw
->vb
.nr_buffers
<< BRW_VE0_INDEX_SHIFT
|
980 BRW_SURFACEFORMAT_R32G32_UINT
<< BRW_VE0_FORMAT_SHIFT
;
981 dw1
|= (i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
;
984 /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
985 * the format is ignored and the value is always int.
992 if (vs_prog_data
->uses_drawid
) {
993 uint32_t dw0
= 0, dw1
= 0;
995 dw1
= (BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
996 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
997 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
998 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
);
1000 if (brw
->gen
>= 6) {
1001 dw0
|= GEN6_VE0_VALID
|
1002 ((brw
->vb
.nr_buffers
+ 1) << GEN6_VE0_INDEX_SHIFT
) |
1003 (BRW_SURFACEFORMAT_R32_UINT
<< BRW_VE0_FORMAT_SHIFT
);
1005 dw0
|= BRW_VE0_VALID
|
1006 ((brw
->vb
.nr_buffers
+ 1) << BRW_VE0_INDEX_SHIFT
) |
1007 (BRW_SURFACEFORMAT_R32_UINT
<< BRW_VE0_FORMAT_SHIFT
);
1009 dw1
|= (i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
;
1016 if (brw
->gen
>= 6 && gen6_edgeflag_input
) {
1018 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
1020 OUT_BATCH((gen6_edgeflag_input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
1022 GEN6_VE0_EDGE_FLAG_ENABLE
|
1023 (format
<< BRW_VE0_FORMAT_SHIFT
) |
1024 (gen6_edgeflag_input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
1025 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
1026 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
1027 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
1028 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
));
1034 const struct brw_tracked_state brw_vertices
= {
1036 .mesa
= _NEW_POLYGON
,
1037 .brw
= BRW_NEW_BATCH
|
1040 BRW_NEW_VS_PROG_DATA
,
1042 .emit
= brw_emit_vertices
,
1046 brw_upload_indices(struct brw_context
*brw
)
1048 struct gl_context
*ctx
= &brw
->ctx
;
1049 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
1051 drm_intel_bo
*old_bo
= brw
->ib
.bo
;
1052 struct gl_buffer_object
*bufferobj
;
1054 GLuint ib_type_size
;
1056 if (index_buffer
== NULL
)
1059 ib_type_size
= _mesa_sizeof_type(index_buffer
->type
);
1060 ib_size
= index_buffer
->count
? ib_type_size
* index_buffer
->count
:
1061 index_buffer
->obj
->Size
;
1062 bufferobj
= index_buffer
->obj
;
1064 /* Turn into a proper VBO:
1066 if (!_mesa_is_bufferobj(bufferobj
)) {
1067 /* Get new bufferobj, offset:
1069 intel_upload_data(brw
, index_buffer
->ptr
, ib_size
, ib_type_size
,
1070 &brw
->ib
.bo
, &offset
);
1071 brw
->ib
.size
= brw
->ib
.bo
->size
;
1073 offset
= (GLuint
) (unsigned long) index_buffer
->ptr
;
1075 /* If the index buffer isn't aligned to its element size, we have to
1076 * rebase it into a temporary.
1078 if ((ib_type_size
- 1) & offset
) {
1079 perf_debug("copying index buffer to a temporary to work around "
1080 "misaligned offset %d\n", offset
);
1082 GLubyte
*map
= ctx
->Driver
.MapBufferRange(ctx
,
1089 intel_upload_data(brw
, map
, ib_size
, ib_type_size
,
1090 &brw
->ib
.bo
, &offset
);
1091 brw
->ib
.size
= brw
->ib
.bo
->size
;
1093 ctx
->Driver
.UnmapBuffer(ctx
, bufferobj
, MAP_INTERNAL
);
1096 intel_bufferobj_buffer(brw
, intel_buffer_object(bufferobj
),
1098 if (bo
!= brw
->ib
.bo
) {
1099 drm_intel_bo_unreference(brw
->ib
.bo
);
1101 brw
->ib
.size
= bufferobj
->Size
;
1102 drm_intel_bo_reference(bo
);
1107 /* Use 3DPRIMITIVE's start_vertex_offset to avoid re-uploading
1108 * the index buffer state when we're just moving the start index
1111 brw
->ib
.start_vertex_offset
= offset
/ ib_type_size
;
1113 if (brw
->ib
.bo
!= old_bo
)
1114 brw
->ctx
.NewDriverState
|= BRW_NEW_INDEX_BUFFER
;
1116 if (index_buffer
->type
!= brw
->ib
.type
) {
1117 brw
->ib
.type
= index_buffer
->type
;
1118 brw
->ctx
.NewDriverState
|= BRW_NEW_INDEX_BUFFER
;
1122 const struct brw_tracked_state brw_indices
= {
1125 .brw
= BRW_NEW_BLORP
|
1128 .emit
= brw_upload_indices
,
1132 brw_emit_index_buffer(struct brw_context
*brw
)
1134 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
1135 GLuint cut_index_setting
;
1137 if (index_buffer
== NULL
)
1140 if (brw
->prim_restart
.enable_cut_index
&& !brw
->is_haswell
) {
1141 cut_index_setting
= BRW_CUT_INDEX_ENABLE
;
1143 cut_index_setting
= 0;
1147 OUT_BATCH(CMD_INDEX_BUFFER
<< 16 |
1149 brw_get_index_type(index_buffer
->type
) |
1151 OUT_RELOC(brw
->ib
.bo
,
1152 I915_GEM_DOMAIN_VERTEX
, 0,
1154 OUT_RELOC(brw
->ib
.bo
,
1155 I915_GEM_DOMAIN_VERTEX
, 0,
1160 const struct brw_tracked_state brw_index_buffer
= {
1163 .brw
= BRW_NEW_BATCH
|
1165 BRW_NEW_INDEX_BUFFER
,
1167 .emit
= brw_emit_index_buffer
,