2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/bufferobj.h"
27 #include "main/context.h"
28 #include "main/enums.h"
29 #include "main/macros.h"
30 #include "main/glformats.h"
33 #include "brw_defines.h"
34 #include "brw_context.h"
35 #include "brw_state.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_buffer_objects.h"
40 static const GLuint double_types_float
[5] = {
42 BRW_SURFACEFORMAT_R64_FLOAT
,
43 BRW_SURFACEFORMAT_R64G64_FLOAT
,
44 BRW_SURFACEFORMAT_R64G64B64_FLOAT
,
45 BRW_SURFACEFORMAT_R64G64B64A64_FLOAT
48 static const GLuint double_types_passthru
[5] = {
50 BRW_SURFACEFORMAT_R64_PASSTHRU
,
51 BRW_SURFACEFORMAT_R64G64_PASSTHRU
,
52 BRW_SURFACEFORMAT_R64G64B64_PASSTHRU
,
53 BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU
56 static const GLuint float_types
[5] = {
58 BRW_SURFACEFORMAT_R32_FLOAT
,
59 BRW_SURFACEFORMAT_R32G32_FLOAT
,
60 BRW_SURFACEFORMAT_R32G32B32_FLOAT
,
61 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
64 static const GLuint half_float_types
[5] = {
66 BRW_SURFACEFORMAT_R16_FLOAT
,
67 BRW_SURFACEFORMAT_R16G16_FLOAT
,
68 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
,
69 BRW_SURFACEFORMAT_R16G16B16A16_FLOAT
72 static const GLuint fixed_point_types
[5] = {
74 BRW_SURFACEFORMAT_R32_SFIXED
,
75 BRW_SURFACEFORMAT_R32G32_SFIXED
,
76 BRW_SURFACEFORMAT_R32G32B32_SFIXED
,
77 BRW_SURFACEFORMAT_R32G32B32A32_SFIXED
,
80 static const GLuint uint_types_direct
[5] = {
82 BRW_SURFACEFORMAT_R32_UINT
,
83 BRW_SURFACEFORMAT_R32G32_UINT
,
84 BRW_SURFACEFORMAT_R32G32B32_UINT
,
85 BRW_SURFACEFORMAT_R32G32B32A32_UINT
88 static const GLuint uint_types_norm
[5] = {
90 BRW_SURFACEFORMAT_R32_UNORM
,
91 BRW_SURFACEFORMAT_R32G32_UNORM
,
92 BRW_SURFACEFORMAT_R32G32B32_UNORM
,
93 BRW_SURFACEFORMAT_R32G32B32A32_UNORM
96 static const GLuint uint_types_scale
[5] = {
98 BRW_SURFACEFORMAT_R32_USCALED
,
99 BRW_SURFACEFORMAT_R32G32_USCALED
,
100 BRW_SURFACEFORMAT_R32G32B32_USCALED
,
101 BRW_SURFACEFORMAT_R32G32B32A32_USCALED
104 static const GLuint int_types_direct
[5] = {
106 BRW_SURFACEFORMAT_R32_SINT
,
107 BRW_SURFACEFORMAT_R32G32_SINT
,
108 BRW_SURFACEFORMAT_R32G32B32_SINT
,
109 BRW_SURFACEFORMAT_R32G32B32A32_SINT
112 static const GLuint int_types_norm
[5] = {
114 BRW_SURFACEFORMAT_R32_SNORM
,
115 BRW_SURFACEFORMAT_R32G32_SNORM
,
116 BRW_SURFACEFORMAT_R32G32B32_SNORM
,
117 BRW_SURFACEFORMAT_R32G32B32A32_SNORM
120 static const GLuint int_types_scale
[5] = {
122 BRW_SURFACEFORMAT_R32_SSCALED
,
123 BRW_SURFACEFORMAT_R32G32_SSCALED
,
124 BRW_SURFACEFORMAT_R32G32B32_SSCALED
,
125 BRW_SURFACEFORMAT_R32G32B32A32_SSCALED
128 static const GLuint ushort_types_direct
[5] = {
130 BRW_SURFACEFORMAT_R16_UINT
,
131 BRW_SURFACEFORMAT_R16G16_UINT
,
132 BRW_SURFACEFORMAT_R16G16B16A16_UINT
,
133 BRW_SURFACEFORMAT_R16G16B16A16_UINT
136 static const GLuint ushort_types_norm
[5] = {
138 BRW_SURFACEFORMAT_R16_UNORM
,
139 BRW_SURFACEFORMAT_R16G16_UNORM
,
140 BRW_SURFACEFORMAT_R16G16B16_UNORM
,
141 BRW_SURFACEFORMAT_R16G16B16A16_UNORM
144 static const GLuint ushort_types_scale
[5] = {
146 BRW_SURFACEFORMAT_R16_USCALED
,
147 BRW_SURFACEFORMAT_R16G16_USCALED
,
148 BRW_SURFACEFORMAT_R16G16B16_USCALED
,
149 BRW_SURFACEFORMAT_R16G16B16A16_USCALED
152 static const GLuint short_types_direct
[5] = {
154 BRW_SURFACEFORMAT_R16_SINT
,
155 BRW_SURFACEFORMAT_R16G16_SINT
,
156 BRW_SURFACEFORMAT_R16G16B16A16_SINT
,
157 BRW_SURFACEFORMAT_R16G16B16A16_SINT
160 static const GLuint short_types_norm
[5] = {
162 BRW_SURFACEFORMAT_R16_SNORM
,
163 BRW_SURFACEFORMAT_R16G16_SNORM
,
164 BRW_SURFACEFORMAT_R16G16B16_SNORM
,
165 BRW_SURFACEFORMAT_R16G16B16A16_SNORM
168 static const GLuint short_types_scale
[5] = {
170 BRW_SURFACEFORMAT_R16_SSCALED
,
171 BRW_SURFACEFORMAT_R16G16_SSCALED
,
172 BRW_SURFACEFORMAT_R16G16B16_SSCALED
,
173 BRW_SURFACEFORMAT_R16G16B16A16_SSCALED
176 static const GLuint ubyte_types_direct
[5] = {
178 BRW_SURFACEFORMAT_R8_UINT
,
179 BRW_SURFACEFORMAT_R8G8_UINT
,
180 BRW_SURFACEFORMAT_R8G8B8A8_UINT
,
181 BRW_SURFACEFORMAT_R8G8B8A8_UINT
184 static const GLuint ubyte_types_norm
[5] = {
186 BRW_SURFACEFORMAT_R8_UNORM
,
187 BRW_SURFACEFORMAT_R8G8_UNORM
,
188 BRW_SURFACEFORMAT_R8G8B8_UNORM
,
189 BRW_SURFACEFORMAT_R8G8B8A8_UNORM
192 static const GLuint ubyte_types_scale
[5] = {
194 BRW_SURFACEFORMAT_R8_USCALED
,
195 BRW_SURFACEFORMAT_R8G8_USCALED
,
196 BRW_SURFACEFORMAT_R8G8B8_USCALED
,
197 BRW_SURFACEFORMAT_R8G8B8A8_USCALED
200 static const GLuint byte_types_direct
[5] = {
202 BRW_SURFACEFORMAT_R8_SINT
,
203 BRW_SURFACEFORMAT_R8G8_SINT
,
204 BRW_SURFACEFORMAT_R8G8B8A8_SINT
,
205 BRW_SURFACEFORMAT_R8G8B8A8_SINT
208 static const GLuint byte_types_norm
[5] = {
210 BRW_SURFACEFORMAT_R8_SNORM
,
211 BRW_SURFACEFORMAT_R8G8_SNORM
,
212 BRW_SURFACEFORMAT_R8G8B8_SNORM
,
213 BRW_SURFACEFORMAT_R8G8B8A8_SNORM
216 static const GLuint byte_types_scale
[5] = {
218 BRW_SURFACEFORMAT_R8_SSCALED
,
219 BRW_SURFACEFORMAT_R8G8_SSCALED
,
220 BRW_SURFACEFORMAT_R8G8B8_SSCALED
,
221 BRW_SURFACEFORMAT_R8G8B8A8_SSCALED
225 double_types(struct brw_context
*brw
,
229 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
230 * "When SourceElementFormat is set to one of the *64*_PASSTHRU formats,
231 * 64-bit components are stored in the URB without any conversion."
232 * Also included on BDW PRM, Volume 7, page 470, table "Source Element
233 * Formats Supported in VF Unit"
234 * Previous PRMs don't include those references.
236 return (brw
->gen
>= 8 && doubles
237 ? double_types_passthru
[size
]
238 : double_types_float
[size
]);
242 * Given vertex array type/size/format/normalized info, return
243 * the appopriate hardware surface type.
244 * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
247 brw_get_vertex_surface_type(struct brw_context
*brw
,
248 const struct gl_client_array
*glarray
)
250 int size
= glarray
->Size
;
252 if (unlikely(INTEL_DEBUG
& DEBUG_VERTS
))
253 fprintf(stderr
, "type %s size %d normalized %d\n",
254 _mesa_enum_to_string(glarray
->Type
),
255 glarray
->Size
, glarray
->Normalized
);
257 if (glarray
->Integer
) {
258 assert(glarray
->Format
== GL_RGBA
); /* sanity check */
259 switch (glarray
->Type
) {
260 case GL_INT
: return int_types_direct
[size
];
261 case GL_SHORT
: return short_types_direct
[size
];
262 case GL_BYTE
: return byte_types_direct
[size
];
263 case GL_UNSIGNED_INT
: return uint_types_direct
[size
];
264 case GL_UNSIGNED_SHORT
: return ushort_types_direct
[size
];
265 case GL_UNSIGNED_BYTE
: return ubyte_types_direct
[size
];
266 default: unreachable("not reached");
268 } else if (glarray
->Type
== GL_UNSIGNED_INT_10F_11F_11F_REV
) {
269 return BRW_SURFACEFORMAT_R11G11B10_FLOAT
;
270 } else if (glarray
->Normalized
) {
271 switch (glarray
->Type
) {
272 case GL_DOUBLE
: return double_types(brw
, size
, glarray
->Doubles
);
273 case GL_FLOAT
: return float_types
[size
];
274 case GL_HALF_FLOAT
: return half_float_types
[size
];
275 case GL_INT
: return int_types_norm
[size
];
276 case GL_SHORT
: return short_types_norm
[size
];
277 case GL_BYTE
: return byte_types_norm
[size
];
278 case GL_UNSIGNED_INT
: return uint_types_norm
[size
];
279 case GL_UNSIGNED_SHORT
: return ushort_types_norm
[size
];
280 case GL_UNSIGNED_BYTE
:
281 if (glarray
->Format
== GL_BGRA
) {
282 /* See GL_EXT_vertex_array_bgra */
284 return BRW_SURFACEFORMAT_B8G8R8A8_UNORM
;
287 return ubyte_types_norm
[size
];
290 if (brw
->gen
>= 8 || brw
->is_haswell
)
291 return fixed_point_types
[size
];
293 /* This produces GL_FIXED inputs as values between INT32_MIN and
294 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
296 return int_types_scale
[size
];
297 /* See GL_ARB_vertex_type_2_10_10_10_rev.
298 * W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
299 * like to use here, so upload everything as UINT and fix
302 case GL_INT_2_10_10_10_REV
:
304 if (brw
->gen
>= 8 || brw
->is_haswell
) {
305 return glarray
->Format
== GL_BGRA
306 ? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
307 : BRW_SURFACEFORMAT_R10G10B10A2_SNORM
;
309 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
310 case GL_UNSIGNED_INT_2_10_10_10_REV
:
312 if (brw
->gen
>= 8 || brw
->is_haswell
) {
313 return glarray
->Format
== GL_BGRA
314 ? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
315 : BRW_SURFACEFORMAT_R10G10B10A2_UNORM
;
317 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
318 default: unreachable("not reached");
322 /* See GL_ARB_vertex_type_2_10_10_10_rev.
323 * W/A: the hardware doesn't really support the formats we'd
324 * like to use here, so upload everything as UINT and fix
327 if (glarray
->Type
== GL_INT_2_10_10_10_REV
) {
329 if (brw
->gen
>= 8 || brw
->is_haswell
) {
330 return glarray
->Format
== GL_BGRA
331 ? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
332 : BRW_SURFACEFORMAT_R10G10B10A2_SSCALED
;
334 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
335 } else if (glarray
->Type
== GL_UNSIGNED_INT_2_10_10_10_REV
) {
337 if (brw
->gen
>= 8 || brw
->is_haswell
) {
338 return glarray
->Format
== GL_BGRA
339 ? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
340 : BRW_SURFACEFORMAT_R10G10B10A2_USCALED
;
342 return BRW_SURFACEFORMAT_R10G10B10A2_UINT
;
344 assert(glarray
->Format
== GL_RGBA
); /* sanity check */
345 switch (glarray
->Type
) {
346 case GL_DOUBLE
: return double_types(brw
, size
, glarray
->Doubles
);
347 case GL_FLOAT
: return float_types
[size
];
348 case GL_HALF_FLOAT
: return half_float_types
[size
];
349 case GL_INT
: return int_types_scale
[size
];
350 case GL_SHORT
: return short_types_scale
[size
];
351 case GL_BYTE
: return byte_types_scale
[size
];
352 case GL_UNSIGNED_INT
: return uint_types_scale
[size
];
353 case GL_UNSIGNED_SHORT
: return ushort_types_scale
[size
];
354 case GL_UNSIGNED_BYTE
: return ubyte_types_scale
[size
];
356 if (brw
->gen
>= 8 || brw
->is_haswell
)
357 return fixed_point_types
[size
];
359 /* This produces GL_FIXED inputs as values between INT32_MIN and
360 * INT32_MAX, which will be scaled down by 1/65536 by the VS.
362 return int_types_scale
[size
];
363 default: unreachable("not reached");
369 copy_array_to_vbo_array(struct brw_context
*brw
,
370 struct brw_vertex_element
*element
,
372 struct brw_vertex_buffer
*buffer
,
375 const int src_stride
= element
->glarray
->StrideB
;
377 /* If the source stride is zero, we just want to upload the current
378 * attribute once and set the buffer's stride to 0. There's no need
379 * to replicate it out.
381 if (src_stride
== 0) {
382 intel_upload_data(brw
, element
->glarray
->Ptr
,
383 element
->glarray
->_ElementSize
,
384 element
->glarray
->_ElementSize
,
385 &buffer
->bo
, &buffer
->offset
);
391 const unsigned char *src
= element
->glarray
->Ptr
+ min
* src_stride
;
392 int count
= max
- min
+ 1;
393 GLuint size
= count
* dst_stride
;
394 uint8_t *dst
= intel_upload_space(brw
, size
, dst_stride
,
395 &buffer
->bo
, &buffer
->offset
);
397 if (dst_stride
== src_stride
) {
398 memcpy(dst
, src
, size
);
401 memcpy(dst
, src
, dst_stride
);
406 buffer
->stride
= dst_stride
;
410 brw_prepare_vertices(struct brw_context
*brw
)
412 struct gl_context
*ctx
= &brw
->ctx
;
413 /* BRW_NEW_VS_PROG_DATA */
414 GLbitfield64 vs_inputs
= brw
->vs
.prog_data
->inputs_read
;
415 const unsigned char *ptr
= NULL
;
416 GLuint interleaved
= 0;
417 unsigned int min_index
= brw
->vb
.min_index
+ brw
->basevertex
;
418 unsigned int max_index
= brw
->vb
.max_index
+ brw
->basevertex
;
422 struct brw_vertex_element
*upload
[VERT_ATTRIB_MAX
];
423 GLuint nr_uploads
= 0;
427 * On gen6+, edge flags don't end up in the VUE (either in or out of the
428 * VS). Instead, they're uploaded as the last vertex element, and the data
429 * is passed sideband through the fixed function units. So, we need to
430 * prepare the vertex buffer for it, but it's not present in inputs_read.
432 if (brw
->gen
>= 6 && (ctx
->Polygon
.FrontMode
!= GL_FILL
||
433 ctx
->Polygon
.BackMode
!= GL_FILL
)) {
434 vs_inputs
|= VERT_BIT_EDGEFLAG
;
438 fprintf(stderr
, "%s %d..%d\n", __func__
, min_index
, max_index
);
440 /* Accumulate the list of enabled arrays. */
441 brw
->vb
.nr_enabled
= 0;
443 GLuint index
= ffsll(vs_inputs
) - 1;
444 struct brw_vertex_element
*input
= &brw
->vb
.inputs
[index
];
446 vs_inputs
&= ~BITFIELD64_BIT(index
);
447 brw
->vb
.enabled
[brw
->vb
.nr_enabled
++] = input
;
450 if (brw
->vb
.nr_enabled
== 0)
453 if (brw
->vb
.nr_buffers
)
456 /* The range of data in a given buffer represented as [min, max) */
457 struct intel_buffer_object
*enabled_buffer
[VERT_ATTRIB_MAX
];
458 uint32_t buffer_range_start
[VERT_ATTRIB_MAX
];
459 uint32_t buffer_range_end
[VERT_ATTRIB_MAX
];
461 for (i
= j
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
462 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
463 const struct gl_client_array
*glarray
= input
->glarray
;
465 if (_mesa_is_bufferobj(glarray
->BufferObj
)) {
466 struct intel_buffer_object
*intel_buffer
=
467 intel_buffer_object(glarray
->BufferObj
);
469 const uint32_t offset
= (uintptr_t)glarray
->Ptr
;
471 /* Start with the worst case */
473 uint32_t range
= intel_buffer
->Base
.Size
;
474 if (glarray
->InstanceDivisor
) {
475 if (brw
->num_instances
) {
476 start
= offset
+ glarray
->StrideB
* brw
->baseinstance
;
477 range
= (glarray
->StrideB
* ((brw
->num_instances
- 1) /
478 glarray
->InstanceDivisor
) +
479 glarray
->_ElementSize
);
482 if (brw
->vb
.index_bounds_valid
) {
483 start
= offset
+ min_index
* glarray
->StrideB
;
484 range
= (glarray
->StrideB
* (max_index
- min_index
) +
485 glarray
->_ElementSize
);
489 /* If we have a VB set to be uploaded for this buffer object
490 * already, reuse that VB state so that we emit fewer
494 for (k
= 0; k
< i
; k
++) {
495 const struct gl_client_array
*other
= brw
->vb
.enabled
[k
]->glarray
;
496 if (glarray
->BufferObj
== other
->BufferObj
&&
497 glarray
->StrideB
== other
->StrideB
&&
498 glarray
->InstanceDivisor
== other
->InstanceDivisor
&&
499 (uintptr_t)(glarray
->Ptr
- other
->Ptr
) < glarray
->StrideB
)
501 input
->buffer
= brw
->vb
.enabled
[k
]->buffer
;
502 input
->offset
= glarray
->Ptr
- other
->Ptr
;
504 buffer_range_start
[k
] = MIN2(buffer_range_start
[k
], start
);
505 buffer_range_end
[k
] = MAX2(buffer_range_end
[k
], start
+ range
);
510 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
512 /* Named buffer object: Just reference its contents directly. */
513 buffer
->offset
= offset
;
514 buffer
->stride
= glarray
->StrideB
;
515 buffer
->step_rate
= glarray
->InstanceDivisor
;
517 enabled_buffer
[j
] = intel_buffer
;
518 buffer_range_start
[j
] = start
;
519 buffer_range_end
[j
] = start
+ range
;
525 /* This is a common place to reach if the user mistakenly supplies
526 * a pointer in place of a VBO offset. If we just let it go through,
527 * we may end up dereferencing a pointer beyond the bounds of the
530 * The VBO spec allows application termination in this case, and it's
531 * probably a service to the poor programmer to do so rather than
532 * trying to just not render.
534 assert(input
->offset
< intel_buffer
->Base
.Size
);
536 /* Queue the buffer object up to be uploaded in the next pass,
537 * when we've decided if we're doing interleaved or not.
539 if (nr_uploads
== 0) {
540 interleaved
= glarray
->StrideB
;
543 else if (interleaved
!= glarray
->StrideB
||
544 glarray
->Ptr
< ptr
||
545 (uintptr_t)(glarray
->Ptr
- ptr
) + glarray
->_ElementSize
> interleaved
)
547 /* If our stride is different from the first attribute's stride,
548 * or if the first attribute's stride didn't cover our element,
549 * disable the interleaved upload optimization. The second case
550 * can most commonly occur in cases where there is a single vertex
551 * and, for example, the data is stored on the application's
554 * NOTE: This will also disable the optimization in cases where
555 * the data is in a different order than the array indices.
559 * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
560 * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
565 upload
[nr_uploads
++] = input
;
569 /* Now that we've set up all of the buffers, we walk through and reference
570 * each of them. We do this late so that we get the right size in each
571 * buffer and don't reference too little data.
573 for (i
= 0; i
< j
; i
++) {
574 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
578 const uint32_t start
= buffer_range_start
[i
];
579 const uint32_t range
= buffer_range_end
[i
] - buffer_range_start
[i
];
581 buffer
->bo
= intel_bufferobj_buffer(brw
, enabled_buffer
[i
], start
, range
);
582 drm_intel_bo_reference(buffer
->bo
);
585 /* If we need to upload all the arrays, then we can trim those arrays to
586 * only the used elements [min_index, max_index] so long as we adjust all
587 * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias.
589 brw
->vb
.start_vertex_bias
= 0;
591 if (nr_uploads
== brw
->vb
.nr_enabled
) {
592 brw
->vb
.start_vertex_bias
= -delta
;
596 /* Handle any arrays to be uploaded. */
597 if (nr_uploads
> 1) {
599 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
600 /* All uploads are interleaved, so upload the arrays together as
601 * interleaved. First, upload the contents and set up upload[0].
603 copy_array_to_vbo_array(brw
, upload
[0], min_index
, max_index
,
604 buffer
, interleaved
);
605 buffer
->offset
-= delta
* interleaved
;
607 for (i
= 0; i
< nr_uploads
; i
++) {
608 /* Then, just point upload[i] at upload[0]'s buffer. */
610 ((const unsigned char *)upload
[i
]->glarray
->Ptr
- ptr
);
611 upload
[i
]->buffer
= j
;
618 /* Upload non-interleaved arrays */
619 for (i
= 0; i
< nr_uploads
; i
++) {
620 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[j
];
621 if (upload
[i
]->glarray
->InstanceDivisor
== 0) {
622 copy_array_to_vbo_array(brw
, upload
[i
], min_index
, max_index
,
623 buffer
, upload
[i
]->glarray
->_ElementSize
);
625 /* This is an instanced attribute, since its InstanceDivisor
626 * is not zero. Therefore, its data will be stepped after the
627 * instanced draw has been run InstanceDivisor times.
629 uint32_t instanced_attr_max_index
=
630 (brw
->num_instances
- 1) / upload
[i
]->glarray
->InstanceDivisor
;
631 copy_array_to_vbo_array(brw
, upload
[i
], 0, instanced_attr_max_index
,
632 buffer
, upload
[i
]->glarray
->_ElementSize
);
634 buffer
->offset
-= delta
* buffer
->stride
;
635 buffer
->step_rate
= upload
[i
]->glarray
->InstanceDivisor
;
636 upload
[i
]->buffer
= j
++;
637 upload
[i
]->offset
= 0;
640 brw
->vb
.nr_buffers
= j
;
644 brw_prepare_shader_draw_parameters(struct brw_context
*brw
)
646 /* For non-indirect draws, upload gl_BaseVertex. */
647 if ((brw
->vs
.prog_data
->uses_basevertex
||
648 brw
->vs
.prog_data
->uses_baseinstance
) &&
649 brw
->draw
.draw_params_bo
== NULL
) {
650 intel_upload_data(brw
, &brw
->draw
.params
, sizeof(brw
->draw
.params
), 4,
651 &brw
->draw
.draw_params_bo
,
652 &brw
->draw
.draw_params_offset
);
655 if (brw
->vs
.prog_data
->uses_drawid
) {
656 intel_upload_data(brw
, &brw
->draw
.gl_drawid
, sizeof(brw
->draw
.gl_drawid
), 4,
657 &brw
->draw
.draw_id_bo
,
658 &brw
->draw
.draw_id_offset
);
663 * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
666 emit_vertex_buffer_state(struct brw_context
*brw
,
669 unsigned bo_ending_address
,
675 struct gl_context
*ctx
= &brw
->ctx
;
679 dw0
= (buffer_nr
<< GEN6_VB0_INDEX_SHIFT
) |
680 (step_rate
? GEN6_VB0_ACCESS_INSTANCEDATA
681 : GEN6_VB0_ACCESS_VERTEXDATA
);
683 dw0
= (buffer_nr
<< BRW_VB0_INDEX_SHIFT
) |
684 (step_rate
? BRW_VB0_ACCESS_INSTANCEDATA
685 : BRW_VB0_ACCESS_VERTEXDATA
);
689 dw0
|= GEN7_VB0_ADDRESS_MODIFYENABLE
;
692 dw0
|= GEN7_MOCS_L3
<< 16;
694 WARN_ONCE(stride
>= (brw
->gen
>= 5 ? 2048 : 2047),
695 "VBO stride %d too large, bad rendering may occur\n",
697 OUT_BATCH(dw0
| (stride
<< BRW_VB0_PITCH_SHIFT
));
698 OUT_RELOC(bo
, I915_GEM_DOMAIN_VERTEX
, 0, bo_offset
);
700 OUT_RELOC(bo
, I915_GEM_DOMAIN_VERTEX
, 0, bo_ending_address
);
704 OUT_BATCH(step_rate
);
708 #define EMIT_VERTEX_BUFFER_STATE(...) __map = emit_vertex_buffer_state(__VA_ARGS__, __map)
711 brw_emit_vertices(struct brw_context
*brw
)
715 brw_prepare_vertices(brw
);
716 brw_prepare_shader_draw_parameters(brw
);
718 brw_emit_query_begin(brw
);
720 unsigned nr_elements
= brw
->vb
.nr_enabled
;
721 if (brw
->vs
.prog_data
->uses_vertexid
|| brw
->vs
.prog_data
->uses_instanceid
||
722 brw
->vs
.prog_data
->uses_basevertex
|| brw
->vs
.prog_data
->uses_baseinstance
)
724 if (brw
->vs
.prog_data
->uses_drawid
)
727 /* If the VS doesn't read any inputs (calculating vertex position from
728 * a state variable for some reason, for example), emit a single pad
729 * VERTEX_ELEMENT struct and bail.
731 * The stale VB state stays in place, but they don't do anything unless
732 * a VE loads from them.
734 if (nr_elements
== 0) {
736 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | 1);
738 OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT
) |
740 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
741 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
743 OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT
) |
745 (BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
<< BRW_VE0_FORMAT_SHIFT
) |
746 (0 << BRW_VE0_SRC_OFFSET_SHIFT
));
748 OUT_BATCH((BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
749 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
750 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
751 (BRW_VE1_COMPONENT_STORE_1_FLT
<< BRW_VE1_COMPONENT_3_SHIFT
));
756 /* Now emit VB and VEP state packets.
759 const bool uses_draw_params
=
760 brw
->vs
.prog_data
->uses_basevertex
||
761 brw
->vs
.prog_data
->uses_baseinstance
;
762 const unsigned nr_buffers
= brw
->vb
.nr_buffers
+
763 uses_draw_params
+ brw
->vs
.prog_data
->uses_drawid
;
767 assert(nr_buffers
<= 33);
769 assert(nr_buffers
<= 17);
772 BEGIN_BATCH(1 + 4 * nr_buffers
);
773 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS
<< 16) | (4 * nr_buffers
- 1));
774 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
775 struct brw_vertex_buffer
*buffer
= &brw
->vb
.buffers
[i
];
776 EMIT_VERTEX_BUFFER_STATE(brw
, i
, buffer
->bo
, buffer
->bo
->size
- 1,
777 buffer
->offset
, buffer
->stride
,
782 if (uses_draw_params
) {
783 EMIT_VERTEX_BUFFER_STATE(brw
, brw
->vb
.nr_buffers
,
784 brw
->draw
.draw_params_bo
,
785 brw
->draw
.draw_params_bo
->size
- 1,
786 brw
->draw
.draw_params_offset
,
791 if (brw
->vs
.prog_data
->uses_drawid
) {
792 EMIT_VERTEX_BUFFER_STATE(brw
, brw
->vb
.nr_buffers
+ 1,
793 brw
->draw
.draw_id_bo
,
794 brw
->draw
.draw_id_bo
->size
- 1,
795 brw
->draw
.draw_id_offset
,
803 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
804 * for VertexID/InstanceID.
807 assert(nr_elements
<= 34);
809 assert(nr_elements
<= 18);
812 struct brw_vertex_element
*gen6_edgeflag_input
= NULL
;
814 BEGIN_BATCH(1 + nr_elements
* 2);
815 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS
<< 16) | (2 * nr_elements
- 1));
816 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
817 struct brw_vertex_element
*input
= brw
->vb
.enabled
[i
];
818 uint32_t format
= brw_get_vertex_surface_type(brw
, input
->glarray
);
819 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
820 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
821 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_SRC
;
822 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_SRC
;
824 if (input
== &brw
->vb
.inputs
[VERT_ATTRIB_EDGEFLAG
]) {
825 /* Gen6+ passes edgeflag as sideband along with the vertex, instead
826 * of in the VUE. We have to upload it sideband as the last vertex
827 * element according to the B-Spec.
830 gen6_edgeflag_input
= input
;
835 switch (input
->glarray
->Size
) {
836 case 0: comp0
= BRW_VE1_COMPONENT_STORE_0
;
837 case 1: comp1
= BRW_VE1_COMPONENT_STORE_0
;
838 case 2: comp2
= BRW_VE1_COMPONENT_STORE_0
;
839 case 3: comp3
= input
->glarray
->Integer
? BRW_VE1_COMPONENT_STORE_1_INT
840 : BRW_VE1_COMPONENT_STORE_1_FLT
;
845 OUT_BATCH((input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
847 (format
<< BRW_VE0_FORMAT_SHIFT
) |
848 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
850 OUT_BATCH((input
->buffer
<< BRW_VE0_INDEX_SHIFT
) |
852 (format
<< BRW_VE0_FORMAT_SHIFT
) |
853 (input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
857 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
858 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
859 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
860 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
));
862 OUT_BATCH((comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
863 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
864 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
865 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
) |
866 ((i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
));
869 if (brw
->vs
.prog_data
->uses_vertexid
|| brw
->vs
.prog_data
->uses_instanceid
||
870 brw
->vs
.prog_data
->uses_basevertex
|| brw
->vs
.prog_data
->uses_baseinstance
) {
871 uint32_t dw0
= 0, dw1
= 0;
872 uint32_t comp0
= BRW_VE1_COMPONENT_STORE_0
;
873 uint32_t comp1
= BRW_VE1_COMPONENT_STORE_0
;
874 uint32_t comp2
= BRW_VE1_COMPONENT_STORE_0
;
875 uint32_t comp3
= BRW_VE1_COMPONENT_STORE_0
;
877 if (brw
->vs
.prog_data
->uses_basevertex
)
878 comp0
= BRW_VE1_COMPONENT_STORE_SRC
;
880 if (brw
->vs
.prog_data
->uses_baseinstance
)
881 comp1
= BRW_VE1_COMPONENT_STORE_SRC
;
883 if (brw
->vs
.prog_data
->uses_vertexid
)
884 comp2
= BRW_VE1_COMPONENT_STORE_VID
;
886 if (brw
->vs
.prog_data
->uses_instanceid
)
887 comp3
= BRW_VE1_COMPONENT_STORE_IID
;
889 dw1
= (comp0
<< BRW_VE1_COMPONENT_0_SHIFT
) |
890 (comp1
<< BRW_VE1_COMPONENT_1_SHIFT
) |
891 (comp2
<< BRW_VE1_COMPONENT_2_SHIFT
) |
892 (comp3
<< BRW_VE1_COMPONENT_3_SHIFT
);
895 dw0
|= GEN6_VE0_VALID
|
896 brw
->vb
.nr_buffers
<< GEN6_VE0_INDEX_SHIFT
|
897 BRW_SURFACEFORMAT_R32G32_UINT
<< BRW_VE0_FORMAT_SHIFT
;
899 dw0
|= BRW_VE0_VALID
|
900 brw
->vb
.nr_buffers
<< BRW_VE0_INDEX_SHIFT
|
901 BRW_SURFACEFORMAT_R32G32_UINT
<< BRW_VE0_FORMAT_SHIFT
;
902 dw1
|= (i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
;
905 /* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
906 * the format is ignored and the value is always int.
913 if (brw
->vs
.prog_data
->uses_drawid
) {
914 uint32_t dw0
= 0, dw1
= 0;
916 dw1
= (BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
917 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
918 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
919 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
);
922 dw0
|= GEN6_VE0_VALID
|
923 ((brw
->vb
.nr_buffers
+ 1) << GEN6_VE0_INDEX_SHIFT
) |
924 (BRW_SURFACEFORMAT_R32_UINT
<< BRW_VE0_FORMAT_SHIFT
);
926 dw0
|= BRW_VE0_VALID
|
927 ((brw
->vb
.nr_buffers
+ 1) << BRW_VE0_INDEX_SHIFT
) |
928 (BRW_SURFACEFORMAT_R32_UINT
<< BRW_VE0_FORMAT_SHIFT
);
930 dw1
|= (i
* 4) << BRW_VE1_DST_OFFSET_SHIFT
;
937 if (brw
->gen
>= 6 && gen6_edgeflag_input
) {
939 brw_get_vertex_surface_type(brw
, gen6_edgeflag_input
->glarray
);
941 OUT_BATCH((gen6_edgeflag_input
->buffer
<< GEN6_VE0_INDEX_SHIFT
) |
943 GEN6_VE0_EDGE_FLAG_ENABLE
|
944 (format
<< BRW_VE0_FORMAT_SHIFT
) |
945 (gen6_edgeflag_input
->offset
<< BRW_VE0_SRC_OFFSET_SHIFT
));
946 OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC
<< BRW_VE1_COMPONENT_0_SHIFT
) |
947 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_1_SHIFT
) |
948 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_2_SHIFT
) |
949 (BRW_VE1_COMPONENT_STORE_0
<< BRW_VE1_COMPONENT_3_SHIFT
));
955 const struct brw_tracked_state brw_vertices
= {
957 .mesa
= _NEW_POLYGON
,
958 .brw
= BRW_NEW_BATCH
|
961 BRW_NEW_VS_PROG_DATA
,
963 .emit
= brw_emit_vertices
,
967 brw_upload_indices(struct brw_context
*brw
)
969 struct gl_context
*ctx
= &brw
->ctx
;
970 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
972 drm_intel_bo
*old_bo
= brw
->ib
.bo
;
973 struct gl_buffer_object
*bufferobj
;
977 if (index_buffer
== NULL
)
980 ib_type_size
= _mesa_sizeof_type(index_buffer
->type
);
981 ib_size
= ib_type_size
* index_buffer
->count
;
982 bufferobj
= index_buffer
->obj
;
984 /* Turn into a proper VBO:
986 if (!_mesa_is_bufferobj(bufferobj
)) {
987 /* Get new bufferobj, offset:
989 intel_upload_data(brw
, index_buffer
->ptr
, ib_size
, ib_type_size
,
990 &brw
->ib
.bo
, &offset
);
992 offset
= (GLuint
) (unsigned long) index_buffer
->ptr
;
994 /* If the index buffer isn't aligned to its element size, we have to
995 * rebase it into a temporary.
997 if ((ib_type_size
- 1) & offset
) {
998 perf_debug("copying index buffer to a temporary to work around "
999 "misaligned offset %d\n", offset
);
1001 GLubyte
*map
= ctx
->Driver
.MapBufferRange(ctx
,
1008 intel_upload_data(brw
, map
, ib_size
, ib_type_size
,
1009 &brw
->ib
.bo
, &offset
);
1011 ctx
->Driver
.UnmapBuffer(ctx
, bufferobj
, MAP_INTERNAL
);
1014 intel_bufferobj_buffer(brw
, intel_buffer_object(bufferobj
),
1016 if (bo
!= brw
->ib
.bo
) {
1017 drm_intel_bo_unreference(brw
->ib
.bo
);
1019 drm_intel_bo_reference(bo
);
1024 /* Use 3DPRIMITIVE's start_vertex_offset to avoid re-uploading
1025 * the index buffer state when we're just moving the start index
1028 brw
->ib
.start_vertex_offset
= offset
/ ib_type_size
;
1030 if (brw
->ib
.bo
!= old_bo
)
1031 brw
->ctx
.NewDriverState
|= BRW_NEW_INDEX_BUFFER
;
1033 if (index_buffer
->type
!= brw
->ib
.type
) {
1034 brw
->ib
.type
= index_buffer
->type
;
1035 brw
->ctx
.NewDriverState
|= BRW_NEW_INDEX_BUFFER
;
1039 const struct brw_tracked_state brw_indices
= {
1042 .brw
= BRW_NEW_BLORP
|
1045 .emit
= brw_upload_indices
,
1049 brw_emit_index_buffer(struct brw_context
*brw
)
1051 const struct _mesa_index_buffer
*index_buffer
= brw
->ib
.ib
;
1052 GLuint cut_index_setting
;
1054 if (index_buffer
== NULL
)
1057 if (brw
->prim_restart
.enable_cut_index
&& !brw
->is_haswell
) {
1058 cut_index_setting
= BRW_CUT_INDEX_ENABLE
;
1060 cut_index_setting
= 0;
1064 OUT_BATCH(CMD_INDEX_BUFFER
<< 16 |
1066 brw_get_index_type(index_buffer
->type
) |
1068 OUT_RELOC(brw
->ib
.bo
,
1069 I915_GEM_DOMAIN_VERTEX
, 0,
1071 OUT_RELOC(brw
->ib
.bo
,
1072 I915_GEM_DOMAIN_VERTEX
, 0,
1073 brw
->ib
.bo
->size
- 1);
1077 const struct brw_tracked_state brw_index_buffer
= {
1080 .brw
= BRW_NEW_BATCH
|
1082 BRW_NEW_INDEX_BUFFER
,
1084 .emit
= brw_emit_index_buffer
,