src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "util/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_Q);
  65    return names[type];
  66 }
  67
  68 /* Returns a conditional modifier that negates the condition. */
  69 enum brw_conditional_mod
  70 brw_negate_cmod(uint32_t cmod)
  71 {
  72    switch (cmod) {
  73    case BRW_CONDITIONAL_Z:
  74       return BRW_CONDITIONAL_NZ;
  75    case BRW_CONDITIONAL_NZ:
  76       return BRW_CONDITIONAL_Z;
  77    case BRW_CONDITIONAL_G:
  78       return BRW_CONDITIONAL_LE;
  79    case BRW_CONDITIONAL_GE:
  80       return BRW_CONDITIONAL_L;
  81    case BRW_CONDITIONAL_L:
  82       return BRW_CONDITIONAL_GE;
  83    case BRW_CONDITIONAL_LE:
  84       return BRW_CONDITIONAL_G;
  85    default:
  86       return ~0;
  87    }
  88 }
  89
  90 /* Returns the corresponding conditional mod for swapping src0 and
  91  * src1 in e.g. CMP.
  92  */
  93 enum brw_conditional_mod
  94 brw_swap_cmod(uint32_t cmod)
  95 {
  96    switch (cmod) {
  97    case BRW_CONDITIONAL_Z:
  98    case BRW_CONDITIONAL_NZ:
  99       return cmod;
 100    case BRW_CONDITIONAL_G:
 101       return BRW_CONDITIONAL_L;
 102    case BRW_CONDITIONAL_GE:
 103       return BRW_CONDITIONAL_LE;
 104    case BRW_CONDITIONAL_L:
 105       return BRW_CONDITIONAL_G;
 106    case BRW_CONDITIONAL_LE:
 107       return BRW_CONDITIONAL_GE;
 108    default:
 109       return BRW_CONDITIONAL_NONE;
 110    }
 111 }
 112
 113 void
 114 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 115 {
 116    brw_inst_set_exec_size(p->devinfo, p->current, value);
 117 }
 118
 119 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 120 {
 121    brw_inst_set_pred_control(p->devinfo, p->current, pc);
 122 }
 123
 124 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 125 {
 126    brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
 127 }
 128
 129 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 130 {
 131    if (p->devinfo->gen >= 7)
 132       brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
 133
 134    brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
 135 }
 136
 137 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 138 {
 139    brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
 140 }
 141
 142 void
 143 brw_set_default_compression_control(struct brw_codegen *p,
 144                             enum brw_compression compression_control)
 145 {
 146    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 147
 148    if (p->devinfo->gen >= 6) {
 149       /* Since we don't use the SIMD32 support in gen6, we translate
 150        * the pre-gen6 compression control here.
 151        */
 152       switch (compression_control) {
 153       case BRW_COMPRESSION_NONE:
 154          /* This is the "use the first set of bits of dmask/vmask/arf
 155           * according to execsize" option.
 156           */
 157          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
 158          break;
 159       case BRW_COMPRESSION_2NDHALF:
 160          /* For SIMD8, this is "use the second set of 8 bits." */
 161          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
 162          break;
 163       case BRW_COMPRESSION_COMPRESSED:
 164          /* For SIMD16 instruction compression, use the first set of 16 bits
 165           * since we don't do SIMD32 dispatch.
 166           */
 167          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
 168          break;
 169       default:
 170          unreachable("not reached");
 171       }
 172    } else {
 173       brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
 174    }
 175 }
 176
 177 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 178 {
 179    brw_inst_set_mask_control(p->devinfo, p->current, value);
 180 }
 181
 182 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 183 {
 184    brw_inst_set_saturate(p->devinfo, p->current, enable);
 185 }
 186
 187 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 188 {
 189    if (p->devinfo->gen >= 6)
 190       brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
 191 }
 192
 193 void brw_push_insn_state( struct brw_codegen *p )
 194 {
 195    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 196    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 197    p->compressed_stack[p->current - p->stack] = p->compressed;
 198    p->current++;
 199 }
 200
 201 void brw_pop_insn_state( struct brw_codegen *p )
 202 {
 203    assert(p->current != p->stack);
 204    p->current--;
 205    p->compressed = p->compressed_stack[p->current - p->stack];
 206 }
 207
 208
 209 /***********************************************************************
 210  */
 211 void
 212 brw_init_codegen(const struct brw_device_info *devinfo,
 213                  struct brw_codegen *p, void *mem_ctx)
 214 {
 215    memset(p, 0, sizeof(*p));
 216
 217    p->devinfo = devinfo;
 218    /*
 219     * Set the initial instruction store array size to 1024, if found that
 220     * isn't enough, then it will double the store size at brw_next_insn()
 221     * until out of memory.
 222     */
 223    p->store_size = 1024;
 224    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 225    p->nr_insn = 0;
 226    p->current = p->stack;
 227    p->compressed = false;
 228    memset(p->current, 0, sizeof(p->current[0]));
 229
 230    p->mem_ctx = mem_ctx;
 231
 232    /* Some defaults?
 233     */
 234    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 235    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 236    brw_set_default_saturate(p, 0);
 237    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 238
 239    /* Set up control flow stack */
 240    p->if_stack_depth = 0;
 241    p->if_stack_array_size = 16;
 242    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 243
 244    p->loop_stack_depth = 0;
 245    p->loop_stack_array_size = 16;
 246    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 247    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 248
 249    brw_init_compaction_tables(devinfo);
 250 }
 251
 252
 253 const unsigned *brw_get_program( struct brw_codegen *p,
 254                                unsigned *sz )
 255 {
 256    *sz = p->next_insn_offset;
 257    return (const unsigned *)p->store;
 258 }
 259
 260 void
 261 brw_disassemble(const struct brw_device_info *devinfo,
 262                 void *assembly, int start, int end, FILE *out)
 263 {
 264    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 265
 266    for (int offset = start; offset < end;) {
 267       brw_inst *insn = assembly + offset;
 268       brw_inst uncompacted;
 269       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 270       if (0)
 271          fprintf(out, "0x%08x: ", offset);
 272
 273       if (compacted) {
 274          brw_compact_inst *compacted = (void *)insn;
 275          if (dump_hex) {
 276             fprintf(out, "0x%08x 0x%08x                       ",
 277                     ((uint32_t *)insn)[1],
 278                     ((uint32_t *)insn)[0]);
 279          }
 280
 281          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 282          insn = &uncompacted;
 283          offset += 8;
 284       } else {
 285          if (dump_hex) {
 286             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 287                     ((uint32_t *)insn)[3],
 288                     ((uint32_t *)insn)[2],
 289                     ((uint32_t *)insn)[1],
 290                     ((uint32_t *)insn)[0]);
 291          }
 292          offset += 16;
 293       }
 294
 295       brw_disassemble_inst(out, devinfo, insn, compacted);
 296    }
 297 }