src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "util/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_Q);
  65    return names[type];
  66 }
  67
  68 /* Returns a conditional modifier that negates the condition. */
  69 enum brw_conditional_mod
  70 brw_negate_cmod(uint32_t cmod)
  71 {
  72    switch (cmod) {
  73    case BRW_CONDITIONAL_Z:
  74       return BRW_CONDITIONAL_NZ;
  75    case BRW_CONDITIONAL_NZ:
  76       return BRW_CONDITIONAL_Z;
  77    case BRW_CONDITIONAL_G:
  78       return BRW_CONDITIONAL_LE;
  79    case BRW_CONDITIONAL_GE:
  80       return BRW_CONDITIONAL_L;
  81    case BRW_CONDITIONAL_L:
  82       return BRW_CONDITIONAL_GE;
  83    case BRW_CONDITIONAL_LE:
  84       return BRW_CONDITIONAL_G;
  85    default:
  86       return ~0;
  87    }
  88 }
  89
  90 /* Returns the corresponding conditional mod for swapping src0 and
  91  * src1 in e.g. CMP.
  92  */
  93 enum brw_conditional_mod
  94 brw_swap_cmod(uint32_t cmod)
  95 {
  96    switch (cmod) {
  97    case BRW_CONDITIONAL_Z:
  98    case BRW_CONDITIONAL_NZ:
  99       return cmod;
 100    case BRW_CONDITIONAL_G:
 101       return BRW_CONDITIONAL_L;
 102    case BRW_CONDITIONAL_GE:
 103       return BRW_CONDITIONAL_LE;
 104    case BRW_CONDITIONAL_L:
 105       return BRW_CONDITIONAL_G;
 106    case BRW_CONDITIONAL_LE:
 107       return BRW_CONDITIONAL_GE;
 108    default:
 109       return BRW_CONDITIONAL_NONE;
 110    }
 111 }
 112
 113 /**
 114  * Get the least significant bit offset of the i+1-th component of immediate
 115  * type \p type.  For \p i equal to the two's complement of j, return the
 116  * offset of the j-th component starting from the end of the vector.  For
 117  * scalar register types return zero.
 118  */
 119 static unsigned
 120 imm_shift(enum brw_reg_type type, unsigned i)
 121 {
 122    assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
 123           "Not implemented.");
 124
 125    if (type == BRW_REGISTER_TYPE_VF)
 126       return 8 * (i & 3);
 127    else
 128       return 0;
 129 }
 130
 131 /**
 132  * Swizzle an arbitrary immediate \p x of the given type according to the
 133  * permutation specified as \p swz.
 134  */
 135 uint32_t
 136 brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
 137 {
 138    if (imm_shift(type, 1)) {
 139       const unsigned n = 32 / imm_shift(type, 1);
 140       uint32_t y = 0;
 141
 142       for (unsigned i = 0; i < n; i++) {
 143          /* Shift the specified component all the way to the right and left to
 144           * discard any undesired L/MSBs, then shift it right into component i.
 145           */
 146          y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
 147                 << imm_shift(type, ~0u)
 148                 >> imm_shift(type, ~0u - i);
 149       }
 150
 151       return y;
 152    } else {
 153       return x;
 154    }
 155 }
 156
 157 void
 158 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 159 {
 160    brw_inst_set_exec_size(p->devinfo, p->current, value);
 161 }
 162
 163 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 164 {
 165    brw_inst_set_pred_control(p->devinfo, p->current, pc);
 166 }
 167
 168 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 169 {
 170    brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
 171 }
 172
 173 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 174 {
 175    if (p->devinfo->gen >= 7)
 176       brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
 177
 178    brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
 179 }
 180
 181 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 182 {
 183    brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
 184 }
 185
 186 void
 187 brw_set_default_compression_control(struct brw_codegen *p,
 188                             enum brw_compression compression_control)
 189 {
 190    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 191
 192    if (p->devinfo->gen >= 6) {
 193       /* Since we don't use the SIMD32 support in gen6, we translate
 194        * the pre-gen6 compression control here.
 195        */
 196       switch (compression_control) {
 197       case BRW_COMPRESSION_NONE:
 198          /* This is the "use the first set of bits of dmask/vmask/arf
 199           * according to execsize" option.
 200           */
 201          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
 202          break;
 203       case BRW_COMPRESSION_2NDHALF:
 204          /* For SIMD8, this is "use the second set of 8 bits." */
 205          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
 206          break;
 207       case BRW_COMPRESSION_COMPRESSED:
 208          /* For SIMD16 instruction compression, use the first set of 16 bits
 209           * since we don't do SIMD32 dispatch.
 210           */
 211          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
 212          break;
 213       default:
 214          unreachable("not reached");
 215       }
 216    } else {
 217       brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
 218    }
 219 }
 220
 221 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 222 {
 223    brw_inst_set_mask_control(p->devinfo, p->current, value);
 224 }
 225
 226 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 227 {
 228    brw_inst_set_saturate(p->devinfo, p->current, enable);
 229 }
 230
 231 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 232 {
 233    if (p->devinfo->gen >= 6)
 234       brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
 235 }
 236
 237 void brw_push_insn_state( struct brw_codegen *p )
 238 {
 239    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 240    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 241    p->compressed_stack[p->current - p->stack] = p->compressed;
 242    p->current++;
 243 }
 244
 245 void brw_pop_insn_state( struct brw_codegen *p )
 246 {
 247    assert(p->current != p->stack);
 248    p->current--;
 249    p->compressed = p->compressed_stack[p->current - p->stack];
 250 }
 251
 252
 253 /***********************************************************************
 254  */
 255 void
 256 brw_init_codegen(const struct brw_device_info *devinfo,
 257                  struct brw_codegen *p, void *mem_ctx)
 258 {
 259    memset(p, 0, sizeof(*p));
 260
 261    p->devinfo = devinfo;
 262    /*
 263     * Set the initial instruction store array size to 1024, if found that
 264     * isn't enough, then it will double the store size at brw_next_insn()
 265     * until out of memory.
 266     */
 267    p->store_size = 1024;
 268    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 269    p->nr_insn = 0;
 270    p->current = p->stack;
 271    p->compressed = false;
 272    memset(p->current, 0, sizeof(p->current[0]));
 273
 274    p->mem_ctx = mem_ctx;
 275
 276    /* Some defaults?
 277     */
 278    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 279    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 280    brw_set_default_saturate(p, 0);
 281    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 282
 283    /* Set up control flow stack */
 284    p->if_stack_depth = 0;
 285    p->if_stack_array_size = 16;
 286    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 287
 288    p->loop_stack_depth = 0;
 289    p->loop_stack_array_size = 16;
 290    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 291    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 292
 293    brw_init_compaction_tables(devinfo);
 294 }
 295
 296
 297 const unsigned *brw_get_program( struct brw_codegen *p,
 298                                unsigned *sz )
 299 {
 300    *sz = p->next_insn_offset;
 301    return (const unsigned *)p->store;
 302 }
 303
 304 void
 305 brw_disassemble(const struct brw_device_info *devinfo,
 306                 void *assembly, int start, int end, FILE *out)
 307 {
 308    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 309
 310    for (int offset = start; offset < end;) {
 311       brw_inst *insn = assembly + offset;
 312       brw_inst uncompacted;
 313       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 314       if (0)
 315          fprintf(out, "0x%08x: ", offset);
 316
 317       if (compacted) {
 318          brw_compact_inst *compacted = (void *)insn;
 319          if (dump_hex) {
 320             fprintf(out, "0x%08x 0x%08x                       ",
 321                     ((uint32_t *)insn)[1],
 322                     ((uint32_t *)insn)[0]);
 323          }
 324
 325          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 326          insn = &uncompacted;
 327          offset += 8;
 328       } else {
 329          if (dump_hex) {
 330             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 331                     ((uint32_t *)insn)[3],
 332                     ((uint32_t *)insn)[2],
 333                     ((uint32_t *)insn)[1],
 334                     ((uint32_t *)insn)[0]);
 335          }
 336          offset += 16;
 337       }
 338
 339       brw_disassemble_inst(out, devinfo, insn, compacted);
 340    }
 341 }
 342
 343 enum gen {
 344    GEN4  = (1 << 0),
 345    GEN45 = (1 << 1),
 346    GEN5  = (1 << 2),
 347    GEN6  = (1 << 3),
 348    GEN7  = (1 << 4),
 349    GEN75 = (1 << 5),
 350    GEN8  = (1 << 6),
 351    GEN9  = (1 << 7),
 352    GEN_ALL = ~0
 353 };
 354
 355 #define GEN_LT(gen) ((gen) - 1)
 356 #define GEN_GE(gen) (~GEN_LT(gen))
 357 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 358
 359 static const struct opcode_desc opcode_10_descs[] = {
 360    { .name = "dim",   .nsrc = 0, .ndst = 0, .gens = GEN75 },
 361    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 362 };
 363
 364 static const struct opcode_desc opcode_35_descs[] = {
 365    { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 366    { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
 367 };
 368
 369 static const struct opcode_desc opcode_38_descs[] = {
 370    { .name = "do",    .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 371    { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 372 };
 373
 374 static const struct opcode_desc opcode_44_descs[] = {
 375    { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 376    { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 377 };
 378
 379 static const struct opcode_desc opcode_45_descs[] = {
 380    { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 381    { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 382 };
 383
 384 static const struct opcode_desc opcode_46_descs[] = {
 385    { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 386    { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 387    { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 388 };
 389
 390 static const struct opcode_desc opcode_descs[128] = {
 391    [BRW_OPCODE_ILLEGAL] = {
 392       .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 393    },
 394    [BRW_OPCODE_MOV] = {
 395       .name = "mov",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 396    },
 397    [BRW_OPCODE_SEL] = {
 398       .name = "sel",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 399    },
 400    [BRW_OPCODE_MOVI] = {
 401       .name = "movi",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 402    },
 403    [BRW_OPCODE_NOT] = {
 404       .name = "not",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 405    },
 406    [BRW_OPCODE_AND] = {
 407       .name = "and",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 408    },
 409    [BRW_OPCODE_OR] = {
 410       .name = "or",      .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 411    },
 412    [BRW_OPCODE_XOR] = {
 413       .name = "xor",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 414    },
 415    [BRW_OPCODE_SHR] = {
 416       .name = "shr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 417    },
 418    [BRW_OPCODE_SHL] = {
 419       .name = "shl",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 420    },
 421    [10] = {
 422       .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
 423    },
 424    /* Reserved - 11 */
 425    [BRW_OPCODE_ASR] = {
 426       .name = "asr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 427    },
 428    /* Reserved - 13-15 */
 429    [BRW_OPCODE_CMP] = {
 430       .name = "cmp",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 431    },
 432    [BRW_OPCODE_CMPN] = {
 433       .name = "cmpn",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 434    },
 435    [BRW_OPCODE_CSEL] = {
 436       .name = "csel",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 437    },
 438    [BRW_OPCODE_F32TO16] = {
 439       .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 440    },
 441    [BRW_OPCODE_F16TO32] = {
 442       .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 443    },
 444    /* Reserved - 21-22 */
 445    [BRW_OPCODE_BFREV] = {
 446       .name = "bfrev",   .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 447    },
 448    [BRW_OPCODE_BFE] = {
 449       .name = "bfe",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 450    },
 451    [BRW_OPCODE_BFI1] = {
 452       .name = "bfi1",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 453    },
 454    [BRW_OPCODE_BFI2] = {
 455       .name = "bfi2",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 456    },
 457    /* Reserved - 27-31 */
 458    [BRW_OPCODE_JMPI] = {
 459       .name = "jmpi",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 460    },
 461    [33] = {
 462       .name = "brd",     .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
 463    },
 464    [BRW_OPCODE_IF] = {
 465       .name = "if",      .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 466    },
 467    [35] = {
 468       .table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
 469    },
 470    [BRW_OPCODE_ELSE] = {
 471       .name = "else",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 472    },
 473    [BRW_OPCODE_ENDIF] = {
 474       .name = "endif",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 475    },
 476    [38] = {
 477       .table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
 478    },
 479    [BRW_OPCODE_WHILE] = {
 480       .name = "while",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 481    },
 482    [BRW_OPCODE_BREAK] = {
 483       .name = "break",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 484    },
 485    [BRW_OPCODE_CONTINUE] = {
 486       .name = "cont",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 487    },
 488    [BRW_OPCODE_HALT] = {
 489       .name = "halt",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 490    },
 491    [43] = {
 492       .name = "calla",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
 493    },
 494    [44] = {
 495       .table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
 496    },
 497    [45] = {
 498       .table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
 499    },
 500    [46] = {
 501       .table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
 502    },
 503    [47] = {
 504       .name = "pop",     .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
 505    },
 506    [BRW_OPCODE_WAIT] = {
 507       .name = "wait",    .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
 508    },
 509    [BRW_OPCODE_SEND] = {
 510       .name = "send",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 511    },
 512    [BRW_OPCODE_SENDC] = {
 513       .name = "sendc",   .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 514    },
 515    [BRW_OPCODE_SENDS] = {
 516       .name = "sends",   .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 517    },
 518    [BRW_OPCODE_SENDSC] = {
 519       .name = "sendsc",  .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 520    },
 521    /* Reserved 53-55 */
 522    [BRW_OPCODE_MATH] = {
 523       .name = "math",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
 524    },
 525    /* Reserved 57-63 */
 526    [BRW_OPCODE_ADD] = {
 527       .name = "add",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 528    },
 529    [BRW_OPCODE_MUL] = {
 530       .name = "mul",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 531    },
 532    [BRW_OPCODE_AVG] = {
 533       .name = "avg",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 534    },
 535    [BRW_OPCODE_FRC] = {
 536       .name = "frc",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 537    },
 538    [BRW_OPCODE_RNDU] = {
 539       .name = "rndu",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 540    },
 541    [BRW_OPCODE_RNDD] = {
 542       .name = "rndd",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 543    },
 544    [BRW_OPCODE_RNDE] = {
 545       .name = "rnde",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 546    },
 547    [BRW_OPCODE_RNDZ] = {
 548       .name = "rndz",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 549    },
 550    [BRW_OPCODE_MAC] = {
 551       .name = "mac",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 552    },
 553    [BRW_OPCODE_MACH] = {
 554       .name = "mach",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 555    },
 556    [BRW_OPCODE_LZD] = {
 557       .name = "lzd",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 558    },
 559    [BRW_OPCODE_FBH] = {
 560       .name = "fbh",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 561    },
 562    [BRW_OPCODE_FBL] = {
 563       .name = "fbl",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 564    },
 565    [BRW_OPCODE_CBIT] = {
 566       .name = "cbit",    .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 567    },
 568    [BRW_OPCODE_ADDC] = {
 569       .name = "addc",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 570    },
 571    [BRW_OPCODE_SUBB] = {
 572       .name = "subb",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 573    },
 574    [BRW_OPCODE_SAD2] = {
 575       .name = "sad2",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 576    },
 577    [BRW_OPCODE_SADA2] = {
 578       .name = "sada2",   .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 579    },
 580    /* Reserved 82-83 */
 581    [BRW_OPCODE_DP4] = {
 582       .name = "dp4",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 583    },
 584    [BRW_OPCODE_DPH] = {
 585       .name = "dph",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 586    },
 587    [BRW_OPCODE_DP3] = {
 588       .name = "dp3",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 589    },
 590    [BRW_OPCODE_DP2] = {
 591       .name = "dp2",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 592    },
 593    /* Reserved 88 */
 594    [BRW_OPCODE_LINE] = {
 595       .name = "line",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 596    },
 597    [BRW_OPCODE_PLN] = {
 598       .name = "pln",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 599    },
 600    [BRW_OPCODE_MAD] = {
 601       .name = "mad",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 602    },
 603    [BRW_OPCODE_LRP] = {
 604       .name = "lrp",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 605    },
 606    [93] = {
 607       .name = "madm",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 608    },
 609    /* Reserved 94-124 */
 610    [BRW_OPCODE_NENOP] = {
 611       .name = "nenop",   .nsrc = 0, .ndst = 0, .gens = GEN45,
 612    },
 613    [BRW_OPCODE_NOP] = {
 614       .name = "nop",     .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 615    },
 616 };
 617
 618 static enum gen
 619 gen_from_devinfo(const struct brw_device_info *devinfo)
 620 {
 621    switch (devinfo->gen) {
 622    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 623    case 5: return GEN5;
 624    case 6: return GEN6;
 625    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 626    case 8: return GEN8;
 627    case 9: return GEN9;
 628    default:
 629       unreachable("not reached");
 630    }
 631 }
 632
 633 /* Return the matching opcode_desc for the specified opcode number and
 634  * hardware generation, or NULL if the opcode is not supported by the device.
 635  */
 636 const struct opcode_desc *
 637 brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode)
 638 {
 639    if (opcode >= ARRAY_SIZE(opcode_descs))
 640       return NULL;
 641
 642    enum gen gen = gen_from_devinfo(devinfo);
 643    if (opcode_descs[opcode].gens != 0) {
 644       if ((opcode_descs[opcode].gens & gen) != 0) {
 645          return &opcode_descs[opcode];
 646       }
 647    } else if (opcode_descs[opcode].table != NULL) {
 648       const struct opcode_desc *table = opcode_descs[opcode].table;
 649       for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
 650          if ((table[i].gens & gen) != 0) {
 651             return &table[i];
 652          }
 653       }
 654    }
 655    return NULL;
 656 }