src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /* Returns the corresponding conditional mod for swapping src0 and
  40  * src1 in e.g. CMP.
  41  */
  42 uint32_t
  43 brw_swap_cmod(uint32_t cmod)
  44 {
  45    switch (cmod) {
  46    case BRW_CONDITIONAL_Z:
  47    case BRW_CONDITIONAL_NZ:
  48       return cmod;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62
  63 /* How does predicate control work when execution_size != 8?  Do I
  64  * need to test/set for 0xffff when execution_size is 16?
  65  */
  66 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
  67 {
  68    p->current->header.predicate_control = BRW_PREDICATE_NONE;
  69
  70    if (value != 0xff) {
  71       if (value != p->flag_value) {
  72          brw_push_insn_state(p);
  73          brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
  74          p->flag_value = value;
  75          brw_pop_insn_state(p);
  76       }
  77
  78       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
  79    }
  80 }
  81
  82 void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
  83 {
  84    p->current->header.predicate_control = pc;
  85 }
  86
  87 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  88 {
  89    p->current->header.predicate_inverse = predicate_inverse;
  90 }
  91
  92 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
  93 {
  94    p->current->header.destreg__conditionalmod = conditional;
  95 }
  96
  97 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
  98 {
  99    p->current->header.access_mode = access_mode;
 100 }
 101
 102 void
 103 brw_set_compression_control(struct brw_compile *p,
 104                             enum brw_compression compression_control)
 105 {
 106    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 107
 108    if (p->brw->intel.gen >= 6) {
 109       /* Since we don't use the 32-wide support in gen6, we translate
 110        * the pre-gen6 compression control here.
 111        */
 112       switch (compression_control) {
 113       case BRW_COMPRESSION_NONE:
 114          /* This is the "use the first set of bits of dmask/vmask/arf
 115           * according to execsize" option.
 116           */
 117          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 118          break;
 119       case BRW_COMPRESSION_2NDHALF:
 120          /* For 8-wide, this is "use the second set of 8 bits." */
 121          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 122          break;
 123       case BRW_COMPRESSION_COMPRESSED:
 124          /* For 16-wide instruction compression, use the first set of 16 bits
 125           * since we don't do 32-wide dispatch.
 126           */
 127          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 128          break;
 129       default:
 130          assert(!"not reached");
 131          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 132          break;
 133       }
 134    } else {
 135       p->current->header.compression_control = compression_control;
 136    }
 137 }
 138
 139 void brw_set_mask_control( struct brw_compile *p, GLuint value )
 140 {
 141    p->current->header.mask_control = value;
 142 }
 143
 144 void brw_set_saturate( struct brw_compile *p, GLuint value )
 145 {
 146    p->current->header.saturate = value;
 147 }
 148
 149 void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
 150 {
 151    if (p->brw->intel.gen >= 6)
 152       p->current->header.acc_wr_control = value;
 153 }
 154
 155 void brw_push_insn_state( struct brw_compile *p )
 156 {
 157    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 158    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 159    p->compressed_stack[p->current - p->stack] = p->compressed;
 160    p->current++;
 161 }
 162
 163 void brw_pop_insn_state( struct brw_compile *p )
 164 {
 165    assert(p->current != p->stack);
 166    p->current--;
 167    p->compressed = p->compressed_stack[p->current - p->stack];
 168 }
 169
 170
 171 /***********************************************************************
 172  */
 173 void
 174 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 175 {
 176    p->brw = brw;
 177    p->nr_insn = 0;
 178    p->current = p->stack;
 179    p->compressed = false;
 180    memset(p->current, 0, sizeof(p->current[0]));
 181
 182    p->mem_ctx = mem_ctx;
 183
 184    /* Some defaults?
 185     */
 186    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 187    brw_set_saturate(p, 0);
 188    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 189    brw_set_predicate_control_flag_value(p, 0xff);
 190
 191    /* Set up control flow stack */
 192    p->if_stack_depth = 0;
 193    p->if_stack_array_size = 16;
 194    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 195
 196    p->loop_stack_depth = 0;
 197    p->loop_stack_array_size = 16;
 198    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 199    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 200 }
 201
 202
 203 const GLuint *brw_get_program( struct brw_compile *p,
 204                                GLuint *sz )
 205 {
 206    GLuint i;
 207
 208    for (i = 0; i < 8; i++)
 209       brw_NOP(p);
 210
 211    *sz = p->nr_insn * sizeof(struct brw_instruction);
 212    return (const GLuint *)p->store;
 213 }
 214
 215
 216
 217 /**
 218  * Subroutine calls require special attention.
 219  * Mesa instructions may be expanded into multiple hardware instructions
 220  * so the prog_instruction::BranchTarget field can't be used as an index
 221  * into the hardware instructions.
 222  *
 223  * The BranchTarget field isn't needed, however.  Mesa's GLSL compiler
 224  * emits CAL and BGNSUB instructions with labels that can be used to map
 225  * subroutine calls to actual subroutine code blocks.
 226  *
 227  * The structures and function here implement patching of CAL instructions
 228  * so they jump to the right subroutine code...
 229  */
 230
 231
 232 /**
 233  * For each OPCODE_BGNSUB we create one of these.
 234  */
 235 struct brw_glsl_label
 236 {
 237    const char *name; /**< the label string */
 238    GLuint position;  /**< the position of the brw instruction for this label */
 239    struct brw_glsl_label *next;  /**< next in linked list */
 240 };
 241
 242
 243 /**
 244  * For each OPCODE_CAL we create one of these.
 245  */
 246 struct brw_glsl_call
 247 {
 248    GLuint call_inst_pos;  /**< location of the CAL instruction */
 249    const char *sub_name;  /**< name of subroutine to call */
 250    struct brw_glsl_call *next;  /**< next in linked list */
 251 };
 252
 253
 254 /**
 255  * Called for each OPCODE_BGNSUB.
 256  */
 257 void
 258 brw_save_label(struct brw_compile *c, const char *name, GLuint position)
 259 {
 260    struct brw_glsl_label *label = CALLOC_STRUCT(brw_glsl_label);
 261    label->name = name;
 262    label->position = position;
 263    label->next = c->first_label;
 264    c->first_label = label;
 265 }
 266
 267
 268 /**
 269  * Called for each OPCODE_CAL.
 270  */
 271 void
 272 brw_save_call(struct brw_compile *c, const char *name, GLuint call_pos)
 273 {
 274    struct brw_glsl_call *call = CALLOC_STRUCT(brw_glsl_call);
 275    call->call_inst_pos = call_pos;
 276    call->sub_name = name;
 277    call->next = c->first_call;
 278    c->first_call = call;
 279 }
 280
 281
 282 /**
 283  * Lookup a label, return label's position/offset.
 284  */
 285 static GLuint
 286 brw_lookup_label(struct brw_compile *c, const char *name)
 287 {
 288    const struct brw_glsl_label *label;
 289    for (label = c->first_label; label; label = label->next) {
 290       if (strcmp(name, label->name) == 0) {
 291          return label->position;
 292       }
 293    }
 294    abort();  /* should never happen */
 295    return ~0;
 296 }
 297
 298
 299 /**
 300  * When we're done generating code, this function is called to resolve
 301  * subroutine calls.
 302  */
 303 void
 304 brw_resolve_cals(struct brw_compile *c)
 305 {
 306     const struct brw_glsl_call *call;
 307
 308     for (call = c->first_call; call; call = call->next) {
 309         const GLuint sub_loc = brw_lookup_label(c, call->sub_name);
 310         struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos];
 311         struct brw_instruction *brw_sub_inst = &c->store[sub_loc];
 312         GLint offset = brw_sub_inst - brw_call_inst;
 313
 314         /* patch brw_inst1 to point to brw_inst2 */
 315         brw_set_src1(c, brw_call_inst, brw_imm_d(offset * 16));
 316     }
 317
 318     /* free linked list of calls */
 319     {
 320         struct brw_glsl_call *call, *next;
 321         for (call = c->first_call; call; call = next) {
 322             next = call->next;
 323             free(call);
 324         }
 325         c->first_call = NULL;
 326     }
 327
 328     /* free linked list of labels */
 329     {
 330         struct brw_glsl_label *label, *next;
 331         for (label = c->first_label; label; label = next) {
 332             next = label->next;
 333             free(label);
 334         }
 335         c->first_label = NULL;
 336     }
 337 }