src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /* Returns the corresponding conditional mod for swapping src0 and
  40  * src1 in e.g. CMP.
  41  */
  42 uint32_t
  43 brw_swap_cmod(uint32_t cmod)
  44 {
  45    switch (cmod) {
  46    case BRW_CONDITIONAL_Z:
  47    case BRW_CONDITIONAL_NZ:
  48       return cmod;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62
  63 /* How does predicate control work when execution_size != 8?  Do I
  64  * need to test/set for 0xffff when execution_size is 16?
  65  */
  66 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
  67 {
  68    p->current->header.predicate_control = BRW_PREDICATE_NONE;
  69
  70    if (value != 0xff) {
  71       if (value != p->flag_value) {
  72          brw_push_insn_state(p);
  73          brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
  74          p->flag_value = value;
  75          brw_pop_insn_state(p);
  76       }
  77
  78       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
  79    }
  80 }
  81
  82 void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
  83 {
  84    p->current->header.predicate_control = pc;
  85 }
  86
  87 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  88 {
  89    p->current->header.predicate_inverse = predicate_inverse;
  90 }
  91
  92 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
  93 {
  94    p->current->header.destreg__conditionalmod = conditional;
  95 }
  96
  97 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
  98 {
  99    p->current->header.access_mode = access_mode;
 100 }
 101
 102 void
 103 brw_set_compression_control(struct brw_compile *p,
 104                             enum brw_compression compression_control)
 105 {
 106    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 107
 108    if (p->brw->intel.gen >= 6) {
 109       /* Since we don't use the 32-wide support in gen6, we translate
 110        * the pre-gen6 compression control here.
 111        */
 112       switch (compression_control) {
 113       case BRW_COMPRESSION_NONE:
 114          /* This is the "use the first set of bits of dmask/vmask/arf
 115           * according to execsize" option.
 116           */
 117          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 118          break;
 119       case BRW_COMPRESSION_2NDHALF:
 120          /* For 8-wide, this is "use the second set of 8 bits." */
 121          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 122          break;
 123       case BRW_COMPRESSION_COMPRESSED:
 124          /* For 16-wide instruction compression, use the first set of 16 bits
 125           * since we don't do 32-wide dispatch.
 126           */
 127          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 128          break;
 129       default:
 130          assert(!"not reached");
 131          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 132          break;
 133       }
 134    } else {
 135       p->current->header.compression_control = compression_control;
 136    }
 137 }
 138
 139 void brw_set_mask_control( struct brw_compile *p, GLuint value )
 140 {
 141    p->current->header.mask_control = value;
 142 }
 143
 144 void brw_set_saturate( struct brw_compile *p, GLuint value )
 145 {
 146    p->current->header.saturate = value;
 147 }
 148
 149 void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
 150 {
 151    if (p->brw->intel.gen >= 6)
 152       p->current->header.acc_wr_control = value;
 153 }
 154
 155 void brw_push_insn_state( struct brw_compile *p )
 156 {
 157    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 158    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 159    p->compressed_stack[p->current - p->stack] = p->compressed;
 160    p->current++;
 161 }
 162
 163 void brw_pop_insn_state( struct brw_compile *p )
 164 {
 165    assert(p->current != p->stack);
 166    p->current--;
 167    p->compressed = p->compressed_stack[p->current - p->stack];
 168 }
 169
 170
 171 /***********************************************************************
 172  */
 173 void
 174 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 175 {
 176    p->brw = brw;
 177    p->nr_insn = 0;
 178    p->current = p->stack;
 179    p->compressed = false;
 180    memset(p->current, 0, sizeof(p->current[0]));
 181
 182    p->mem_ctx = mem_ctx;
 183
 184    /* Some defaults?
 185     */
 186    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 187    brw_set_saturate(p, 0);
 188    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 189    brw_set_predicate_control_flag_value(p, 0xff);
 190
 191    /* Set up control flow stack */
 192    p->if_stack_depth = 0;
 193    p->if_stack_array_size = 16;
 194    p->if_stack =
 195       rzalloc_array(mem_ctx, struct brw_instruction *, p->if_stack_array_size);
 196 }
 197
 198
 199 const GLuint *brw_get_program( struct brw_compile *p,
 200                                GLuint *sz )
 201 {
 202    GLuint i;
 203
 204    for (i = 0; i < 8; i++)
 205       brw_NOP(p);
 206
 207    *sz = p->nr_insn * sizeof(struct brw_instruction);
 208    return (const GLuint *)p->store;
 209 }
 210
 211
 212
 213 /**
 214  * Subroutine calls require special attention.
 215  * Mesa instructions may be expanded into multiple hardware instructions
 216  * so the prog_instruction::BranchTarget field can't be used as an index
 217  * into the hardware instructions.
 218  *
 219  * The BranchTarget field isn't needed, however.  Mesa's GLSL compiler
 220  * emits CAL and BGNSUB instructions with labels that can be used to map
 221  * subroutine calls to actual subroutine code blocks.
 222  *
 223  * The structures and function here implement patching of CAL instructions
 224  * so they jump to the right subroutine code...
 225  */
 226
 227
 228 /**
 229  * For each OPCODE_BGNSUB we create one of these.
 230  */
 231 struct brw_glsl_label
 232 {
 233    const char *name; /**< the label string */
 234    GLuint position;  /**< the position of the brw instruction for this label */
 235    struct brw_glsl_label *next;  /**< next in linked list */
 236 };
 237
 238
 239 /**
 240  * For each OPCODE_CAL we create one of these.
 241  */
 242 struct brw_glsl_call
 243 {
 244    GLuint call_inst_pos;  /**< location of the CAL instruction */
 245    const char *sub_name;  /**< name of subroutine to call */
 246    struct brw_glsl_call *next;  /**< next in linked list */
 247 };
 248
 249
 250 /**
 251  * Called for each OPCODE_BGNSUB.
 252  */
 253 void
 254 brw_save_label(struct brw_compile *c, const char *name, GLuint position)
 255 {
 256    struct brw_glsl_label *label = CALLOC_STRUCT(brw_glsl_label);
 257    label->name = name;
 258    label->position = position;
 259    label->next = c->first_label;
 260    c->first_label = label;
 261 }
 262
 263
 264 /**
 265  * Called for each OPCODE_CAL.
 266  */
 267 void
 268 brw_save_call(struct brw_compile *c, const char *name, GLuint call_pos)
 269 {
 270    struct brw_glsl_call *call = CALLOC_STRUCT(brw_glsl_call);
 271    call->call_inst_pos = call_pos;
 272    call->sub_name = name;
 273    call->next = c->first_call;
 274    c->first_call = call;
 275 }
 276
 277
 278 /**
 279  * Lookup a label, return label's position/offset.
 280  */
 281 static GLuint
 282 brw_lookup_label(struct brw_compile *c, const char *name)
 283 {
 284    const struct brw_glsl_label *label;
 285    for (label = c->first_label; label; label = label->next) {
 286       if (strcmp(name, label->name) == 0) {
 287          return label->position;
 288       }
 289    }
 290    abort();  /* should never happen */
 291    return ~0;
 292 }
 293
 294
 295 /**
 296  * When we're done generating code, this function is called to resolve
 297  * subroutine calls.
 298  */
 299 void
 300 brw_resolve_cals(struct brw_compile *c)
 301 {
 302     const struct brw_glsl_call *call;
 303
 304     for (call = c->first_call; call; call = call->next) {
 305         const GLuint sub_loc = brw_lookup_label(c, call->sub_name);
 306         struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos];
 307         struct brw_instruction *brw_sub_inst = &c->store[sub_loc];
 308         GLint offset = brw_sub_inst - brw_call_inst;
 309
 310         /* patch brw_inst1 to point to brw_inst2 */
 311         brw_set_src1(c, brw_call_inst, brw_imm_d(offset * 16));
 312     }
 313
 314     /* free linked list of calls */
 315     {
 316         struct brw_glsl_call *call, *next;
 317         for (call = c->first_call; call; call = next) {
 318             next = call->next;
 319             free(call);
 320         }
 321         c->first_call = NULL;
 322     }
 323
 324     /* free linked list of labels */
 325     {
 326         struct brw_glsl_label *label, *next;
 327         for (label = c->first_label; label; label = next) {
 328             next = label->next;
 329             free(label);
 330         }
 331         c->first_label = NULL;
 332     }
 333 }