2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "brw_context.h"
34 #include "brw_defines.h"
37 #include "glsl/ralloc.h"
40 * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
42 * This is different than reg_encoding from brw_disasm.c in that it operates
43 * on the abstract enum values, rather than the generation-specific encoding.
46 brw_reg_type_letters(unsigned type
)
48 const char *names
[] = {
49 [BRW_REGISTER_TYPE_UD
] = "UD",
50 [BRW_REGISTER_TYPE_D
] = "D",
51 [BRW_REGISTER_TYPE_UW
] = "UW",
52 [BRW_REGISTER_TYPE_W
] = "W",
53 [BRW_REGISTER_TYPE_F
] = "F",
54 [BRW_REGISTER_TYPE_UB
] = "UB",
55 [BRW_REGISTER_TYPE_B
] = "B",
56 [BRW_REGISTER_TYPE_UV
] = "UV",
57 [BRW_REGISTER_TYPE_V
] = "V",
58 [BRW_REGISTER_TYPE_VF
] = "VF",
59 [BRW_REGISTER_TYPE_DF
] = "DF",
60 [BRW_REGISTER_TYPE_HF
] = "HF",
61 [BRW_REGISTER_TYPE_UQ
] = "UQ",
62 [BRW_REGISTER_TYPE_Q
] = "Q",
64 assert(type
<= BRW_REGISTER_TYPE_UQ
);
68 /* Returns the corresponding conditional mod for swapping src0 and
72 brw_swap_cmod(uint32_t cmod
)
75 case BRW_CONDITIONAL_Z
:
76 case BRW_CONDITIONAL_NZ
:
78 case BRW_CONDITIONAL_G
:
79 return BRW_CONDITIONAL_L
;
80 case BRW_CONDITIONAL_GE
:
81 return BRW_CONDITIONAL_LE
;
82 case BRW_CONDITIONAL_L
:
83 return BRW_CONDITIONAL_G
;
84 case BRW_CONDITIONAL_LE
:
85 return BRW_CONDITIONAL_GE
;
92 /* How does predicate control work when execution_size != 8? Do I
93 * need to test/set for 0xffff when execution_size is 16?
95 void brw_set_predicate_control_flag_value( struct brw_compile
*p
, unsigned value
)
97 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
100 if (value
!= p
->flag_value
) {
101 brw_push_insn_state(p
);
102 brw_MOV(p
, brw_flag_reg(0, 0), brw_imm_uw(value
));
103 p
->flag_value
= value
;
104 brw_pop_insn_state(p
);
107 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
111 void brw_set_predicate_control( struct brw_compile
*p
, unsigned pc
)
113 p
->current
->header
.predicate_control
= pc
;
116 void brw_set_predicate_inverse(struct brw_compile
*p
, bool predicate_inverse
)
118 p
->current
->header
.predicate_inverse
= predicate_inverse
;
121 void brw_set_conditionalmod( struct brw_compile
*p
, unsigned conditional
)
123 p
->current
->header
.destreg__conditionalmod
= conditional
;
126 void brw_set_flag_reg(struct brw_compile
*p
, int reg
, int subreg
)
128 p
->current
->bits2
.da1
.flag_reg_nr
= reg
;
129 p
->current
->bits2
.da1
.flag_subreg_nr
= subreg
;
132 void brw_set_access_mode( struct brw_compile
*p
, unsigned access_mode
)
134 p
->current
->header
.access_mode
= access_mode
;
138 brw_set_compression_control(struct brw_compile
*p
,
139 enum brw_compression compression_control
)
141 p
->compressed
= (compression_control
== BRW_COMPRESSION_COMPRESSED
);
143 if (p
->brw
->gen
>= 6) {
144 /* Since we don't use the SIMD32 support in gen6, we translate
145 * the pre-gen6 compression control here.
147 switch (compression_control
) {
148 case BRW_COMPRESSION_NONE
:
149 /* This is the "use the first set of bits of dmask/vmask/arf
150 * according to execsize" option.
152 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1Q
;
154 case BRW_COMPRESSION_2NDHALF
:
155 /* For SIMD8, this is "use the second set of 8 bits." */
156 p
->current
->header
.compression_control
= GEN6_COMPRESSION_2Q
;
158 case BRW_COMPRESSION_COMPRESSED
:
159 /* For SIMD16 instruction compression, use the first set of 16 bits
160 * since we don't do SIMD32 dispatch.
162 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1H
;
165 assert(!"not reached");
166 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1H
;
170 p
->current
->header
.compression_control
= compression_control
;
174 void brw_set_mask_control( struct brw_compile
*p
, unsigned value
)
176 p
->current
->header
.mask_control
= value
;
179 void brw_set_saturate( struct brw_compile
*p
, bool enable
)
181 p
->current
->header
.saturate
= enable
;
184 void brw_set_acc_write_control(struct brw_compile
*p
, unsigned value
)
186 if (p
->brw
->gen
>= 6)
187 p
->current
->header
.acc_wr_control
= value
;
190 void brw_push_insn_state( struct brw_compile
*p
)
192 assert(p
->current
!= &p
->stack
[BRW_EU_MAX_INSN_STACK
-1]);
193 memcpy(p
->current
+1, p
->current
, sizeof(struct brw_instruction
));
194 p
->compressed_stack
[p
->current
- p
->stack
] = p
->compressed
;
198 void brw_pop_insn_state( struct brw_compile
*p
)
200 assert(p
->current
!= p
->stack
);
202 p
->compressed
= p
->compressed_stack
[p
->current
- p
->stack
];
206 /***********************************************************************
209 brw_init_compile(struct brw_context
*brw
, struct brw_compile
*p
, void *mem_ctx
)
211 memset(p
, 0, sizeof(*p
));
215 * Set the initial instruction store array size to 1024, if found that
216 * isn't enough, then it will double the store size at brw_next_insn()
217 * until out of memory.
219 p
->store_size
= 1024;
220 p
->store
= rzalloc_array(mem_ctx
, struct brw_instruction
, p
->store_size
);
222 p
->current
= p
->stack
;
223 p
->compressed
= false;
224 memset(p
->current
, 0, sizeof(p
->current
[0]));
226 p
->mem_ctx
= mem_ctx
;
230 brw_set_mask_control(p
, BRW_MASK_ENABLE
); /* what does this do? */
231 brw_set_saturate(p
, 0);
232 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
233 brw_set_predicate_control_flag_value(p
, 0xff);
235 /* Set up control flow stack */
236 p
->if_stack_depth
= 0;
237 p
->if_stack_array_size
= 16;
238 p
->if_stack
= rzalloc_array(mem_ctx
, int, p
->if_stack_array_size
);
240 p
->loop_stack_depth
= 0;
241 p
->loop_stack_array_size
= 16;
242 p
->loop_stack
= rzalloc_array(mem_ctx
, int, p
->loop_stack_array_size
);
243 p
->if_depth_in_loop
= rzalloc_array(mem_ctx
, int, p
->loop_stack_array_size
);
245 brw_init_compaction_tables(brw
);
249 const unsigned *brw_get_program( struct brw_compile
*p
,
252 brw_compact_instructions(p
);
254 *sz
= p
->next_insn_offset
;
255 return (const unsigned *)p
->store
;
259 brw_dump_compile(struct brw_compile
*p
, FILE *out
, int start
, int end
)
261 struct brw_context
*brw
= p
->brw
;
262 void *store
= p
->store
;
263 bool dump_hex
= false;
265 for (int offset
= start
; offset
< end
;) {
266 struct brw_instruction
*insn
= store
+ offset
;
267 struct brw_instruction uncompacted
;
268 fprintf(out
, "0x%08x: ", offset
);
270 if (insn
->header
.cmpt_control
) {
271 struct brw_compact_instruction
*compacted
= (void *)insn
;
273 fprintf(out
, "0x%08x 0x%08x ",
274 ((uint32_t *)insn
)[1],
275 ((uint32_t *)insn
)[0]);
278 brw_uncompact_instruction(brw
, &uncompacted
, compacted
);
283 fprintf(out
, "0x%08x 0x%08x 0x%08x 0x%08x ",
284 ((uint32_t *)insn
)[3],
285 ((uint32_t *)insn
)[2],
286 ((uint32_t *)insn
)[1],
287 ((uint32_t *)insn
)[0]);
292 brw_disasm(out
, insn
, p
->brw
->gen
);