2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "brw_context.h"
34 #include "brw_defines.h"
37 #include "glsl/ralloc.h"
40 * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
42 * This is different than reg_encoding from brw_disasm.c in that it operates
43 * on the abstract enum values, rather than the generation-specific encoding.
46 brw_reg_type_letters(unsigned type
)
48 const char *names
[] = {
49 [BRW_REGISTER_TYPE_UD
] = "UD",
50 [BRW_REGISTER_TYPE_D
] = "D",
51 [BRW_REGISTER_TYPE_UW
] = "UW",
52 [BRW_REGISTER_TYPE_W
] = "W",
53 [BRW_REGISTER_TYPE_F
] = "F",
54 [BRW_REGISTER_TYPE_UB
] = "UB",
55 [BRW_REGISTER_TYPE_B
] = "B",
56 [BRW_REGISTER_TYPE_UV
] = "UV",
57 [BRW_REGISTER_TYPE_V
] = "V",
58 [BRW_REGISTER_TYPE_VF
] = "VF",
59 [BRW_REGISTER_TYPE_DF
] = "DF",
60 [BRW_REGISTER_TYPE_HF
] = "HF",
61 [BRW_REGISTER_TYPE_UQ
] = "UQ",
62 [BRW_REGISTER_TYPE_Q
] = "Q",
64 assert(type
<= BRW_REGISTER_TYPE_UQ
);
68 /* Returns the corresponding conditional mod for swapping src0 and
72 brw_swap_cmod(uint32_t cmod
)
75 case BRW_CONDITIONAL_Z
:
76 case BRW_CONDITIONAL_NZ
:
78 case BRW_CONDITIONAL_G
:
79 return BRW_CONDITIONAL_L
;
80 case BRW_CONDITIONAL_GE
:
81 return BRW_CONDITIONAL_LE
;
82 case BRW_CONDITIONAL_L
:
83 return BRW_CONDITIONAL_G
;
84 case BRW_CONDITIONAL_LE
:
85 return BRW_CONDITIONAL_GE
;
91 void brw_set_default_predicate_control( struct brw_compile
*p
, unsigned pc
)
93 p
->current
->header
.predicate_control
= pc
;
96 void brw_set_default_predicate_inverse(struct brw_compile
*p
, bool predicate_inverse
)
98 p
->current
->header
.predicate_inverse
= predicate_inverse
;
101 void brw_set_default_flag_reg(struct brw_compile
*p
, int reg
, int subreg
)
103 p
->current
->bits2
.da1
.flag_reg_nr
= reg
;
104 p
->current
->bits2
.da1
.flag_subreg_nr
= subreg
;
107 void brw_set_default_access_mode( struct brw_compile
*p
, unsigned access_mode
)
109 p
->current
->header
.access_mode
= access_mode
;
113 brw_set_default_compression_control(struct brw_compile
*p
,
114 enum brw_compression compression_control
)
116 struct brw_context
*brw
= p
->brw
;
118 p
->compressed
= (compression_control
== BRW_COMPRESSION_COMPRESSED
);
121 /* Since we don't use the SIMD32 support in gen6, we translate
122 * the pre-gen6 compression control here.
124 switch (compression_control
) {
125 case BRW_COMPRESSION_NONE
:
126 /* This is the "use the first set of bits of dmask/vmask/arf
127 * according to execsize" option.
129 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1Q
;
131 case BRW_COMPRESSION_2NDHALF
:
132 /* For SIMD8, this is "use the second set of 8 bits." */
133 p
->current
->header
.compression_control
= GEN6_COMPRESSION_2Q
;
135 case BRW_COMPRESSION_COMPRESSED
:
136 /* For SIMD16 instruction compression, use the first set of 16 bits
137 * since we don't do SIMD32 dispatch.
139 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1H
;
142 assert(!"not reached");
143 p
->current
->header
.compression_control
= GEN6_COMPRESSION_1H
;
147 p
->current
->header
.compression_control
= compression_control
;
151 void brw_set_default_mask_control( struct brw_compile
*p
, unsigned value
)
153 p
->current
->header
.mask_control
= value
;
156 void brw_set_default_saturate( struct brw_compile
*p
, bool enable
)
158 p
->current
->header
.saturate
= enable
;
161 void brw_set_default_acc_write_control(struct brw_compile
*p
, unsigned value
)
163 struct brw_context
*brw
= p
->brw
;
166 p
->current
->header
.acc_wr_control
= value
;
169 void brw_push_insn_state( struct brw_compile
*p
)
171 assert(p
->current
!= &p
->stack
[BRW_EU_MAX_INSN_STACK
-1]);
172 memcpy(p
->current
+1, p
->current
, sizeof(struct brw_instruction
));
173 p
->compressed_stack
[p
->current
- p
->stack
] = p
->compressed
;
177 void brw_pop_insn_state( struct brw_compile
*p
)
179 assert(p
->current
!= p
->stack
);
181 p
->compressed
= p
->compressed_stack
[p
->current
- p
->stack
];
185 /***********************************************************************
188 brw_init_compile(struct brw_context
*brw
, struct brw_compile
*p
, void *mem_ctx
)
190 memset(p
, 0, sizeof(*p
));
194 * Set the initial instruction store array size to 1024, if found that
195 * isn't enough, then it will double the store size at brw_next_insn()
196 * until out of memory.
198 p
->store_size
= 1024;
199 p
->store
= rzalloc_array(mem_ctx
, struct brw_instruction
, p
->store_size
);
201 p
->current
= p
->stack
;
202 p
->compressed
= false;
203 memset(p
->current
, 0, sizeof(p
->current
[0]));
205 p
->mem_ctx
= mem_ctx
;
209 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
); /* what does this do? */
210 brw_set_default_saturate(p
, 0);
211 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
213 /* Set up control flow stack */
214 p
->if_stack_depth
= 0;
215 p
->if_stack_array_size
= 16;
216 p
->if_stack
= rzalloc_array(mem_ctx
, int, p
->if_stack_array_size
);
218 p
->loop_stack_depth
= 0;
219 p
->loop_stack_array_size
= 16;
220 p
->loop_stack
= rzalloc_array(mem_ctx
, int, p
->loop_stack_array_size
);
221 p
->if_depth_in_loop
= rzalloc_array(mem_ctx
, int, p
->loop_stack_array_size
);
223 brw_init_compaction_tables(brw
);
227 const unsigned *brw_get_program( struct brw_compile
*p
,
230 *sz
= p
->next_insn_offset
;
231 return (const unsigned *)p
->store
;
235 brw_disassemble(struct brw_context
*brw
,
236 void *assembly
, int start
, int end
, FILE *out
)
238 bool dump_hex
= false;
240 for (int offset
= start
; offset
< end
;) {
241 struct brw_instruction
*insn
= assembly
+ offset
;
242 struct brw_instruction uncompacted
;
243 bool compacted
= insn
->header
.cmpt_control
;
244 fprintf(out
, "0x%08x: ", offset
);
246 if (insn
->header
.cmpt_control
) {
247 struct brw_compact_instruction
*compacted
= (void *)insn
;
249 fprintf(out
, "0x%08x 0x%08x ",
250 ((uint32_t *)insn
)[1],
251 ((uint32_t *)insn
)[0]);
254 brw_uncompact_instruction(brw
, &uncompacted
, compacted
);
259 fprintf(out
, "0x%08x 0x%08x 0x%08x 0x%08x ",
260 ((uint32_t *)insn
)[3],
261 ((uint32_t *)insn
)[2],
262 ((uint32_t *)insn
)[1],
263 ((uint32_t *)insn
)[0]);
268 brw_disassemble_inst(out
, insn
, brw
->gen
, compacted
);