src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /* Returns the corresponding conditional mod for swapping src0 and
  40  * src1 in e.g. CMP.
  41  */
  42 uint32_t
  43 brw_swap_cmod(uint32_t cmod)
  44 {
  45    switch (cmod) {
  46    case BRW_CONDITIONAL_Z:
  47    case BRW_CONDITIONAL_NZ:
  48       return cmod;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_L;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_LE;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_G;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_GE;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62
  63 /* How does predicate control work when execution_size != 8?  Do I
  64  * need to test/set for 0xffff when execution_size is 16?
  65  */
  66 void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value )
  67 {
  68    p->current->header.predicate_control = BRW_PREDICATE_NONE;
  69
  70    if (value != 0xff) {
  71       if (value != p->flag_value) {
  72          brw_push_insn_state(p);
  73          brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
  74          p->flag_value = value;
  75          brw_pop_insn_state(p);
  76       }
  77
  78       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
  79    }
  80 }
  81
  82 void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
  83 {
  84    p->current->header.predicate_control = pc;
  85 }
  86
  87 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  88 {
  89    p->current->header.predicate_inverse = predicate_inverse;
  90 }
  91
  92 void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
  93 {
  94    p->current->header.destreg__conditionalmod = conditional;
  95 }
  96
  97 void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
  98 {
  99    p->current->bits2.da1.flag_reg_nr = reg;
 100    p->current->bits2.da1.flag_subreg_nr = subreg;
 101 }
 102
 103 void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
 104 {
 105    p->current->header.access_mode = access_mode;
 106 }
 107
 108 void
 109 brw_set_compression_control(struct brw_compile *p,
 110                             enum brw_compression compression_control)
 111 {
 112    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 113
 114    if (p->brw->gen >= 6) {
 115       /* Since we don't use the 32-wide support in gen6, we translate
 116        * the pre-gen6 compression control here.
 117        */
 118       switch (compression_control) {
 119       case BRW_COMPRESSION_NONE:
 120          /* This is the "use the first set of bits of dmask/vmask/arf
 121           * according to execsize" option.
 122           */
 123          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 124          break;
 125       case BRW_COMPRESSION_2NDHALF:
 126          /* For 8-wide, this is "use the second set of 8 bits." */
 127          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 128          break;
 129       case BRW_COMPRESSION_COMPRESSED:
 130          /* For 16-wide instruction compression, use the first set of 16 bits
 131           * since we don't do 32-wide dispatch.
 132           */
 133          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 134          break;
 135       default:
 136          assert(!"not reached");
 137          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 138          break;
 139       }
 140    } else {
 141       p->current->header.compression_control = compression_control;
 142    }
 143 }
 144
 145 void brw_set_mask_control( struct brw_compile *p, unsigned value )
 146 {
 147    p->current->header.mask_control = value;
 148 }
 149
 150 void brw_set_saturate( struct brw_compile *p, bool enable )
 151 {
 152    p->current->header.saturate = enable;
 153 }
 154
 155 void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
 156 {
 157    if (p->brw->gen >= 6)
 158       p->current->header.acc_wr_control = value;
 159 }
 160
 161 void brw_push_insn_state( struct brw_compile *p )
 162 {
 163    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 164    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 165    p->compressed_stack[p->current - p->stack] = p->compressed;
 166    p->current++;
 167 }
 168
 169 void brw_pop_insn_state( struct brw_compile *p )
 170 {
 171    assert(p->current != p->stack);
 172    p->current--;
 173    p->compressed = p->compressed_stack[p->current - p->stack];
 174 }
 175
 176
 177 /***********************************************************************
 178  */
 179 void
 180 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 181 {
 182    memset(p, 0, sizeof(*p));
 183
 184    p->brw = brw;
 185    /*
 186     * Set the initial instruction store array size to 1024, if found that
 187     * isn't enough, then it will double the store size at brw_next_insn()
 188     * until out of memory.
 189     */
 190    p->store_size = 1024;
 191    p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
 192    p->nr_insn = 0;
 193    p->current = p->stack;
 194    p->compressed = false;
 195    memset(p->current, 0, sizeof(p->current[0]));
 196
 197    p->mem_ctx = mem_ctx;
 198
 199    /* Some defaults?
 200     */
 201    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 202    brw_set_saturate(p, 0);
 203    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 204    brw_set_predicate_control_flag_value(p, 0xff);
 205
 206    /* Set up control flow stack */
 207    p->if_stack_depth = 0;
 208    p->if_stack_array_size = 16;
 209    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 210
 211    p->loop_stack_depth = 0;
 212    p->loop_stack_array_size = 16;
 213    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 214    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 215
 216    brw_init_compaction_tables(brw);
 217 }
 218
 219
 220 const unsigned *brw_get_program( struct brw_compile *p,
 221                                unsigned *sz )
 222 {
 223    brw_compact_instructions(p);
 224
 225    *sz = p->next_insn_offset;
 226    return (const unsigned *)p->store;
 227 }
 228
 229 void
 230 brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
 231 {
 232    struct brw_context *brw = p->brw;
 233    void *store = p->store;
 234    bool dump_hex = false;
 235
 236    for (int offset = start; offset < end;) {
 237       struct brw_instruction *insn = store + offset;
 238       struct brw_instruction uncompacted;
 239       printf("0x%08x: ", offset);
 240
 241       if (insn->header.cmpt_control) {
 242          struct brw_compact_instruction *compacted = (void *)insn;
 243          if (dump_hex) {
 244             printf("0x%08x 0x%08x                       ",
 245                    ((uint32_t *)insn)[1],
 246                    ((uint32_t *)insn)[0]);
 247          }
 248
 249          brw_uncompact_instruction(brw, &uncompacted, compacted);
 250          insn = &uncompacted;
 251          offset += 8;
 252       } else {
 253          if (dump_hex) {
 254             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 255                    ((uint32_t *)insn)[3],
 256                    ((uint32_t *)insn)[2],
 257                    ((uint32_t *)insn)[1],
 258                    ((uint32_t *)insn)[0]);
 259          }
 260          offset += 16;
 261       }
 262
 263       brw_disasm(stdout, insn, p->brw->gen);
 264    }
 265 }