src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "util/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_UQ);
  65    return names[type];
  66 }
  67
  68 /* Returns a conditional modifier that negates the condition. */
  69 enum brw_conditional_mod
  70 brw_negate_cmod(uint32_t cmod)
  71 {
  72    switch (cmod) {
  73    case BRW_CONDITIONAL_Z:
  74       return BRW_CONDITIONAL_NZ;
  75    case BRW_CONDITIONAL_NZ:
  76       return BRW_CONDITIONAL_Z;
  77    case BRW_CONDITIONAL_G:
  78       return BRW_CONDITIONAL_LE;
  79    case BRW_CONDITIONAL_GE:
  80       return BRW_CONDITIONAL_L;
  81    case BRW_CONDITIONAL_L:
  82       return BRW_CONDITIONAL_GE;
  83    case BRW_CONDITIONAL_LE:
  84       return BRW_CONDITIONAL_G;
  85    default:
  86       return ~0;
  87    }
  88 }
  89
  90 /* Returns the corresponding conditional mod for swapping src0 and
  91  * src1 in e.g. CMP.
  92  */
  93 enum brw_conditional_mod
  94 brw_swap_cmod(uint32_t cmod)
  95 {
  96    switch (cmod) {
  97    case BRW_CONDITIONAL_Z:
  98    case BRW_CONDITIONAL_NZ:
  99       return cmod;
 100    case BRW_CONDITIONAL_G:
 101       return BRW_CONDITIONAL_L;
 102    case BRW_CONDITIONAL_GE:
 103       return BRW_CONDITIONAL_LE;
 104    case BRW_CONDITIONAL_L:
 105       return BRW_CONDITIONAL_G;
 106    case BRW_CONDITIONAL_LE:
 107       return BRW_CONDITIONAL_GE;
 108    default:
 109       return BRW_CONDITIONAL_NONE;
 110    }
 111 }
 112
 113 void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
 114 {
 115    brw_inst_set_pred_control(p->brw, p->current, pc);
 116 }
 117
 118 void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
 119 {
 120    brw_inst_set_pred_inv(p->brw, p->current, predicate_inverse);
 121 }
 122
 123 void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
 124 {
 125    if (p->brw->gen >= 7)
 126       brw_inst_set_flag_reg_nr(p->brw, p->current, reg);
 127
 128    brw_inst_set_flag_subreg_nr(p->brw, p->current, subreg);
 129 }
 130
 131 void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
 132 {
 133    brw_inst_set_access_mode(p->brw, p->current, access_mode);
 134 }
 135
 136 void
 137 brw_set_default_compression_control(struct brw_compile *p,
 138                             enum brw_compression compression_control)
 139 {
 140    struct brw_context *brw = p->brw;
 141
 142    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 143
 144    if (brw->gen >= 6) {
 145       /* Since we don't use the SIMD32 support in gen6, we translate
 146        * the pre-gen6 compression control here.
 147        */
 148       switch (compression_control) {
 149       case BRW_COMPRESSION_NONE:
 150          /* This is the "use the first set of bits of dmask/vmask/arf
 151           * according to execsize" option.
 152           */
 153          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1Q);
 154          break;
 155       case BRW_COMPRESSION_2NDHALF:
 156          /* For SIMD8, this is "use the second set of 8 bits." */
 157          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_2Q);
 158          break;
 159       case BRW_COMPRESSION_COMPRESSED:
 160          /* For SIMD16 instruction compression, use the first set of 16 bits
 161           * since we don't do SIMD32 dispatch.
 162           */
 163          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
 164          break;
 165       default:
 166          unreachable("not reached");
 167       }
 168    } else {
 169       brw_inst_set_qtr_control(brw, p->current, compression_control);
 170    }
 171 }
 172
 173 void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
 174 {
 175    brw_inst_set_mask_control(p->brw, p->current, value);
 176 }
 177
 178 void brw_set_default_saturate( struct brw_compile *p, bool enable )
 179 {
 180    brw_inst_set_saturate(p->brw, p->current, enable);
 181 }
 182
 183 void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
 184 {
 185    struct brw_context *brw = p->brw;
 186
 187    if (brw->gen >= 6)
 188       brw_inst_set_acc_wr_control(p->brw, p->current, value);
 189 }
 190
 191 void brw_push_insn_state( struct brw_compile *p )
 192 {
 193    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 194    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 195    p->compressed_stack[p->current - p->stack] = p->compressed;
 196    p->current++;
 197 }
 198
 199 void brw_pop_insn_state( struct brw_compile *p )
 200 {
 201    assert(p->current != p->stack);
 202    p->current--;
 203    p->compressed = p->compressed_stack[p->current - p->stack];
 204 }
 205
 206
 207 /***********************************************************************
 208  */
 209 void
 210 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 211 {
 212    memset(p, 0, sizeof(*p));
 213
 214    p->brw = brw;
 215    /*
 216     * Set the initial instruction store array size to 1024, if found that
 217     * isn't enough, then it will double the store size at brw_next_insn()
 218     * until out of memory.
 219     */
 220    p->store_size = 1024;
 221    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 222    p->nr_insn = 0;
 223    p->current = p->stack;
 224    p->compressed = false;
 225    memset(p->current, 0, sizeof(p->current[0]));
 226
 227    p->mem_ctx = mem_ctx;
 228
 229    /* Some defaults?
 230     */
 231    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 232    brw_set_default_saturate(p, 0);
 233    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 234
 235    /* Set up control flow stack */
 236    p->if_stack_depth = 0;
 237    p->if_stack_array_size = 16;
 238    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 239
 240    p->loop_stack_depth = 0;
 241    p->loop_stack_array_size = 16;
 242    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 243    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 244
 245    brw_init_compaction_tables(brw);
 246 }
 247
 248
 249 const unsigned *brw_get_program( struct brw_compile *p,
 250                                unsigned *sz )
 251 {
 252    *sz = p->next_insn_offset;
 253    return (const unsigned *)p->store;
 254 }
 255
 256 void
 257 brw_disassemble(struct brw_context *brw,
 258                 void *assembly, int start, int end, FILE *out)
 259 {
 260    bool dump_hex = false;
 261
 262    for (int offset = start; offset < end;) {
 263       brw_inst *insn = assembly + offset;
 264       brw_inst uncompacted;
 265       bool compacted = brw_inst_cmpt_control(brw, insn);
 266       if (0)
 267          fprintf(out, "0x%08x: ", offset);
 268
 269       if (compacted) {
 270          brw_compact_inst *compacted = (void *)insn;
 271          if (dump_hex) {
 272             fprintf(out, "0x%08x 0x%08x                       ",
 273                     ((uint32_t *)insn)[1],
 274                     ((uint32_t *)insn)[0]);
 275          }
 276
 277          brw_uncompact_instruction(brw, &uncompacted, compacted);
 278          insn = &uncompacted;
 279          offset += 8;
 280       } else {
 281          if (dump_hex) {
 282             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 283                     ((uint32_t *)insn)[3],
 284                     ((uint32_t *)insn)[2],
 285                     ((uint32_t *)insn)[1],
 286                     ((uint32_t *)insn)[0]);
 287          }
 288          offset += 16;
 289       }
 290
 291       brw_disassemble_inst(out, brw, insn, compacted);
 292    }
 293 }