src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_UQ);
  65    return names[type];
  66 }
  67
  68 /* Returns the corresponding conditional mod for swapping src0 and
  69  * src1 in e.g. CMP.
  70  */
  71 uint32_t
  72 brw_swap_cmod(uint32_t cmod)
  73 {
  74    switch (cmod) {
  75    case BRW_CONDITIONAL_Z:
  76    case BRW_CONDITIONAL_NZ:
  77       return cmod;
  78    case BRW_CONDITIONAL_G:
  79       return BRW_CONDITIONAL_L;
  80    case BRW_CONDITIONAL_GE:
  81       return BRW_CONDITIONAL_LE;
  82    case BRW_CONDITIONAL_L:
  83       return BRW_CONDITIONAL_G;
  84    case BRW_CONDITIONAL_LE:
  85       return BRW_CONDITIONAL_GE;
  86    default:
  87       return ~0;
  88    }
  89 }
  90
  91 void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc )
  92 {
  93    brw_inst_set_pred_control(p->brw, p->current, pc);
  94 }
  95
  96 void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  97 {
  98    brw_inst_set_pred_inv(p->brw, p->current, predicate_inverse);
  99 }
 100
 101 void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg)
 102 {
 103    if (p->brw->gen >= 7)
 104       brw_inst_set_flag_reg_nr(p->brw, p->current, reg);
 105
 106    brw_inst_set_flag_subreg_nr(p->brw, p->current, subreg);
 107 }
 108
 109 void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode )
 110 {
 111    brw_inst_set_access_mode(p->brw, p->current, access_mode);
 112 }
 113
 114 void
 115 brw_set_default_compression_control(struct brw_compile *p,
 116                             enum brw_compression compression_control)
 117 {
 118    struct brw_context *brw = p->brw;
 119
 120    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 121
 122    if (brw->gen >= 6) {
 123       /* Since we don't use the SIMD32 support in gen6, we translate
 124        * the pre-gen6 compression control here.
 125        */
 126       switch (compression_control) {
 127       case BRW_COMPRESSION_NONE:
 128          /* This is the "use the first set of bits of dmask/vmask/arf
 129           * according to execsize" option.
 130           */
 131          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1Q);
 132          break;
 133       case BRW_COMPRESSION_2NDHALF:
 134          /* For SIMD8, this is "use the second set of 8 bits." */
 135          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_2Q);
 136          break;
 137       case BRW_COMPRESSION_COMPRESSED:
 138          /* For SIMD16 instruction compression, use the first set of 16 bits
 139           * since we don't do SIMD32 dispatch.
 140           */
 141          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
 142          break;
 143       default:
 144          assert(!"not reached");
 145          brw_inst_set_qtr_control(brw, p->current, GEN6_COMPRESSION_1H);
 146          break;
 147       }
 148    } else {
 149       brw_inst_set_qtr_control(brw, p->current, compression_control);
 150    }
 151 }
 152
 153 void brw_set_default_mask_control( struct brw_compile *p, unsigned value )
 154 {
 155    brw_inst_set_mask_control(p->brw, p->current, value);
 156 }
 157
 158 void brw_set_default_saturate( struct brw_compile *p, bool enable )
 159 {
 160    brw_inst_set_saturate(p->brw, p->current, enable);
 161 }
 162
 163 void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value)
 164 {
 165    struct brw_context *brw = p->brw;
 166
 167    if (brw->gen >= 6)
 168       brw_inst_set_acc_wr_control(p->brw, p->current, value);
 169 }
 170
 171 void brw_push_insn_state( struct brw_compile *p )
 172 {
 173    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 174    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 175    p->compressed_stack[p->current - p->stack] = p->compressed;
 176    p->current++;
 177 }
 178
 179 void brw_pop_insn_state( struct brw_compile *p )
 180 {
 181    assert(p->current != p->stack);
 182    p->current--;
 183    p->compressed = p->compressed_stack[p->current - p->stack];
 184 }
 185
 186
 187 /***********************************************************************
 188  */
 189 void
 190 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 191 {
 192    memset(p, 0, sizeof(*p));
 193
 194    p->brw = brw;
 195    /*
 196     * Set the initial instruction store array size to 1024, if found that
 197     * isn't enough, then it will double the store size at brw_next_insn()
 198     * until out of memory.
 199     */
 200    p->store_size = 1024;
 201    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 202    p->nr_insn = 0;
 203    p->current = p->stack;
 204    p->compressed = false;
 205    memset(p->current, 0, sizeof(p->current[0]));
 206
 207    p->mem_ctx = mem_ctx;
 208
 209    /* Some defaults?
 210     */
 211    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 212    brw_set_default_saturate(p, 0);
 213    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 214
 215    /* Set up control flow stack */
 216    p->if_stack_depth = 0;
 217    p->if_stack_array_size = 16;
 218    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 219
 220    p->loop_stack_depth = 0;
 221    p->loop_stack_array_size = 16;
 222    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 223    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 224
 225    brw_init_compaction_tables(brw);
 226 }
 227
 228
 229 const unsigned *brw_get_program( struct brw_compile *p,
 230                                unsigned *sz )
 231 {
 232    *sz = p->next_insn_offset;
 233    return (const unsigned *)p->store;
 234 }
 235
 236 void
 237 brw_disassemble(struct brw_context *brw,
 238                 void *assembly, int start, int end, FILE *out)
 239 {
 240    bool dump_hex = false;
 241
 242    for (int offset = start; offset < end;) {
 243       brw_inst *insn = assembly + offset;
 244       brw_inst uncompacted;
 245       bool compacted = brw_inst_cmpt_control(brw, insn);
 246       fprintf(out, "0x%08x: ", offset);
 247
 248       if (compacted) {
 249          struct brw_compact_instruction *compacted = (void *)insn;
 250          if (dump_hex) {
 251             fprintf(out, "0x%08x 0x%08x                       ",
 252                     ((uint32_t *)insn)[1],
 253                     ((uint32_t *)insn)[0]);
 254          }
 255
 256          brw_uncompact_instruction(brw, &uncompacted, compacted);
 257          insn = &uncompacted;
 258          offset += 8;
 259       } else {
 260          if (dump_hex) {
 261             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 262                     ((uint32_t *)insn)[3],
 263                     ((uint32_t *)insn)[2],
 264                     ((uint32_t *)insn)[1],
 265                     ((uint32_t *)insn)[0]);
 266          }
 267          offset += 16;
 268       }
 269
 270       brw_disassemble_inst(out, brw, insn, compacted);
 271    }
 272 }