i965/fs: Constant-fold immediates in src0 of CMP instructions.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "brw_context.h"
34 #include "brw_defines.h"
35 #include "brw_eu.h"
36
37 /* Returns the corresponding conditional mod for swapping src0 and
38 * src1 in e.g. CMP.
39 */
40 uint32_t
41 brw_swap_cmod(uint32_t cmod)
42 {
43 switch (cmod) {
44 case BRW_CONDITIONAL_Z:
45 case BRW_CONDITIONAL_NZ:
46 return cmod;
47 case BRW_CONDITIONAL_G:
48 return BRW_CONDITIONAL_LE;
49 case BRW_CONDITIONAL_GE:
50 return BRW_CONDITIONAL_L;
51 case BRW_CONDITIONAL_L:
52 return BRW_CONDITIONAL_GE;
53 case BRW_CONDITIONAL_LE:
54 return BRW_CONDITIONAL_G;
55 default:
56 return ~0;
57 }
58 }
59
60
61 /* How does predicate control work when execution_size != 8? Do I
62 * need to test/set for 0xffff when execution_size is 16?
63 */
64 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
65 {
66 p->current->header.predicate_control = BRW_PREDICATE_NONE;
67
68 if (value != 0xff) {
69 if (value != p->flag_value) {
70 brw_push_insn_state(p);
71 brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
72 p->flag_value = value;
73 brw_pop_insn_state(p);
74 }
75
76 p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
77 }
78 }
79
80 void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
81 {
82 p->current->header.predicate_control = pc;
83 }
84
85 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
86 {
87 p->current->header.destreg__conditionalmod = conditional;
88 }
89
90 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
91 {
92 p->current->header.access_mode = access_mode;
93 }
94
95 void brw_set_compression_control( struct brw_compile *p, GLboolean compression_control )
96 {
97 p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
98
99 if (p->brw->intel.gen >= 6) {
100 /* Since we don't use the 32-wide support in gen6, we translate
101 * the pre-gen6 compression control here.
102 */
103 switch (compression_control) {
104 case BRW_COMPRESSION_NONE:
105 /* This is the "use the first set of bits of dmask/vmask/arf
106 * according to execsize" option.
107 */
108 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
109 break;
110 case BRW_COMPRESSION_2NDHALF:
111 /* For 8-wide, this is "use the second set of 8 bits." */
112 p->current->header.compression_control = GEN6_COMPRESSION_2Q;
113 break;
114 case BRW_COMPRESSION_COMPRESSED:
115 /* For 16-wide instruction compression, use the first set of 16 bits
116 * since we don't do 32-wide dispatch.
117 */
118 p->current->header.compression_control = GEN6_COMPRESSION_1H;
119 break;
120 default:
121 assert(!"not reached");
122 p->current->header.compression_control = GEN6_COMPRESSION_1H;
123 break;
124 }
125 } else {
126 p->current->header.compression_control = compression_control;
127 }
128 }
129
130 void brw_set_mask_control( struct brw_compile *p, GLuint value )
131 {
132 p->current->header.mask_control = value;
133 }
134
135 void brw_set_saturate( struct brw_compile *p, GLuint value )
136 {
137 p->current->header.saturate = value;
138 }
139
140 void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
141 {
142 if (p->brw->intel.gen >= 6)
143 p->current->header.acc_wr_control = value;
144 }
145
146 void brw_push_insn_state( struct brw_compile *p )
147 {
148 assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
149 memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
150 p->compressed_stack[p->current - p->stack] = p->compressed;
151 p->current++;
152 }
153
154 void brw_pop_insn_state( struct brw_compile *p )
155 {
156 assert(p->current != p->stack);
157 p->current--;
158 p->compressed = p->compressed_stack[p->current - p->stack];
159 }
160
161
162 /***********************************************************************
163 */
164 void brw_init_compile( struct brw_context *brw, struct brw_compile *p )
165 {
166 p->brw = brw;
167 p->nr_insn = 0;
168 p->current = p->stack;
169 p->compressed = false;
170 memset(p->current, 0, sizeof(p->current[0]));
171
172 /* Some defaults?
173 */
174 brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
175 brw_set_saturate(p, 0);
176 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
177 brw_set_predicate_control_flag_value(p, 0xff);
178 }
179
180
181 const GLuint *brw_get_program( struct brw_compile *p,
182 GLuint *sz )
183 {
184 GLuint i;
185
186 for (i = 0; i < 8; i++)
187 brw_NOP(p);
188
189 *sz = p->nr_insn * sizeof(struct brw_instruction);
190 return (const GLuint *)p->store;
191 }
192
193
194
195 /**
196 * Subroutine calls require special attention.
197 * Mesa instructions may be expanded into multiple hardware instructions
198 * so the prog_instruction::BranchTarget field can't be used as an index
199 * into the hardware instructions.
200 *
201 * The BranchTarget field isn't needed, however. Mesa's GLSL compiler
202 * emits CAL and BGNSUB instructions with labels that can be used to map
203 * subroutine calls to actual subroutine code blocks.
204 *
205 * The structures and function here implement patching of CAL instructions
206 * so they jump to the right subroutine code...
207 */
208
209
210 /**
211 * For each OPCODE_BGNSUB we create one of these.
212 */
213 struct brw_glsl_label
214 {
215 const char *name; /**< the label string */
216 GLuint position; /**< the position of the brw instruction for this label */
217 struct brw_glsl_label *next; /**< next in linked list */
218 };
219
220
221 /**
222 * For each OPCODE_CAL we create one of these.
223 */
224 struct brw_glsl_call
225 {
226 GLuint call_inst_pos; /**< location of the CAL instruction */
227 const char *sub_name; /**< name of subroutine to call */
228 struct brw_glsl_call *next; /**< next in linked list */
229 };
230
231
232 /**
233 * Called for each OPCODE_BGNSUB.
234 */
235 void
236 brw_save_label(struct brw_compile *c, const char *name, GLuint position)
237 {
238 struct brw_glsl_label *label = CALLOC_STRUCT(brw_glsl_label);
239 label->name = name;
240 label->position = position;
241 label->next = c->first_label;
242 c->first_label = label;
243 }
244
245
246 /**
247 * Called for each OPCODE_CAL.
248 */
249 void
250 brw_save_call(struct brw_compile *c, const char *name, GLuint call_pos)
251 {
252 struct brw_glsl_call *call = CALLOC_STRUCT(brw_glsl_call);
253 call->call_inst_pos = call_pos;
254 call->sub_name = name;
255 call->next = c->first_call;
256 c->first_call = call;
257 }
258
259
260 /**
261 * Lookup a label, return label's position/offset.
262 */
263 static GLuint
264 brw_lookup_label(struct brw_compile *c, const char *name)
265 {
266 const struct brw_glsl_label *label;
267 for (label = c->first_label; label; label = label->next) {
268 if (strcmp(name, label->name) == 0) {
269 return label->position;
270 }
271 }
272 abort(); /* should never happen */
273 return ~0;
274 }
275
276
277 /**
278 * When we're done generating code, this function is called to resolve
279 * subroutine calls.
280 */
281 void
282 brw_resolve_cals(struct brw_compile *c)
283 {
284 const struct brw_glsl_call *call;
285
286 for (call = c->first_call; call; call = call->next) {
287 const GLuint sub_loc = brw_lookup_label(c, call->sub_name);
288 struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos];
289 struct brw_instruction *brw_sub_inst = &c->store[sub_loc];
290 GLint offset = brw_sub_inst - brw_call_inst;
291
292 /* patch brw_inst1 to point to brw_inst2 */
293 brw_set_src1(brw_call_inst, brw_imm_d(offset * 16));
294 }
295
296 /* free linked list of calls */
297 {
298 struct brw_glsl_call *call, *next;
299 for (call = c->first_call; call; call = next) {
300 next = call->next;
301 free(call);
302 }
303 c->first_call = NULL;
304 }
305
306 /* free linked list of labels */
307 {
308 struct brw_glsl_label *label, *next;
309 for (label = c->first_label; label; label = next) {
310 next = label->next;
311 free(label);
312 }
313 c->first_label = NULL;
314 }
315 }