src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "../glsl/ralloc.h"
  38
  39 /* Returns the corresponding conditional mod for swapping src0 and
  40  * src1 in e.g. CMP.
  41  */
  42 uint32_t
  43 brw_swap_cmod(uint32_t cmod)
  44 {
  45    switch (cmod) {
  46    case BRW_CONDITIONAL_Z:
  47    case BRW_CONDITIONAL_NZ:
  48       return cmod;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62
  63 /* How does predicate control work when execution_size != 8?  Do I
  64  * need to test/set for 0xffff when execution_size is 16?
  65  */
  66 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
  67 {
  68    p->current->header.predicate_control = BRW_PREDICATE_NONE;
  69
  70    if (value != 0xff) {
  71       if (value != p->flag_value) {
  72          brw_push_insn_state(p);
  73          brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
  74          p->flag_value = value;
  75          brw_pop_insn_state(p);
  76       }
  77
  78       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
  79    }
  80 }
  81
  82 void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
  83 {
  84    p->current->header.predicate_control = pc;
  85 }
  86
  87 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  88 {
  89    p->current->header.predicate_inverse = predicate_inverse;
  90 }
  91
  92 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
  93 {
  94    p->current->header.destreg__conditionalmod = conditional;
  95 }
  96
  97 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
  98 {
  99    p->current->header.access_mode = access_mode;
 100 }
 101
 102 void brw_set_compression_control( struct brw_compile *p, GLboolean compression_control )
 103 {
 104    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 105
 106    if (p->brw->intel.gen >= 6) {
 107       /* Since we don't use the 32-wide support in gen6, we translate
 108        * the pre-gen6 compression control here.
 109        */
 110       switch (compression_control) {
 111       case BRW_COMPRESSION_NONE:
 112          /* This is the "use the first set of bits of dmask/vmask/arf
 113           * according to execsize" option.
 114           */
 115          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 116          break;
 117       case BRW_COMPRESSION_2NDHALF:
 118          /* For 8-wide, this is "use the second set of 8 bits." */
 119          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 120          break;
 121       case BRW_COMPRESSION_COMPRESSED:
 122          /* For 16-wide instruction compression, use the first set of 16 bits
 123           * since we don't do 32-wide dispatch.
 124           */
 125          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 126          break;
 127       default:
 128          assert(!"not reached");
 129          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 130          break;
 131       }
 132    } else {
 133       p->current->header.compression_control = compression_control;
 134    }
 135 }
 136
 137 void brw_set_mask_control( struct brw_compile *p, GLuint value )
 138 {
 139    p->current->header.mask_control = value;
 140 }
 141
 142 void brw_set_saturate( struct brw_compile *p, GLuint value )
 143 {
 144    p->current->header.saturate = value;
 145 }
 146
 147 void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
 148 {
 149    if (p->brw->intel.gen >= 6)
 150       p->current->header.acc_wr_control = value;
 151 }
 152
 153 void brw_push_insn_state( struct brw_compile *p )
 154 {
 155    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 156    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 157    p->compressed_stack[p->current - p->stack] = p->compressed;
 158    p->current++;
 159 }
 160
 161 void brw_pop_insn_state( struct brw_compile *p )
 162 {
 163    assert(p->current != p->stack);
 164    p->current--;
 165    p->compressed = p->compressed_stack[p->current - p->stack];
 166 }
 167
 168
 169 /***********************************************************************
 170  */
 171 void
 172 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 173 {
 174    p->brw = brw;
 175    p->nr_insn = 0;
 176    p->current = p->stack;
 177    p->compressed = false;
 178    memset(p->current, 0, sizeof(p->current[0]));
 179
 180    p->mem_ctx = mem_ctx;
 181
 182    /* Some defaults?
 183     */
 184    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 185    brw_set_saturate(p, 0);
 186    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 187    brw_set_predicate_control_flag_value(p, 0xff);
 188
 189    /* Set up control flow stack */
 190    p->if_stack_depth = 0;
 191    p->if_stack_array_size = 16;
 192    p->if_stack =
 193       rzalloc_array(mem_ctx, struct brw_instruction *, p->if_stack_array_size);
 194 }
 195
 196
 197 const GLuint *brw_get_program( struct brw_compile *p,
 198                                GLuint *sz )
 199 {
 200    GLuint i;
 201
 202    for (i = 0; i < 8; i++)
 203       brw_NOP(p);
 204
 205    *sz = p->nr_insn * sizeof(struct brw_instruction);
 206    return (const GLuint *)p->store;
 207 }
 208
 209
 210
 211 /**
 212  * Subroutine calls require special attention.
 213  * Mesa instructions may be expanded into multiple hardware instructions
 214  * so the prog_instruction::BranchTarget field can't be used as an index
 215  * into the hardware instructions.
 216  *
 217  * The BranchTarget field isn't needed, however.  Mesa's GLSL compiler
 218  * emits CAL and BGNSUB instructions with labels that can be used to map
 219  * subroutine calls to actual subroutine code blocks.
 220  *
 221  * The structures and function here implement patching of CAL instructions
 222  * so they jump to the right subroutine code...
 223  */
 224
 225
 226 /**
 227  * For each OPCODE_BGNSUB we create one of these.
 228  */
 229 struct brw_glsl_label
 230 {
 231    const char *name; /**< the label string */
 232    GLuint position;  /**< the position of the brw instruction for this label */
 233    struct brw_glsl_label *next;  /**< next in linked list */
 234 };
 235
 236
 237 /**
 238  * For each OPCODE_CAL we create one of these.
 239  */
 240 struct brw_glsl_call
 241 {
 242    GLuint call_inst_pos;  /**< location of the CAL instruction */
 243    const char *sub_name;  /**< name of subroutine to call */
 244    struct brw_glsl_call *next;  /**< next in linked list */
 245 };
 246
 247
 248 /**
 249  * Called for each OPCODE_BGNSUB.
 250  */
 251 void
 252 brw_save_label(struct brw_compile *c, const char *name, GLuint position)
 253 {
 254    struct brw_glsl_label *label = CALLOC_STRUCT(brw_glsl_label);
 255    label->name = name;
 256    label->position = position;
 257    label->next = c->first_label;
 258    c->first_label = label;
 259 }
 260
 261
 262 /**
 263  * Called for each OPCODE_CAL.
 264  */
 265 void
 266 brw_save_call(struct brw_compile *c, const char *name, GLuint call_pos)
 267 {
 268    struct brw_glsl_call *call = CALLOC_STRUCT(brw_glsl_call);
 269    call->call_inst_pos = call_pos;
 270    call->sub_name = name;
 271    call->next = c->first_call;
 272    c->first_call = call;
 273 }
 274
 275
 276 /**
 277  * Lookup a label, return label's position/offset.
 278  */
 279 static GLuint
 280 brw_lookup_label(struct brw_compile *c, const char *name)
 281 {
 282    const struct brw_glsl_label *label;
 283    for (label = c->first_label; label; label = label->next) {
 284       if (strcmp(name, label->name) == 0) {
 285          return label->position;
 286       }
 287    }
 288    abort();  /* should never happen */
 289    return ~0;
 290 }
 291
 292
 293 /**
 294  * When we're done generating code, this function is called to resolve
 295  * subroutine calls.
 296  */
 297 void
 298 brw_resolve_cals(struct brw_compile *c)
 299 {
 300     const struct brw_glsl_call *call;
 301
 302     for (call = c->first_call; call; call = call->next) {
 303         const GLuint sub_loc = brw_lookup_label(c, call->sub_name);
 304         struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos];
 305         struct brw_instruction *brw_sub_inst = &c->store[sub_loc];
 306         GLint offset = brw_sub_inst - brw_call_inst;
 307
 308         /* patch brw_inst1 to point to brw_inst2 */
 309         brw_set_src1(c, brw_call_inst, brw_imm_d(offset * 16));
 310     }
 311
 312     /* free linked list of calls */
 313     {
 314         struct brw_glsl_call *call, *next;
 315         for (call = c->first_call; call; call = next) {
 316             next = call->next;
 317             free(call);
 318         }
 319         c->first_call = NULL;
 320     }
 321
 322     /* free linked list of labels */
 323     {
 324         struct brw_glsl_label *label, *next;
 325         for (label = c->first_label; label; label = next) {
 326             next = label->next;
 327             free(label);
 328         }
 329         c->first_label = NULL;
 330     }
 331 }