src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_UQ);
  65    return names[type];
  66 }
  67
  68 /* Returns the corresponding conditional mod for swapping src0 and
  69  * src1 in e.g. CMP.
  70  */
  71 uint32_t
  72 brw_swap_cmod(uint32_t cmod)
  73 {
  74    switch (cmod) {
  75    case BRW_CONDITIONAL_Z:
  76    case BRW_CONDITIONAL_NZ:
  77       return cmod;
  78    case BRW_CONDITIONAL_G:
  79       return BRW_CONDITIONAL_L;
  80    case BRW_CONDITIONAL_GE:
  81       return BRW_CONDITIONAL_LE;
  82    case BRW_CONDITIONAL_L:
  83       return BRW_CONDITIONAL_G;
  84    case BRW_CONDITIONAL_LE:
  85       return BRW_CONDITIONAL_GE;
  86    default:
  87       return ~0;
  88    }
  89 }
  90
  91
  92 /* How does predicate control work when execution_size != 8?  Do I
  93  * need to test/set for 0xffff when execution_size is 16?
  94  */
  95 void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value )
  96 {
  97    p->current->header.predicate_control = BRW_PREDICATE_NONE;
  98
  99    if (value != 0xff) {
 100       if (value != p->flag_value) {
 101          brw_push_insn_state(p);
 102          brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
 103          p->flag_value = value;
 104          brw_pop_insn_state(p);
 105       }
 106
 107       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
 108    }
 109 }
 110
 111 void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
 112 {
 113    p->current->header.predicate_control = pc;
 114 }
 115
 116 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
 117 {
 118    p->current->header.predicate_inverse = predicate_inverse;
 119 }
 120
 121 void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
 122 {
 123    p->current->header.destreg__conditionalmod = conditional;
 124 }
 125
 126 void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
 127 {
 128    p->current->bits2.da1.flag_reg_nr = reg;
 129    p->current->bits2.da1.flag_subreg_nr = subreg;
 130 }
 131
 132 void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
 133 {
 134    p->current->header.access_mode = access_mode;
 135 }
 136
 137 void
 138 brw_set_compression_control(struct brw_compile *p,
 139                             enum brw_compression compression_control)
 140 {
 141    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 142
 143    if (p->brw->gen >= 6) {
 144       /* Since we don't use the SIMD32 support in gen6, we translate
 145        * the pre-gen6 compression control here.
 146        */
 147       switch (compression_control) {
 148       case BRW_COMPRESSION_NONE:
 149          /* This is the "use the first set of bits of dmask/vmask/arf
 150           * according to execsize" option.
 151           */
 152          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 153          break;
 154       case BRW_COMPRESSION_2NDHALF:
 155          /* For SIMD8, this is "use the second set of 8 bits." */
 156          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 157          break;
 158       case BRW_COMPRESSION_COMPRESSED:
 159          /* For SIMD16 instruction compression, use the first set of 16 bits
 160           * since we don't do SIMD32 dispatch.
 161           */
 162          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 163          break;
 164       default:
 165          assert(!"not reached");
 166          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 167          break;
 168       }
 169    } else {
 170       p->current->header.compression_control = compression_control;
 171    }
 172 }
 173
 174 void brw_set_mask_control( struct brw_compile *p, unsigned value )
 175 {
 176    p->current->header.mask_control = value;
 177 }
 178
 179 void brw_set_saturate( struct brw_compile *p, bool enable )
 180 {
 181    p->current->header.saturate = enable;
 182 }
 183
 184 void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
 185 {
 186    if (p->brw->gen >= 6)
 187       p->current->header.acc_wr_control = value;
 188 }
 189
 190 void brw_push_insn_state( struct brw_compile *p )
 191 {
 192    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 193    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 194    p->compressed_stack[p->current - p->stack] = p->compressed;
 195    p->current++;
 196 }
 197
 198 void brw_pop_insn_state( struct brw_compile *p )
 199 {
 200    assert(p->current != p->stack);
 201    p->current--;
 202    p->compressed = p->compressed_stack[p->current - p->stack];
 203 }
 204
 205
 206 /***********************************************************************
 207  */
 208 void
 209 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 210 {
 211    memset(p, 0, sizeof(*p));
 212
 213    p->brw = brw;
 214    /*
 215     * Set the initial instruction store array size to 1024, if found that
 216     * isn't enough, then it will double the store size at brw_next_insn()
 217     * until out of memory.
 218     */
 219    p->store_size = 1024;
 220    p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
 221    p->nr_insn = 0;
 222    p->current = p->stack;
 223    p->compressed = false;
 224    memset(p->current, 0, sizeof(p->current[0]));
 225
 226    p->mem_ctx = mem_ctx;
 227
 228    /* Some defaults?
 229     */
 230    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 231    brw_set_saturate(p, 0);
 232    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 233    brw_set_predicate_control_flag_value(p, 0xff);
 234
 235    /* Set up control flow stack */
 236    p->if_stack_depth = 0;
 237    p->if_stack_array_size = 16;
 238    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 239
 240    p->loop_stack_depth = 0;
 241    p->loop_stack_array_size = 16;
 242    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 243    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 244
 245    brw_init_compaction_tables(brw);
 246 }
 247
 248
 249 const unsigned *brw_get_program( struct brw_compile *p,
 250                                unsigned *sz )
 251 {
 252    brw_compact_instructions(p);
 253
 254    *sz = p->next_insn_offset;
 255    return (const unsigned *)p->store;
 256 }
 257
 258 void
 259 brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
 260 {
 261    struct brw_context *brw = p->brw;
 262    void *store = p->store;
 263    bool dump_hex = false;
 264
 265    for (int offset = start; offset < end;) {
 266       struct brw_instruction *insn = store + offset;
 267       struct brw_instruction uncompacted;
 268       bool compacted = insn->header.cmpt_control;
 269       fprintf(out, "0x%08x: ", offset);
 270
 271       if (insn->header.cmpt_control) {
 272          struct brw_compact_instruction *compacted = (void *)insn;
 273          if (dump_hex) {
 274             fprintf(out, "0x%08x 0x%08x                       ",
 275                     ((uint32_t *)insn)[1],
 276                     ((uint32_t *)insn)[0]);
 277          }
 278
 279          brw_uncompact_instruction(brw, &uncompacted, compacted);
 280          insn = &uncompacted;
 281          offset += 8;
 282       } else {
 283          if (dump_hex) {
 284             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 285                     ((uint32_t *)insn)[3],
 286                     ((uint32_t *)insn)[2],
 287                     ((uint32_t *)insn)[1],
 288                     ((uint32_t *)insn)[0]);
 289          }
 290          offset += 16;
 291       }
 292
 293       brw_disasm(out, insn, p->brw->gen, compacted);
 294    }
 295 }