src/mesa/drivers/dri/i965/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_defines.h"
  35 #include "brw_eu.h"
  36
  37 #include "glsl/ralloc.h"
  38
  39 /**
  40  * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
  41  *
  42  * This is different than reg_encoding from brw_disasm.c in that it operates
  43  * on the abstract enum values, rather than the generation-specific encoding.
  44  */
  45 const char *
  46 brw_reg_type_letters(unsigned type)
  47 {
  48    const char *names[] = {
  49       [BRW_REGISTER_TYPE_UD] = "UD",
  50       [BRW_REGISTER_TYPE_D]  = "D",
  51       [BRW_REGISTER_TYPE_UW] = "UW",
  52       [BRW_REGISTER_TYPE_W]  = "W",
  53       [BRW_REGISTER_TYPE_F]  = "F",
  54       [BRW_REGISTER_TYPE_UB] = "UB",
  55       [BRW_REGISTER_TYPE_B]  = "B",
  56       [BRW_REGISTER_TYPE_UV] = "UV",
  57       [BRW_REGISTER_TYPE_V]  = "V",
  58       [BRW_REGISTER_TYPE_VF] = "VF",
  59       [BRW_REGISTER_TYPE_DF] = "DF",
  60       [BRW_REGISTER_TYPE_HF] = "HF",
  61       [BRW_REGISTER_TYPE_UQ] = "UQ",
  62       [BRW_REGISTER_TYPE_Q]  = "Q",
  63    };
  64    assert(type <= BRW_REGISTER_TYPE_UQ);
  65    return names[type];
  66 }
  67
  68 /* Returns the corresponding conditional mod for swapping src0 and
  69  * src1 in e.g. CMP.
  70  */
  71 uint32_t
  72 brw_swap_cmod(uint32_t cmod)
  73 {
  74    switch (cmod) {
  75    case BRW_CONDITIONAL_Z:
  76    case BRW_CONDITIONAL_NZ:
  77       return cmod;
  78    case BRW_CONDITIONAL_G:
  79       return BRW_CONDITIONAL_L;
  80    case BRW_CONDITIONAL_GE:
  81       return BRW_CONDITIONAL_LE;
  82    case BRW_CONDITIONAL_L:
  83       return BRW_CONDITIONAL_G;
  84    case BRW_CONDITIONAL_LE:
  85       return BRW_CONDITIONAL_GE;
  86    default:
  87       return ~0;
  88    }
  89 }
  90
  91 void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
  92 {
  93    p->current->header.predicate_control = pc;
  94 }
  95
  96 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
  97 {
  98    p->current->header.predicate_inverse = predicate_inverse;
  99 }
 100
 101 void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
 102 {
 103    p->current->header.destreg__conditionalmod = conditional;
 104 }
 105
 106 void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
 107 {
 108    p->current->bits2.da1.flag_reg_nr = reg;
 109    p->current->bits2.da1.flag_subreg_nr = subreg;
 110 }
 111
 112 void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
 113 {
 114    p->current->header.access_mode = access_mode;
 115 }
 116
 117 void
 118 brw_set_compression_control(struct brw_compile *p,
 119                             enum brw_compression compression_control)
 120 {
 121    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 122
 123    if (p->brw->gen >= 6) {
 124       /* Since we don't use the SIMD32 support in gen6, we translate
 125        * the pre-gen6 compression control here.
 126        */
 127       switch (compression_control) {
 128       case BRW_COMPRESSION_NONE:
 129          /* This is the "use the first set of bits of dmask/vmask/arf
 130           * according to execsize" option.
 131           */
 132          p->current->header.compression_control = GEN6_COMPRESSION_1Q;
 133          break;
 134       case BRW_COMPRESSION_2NDHALF:
 135          /* For SIMD8, this is "use the second set of 8 bits." */
 136          p->current->header.compression_control = GEN6_COMPRESSION_2Q;
 137          break;
 138       case BRW_COMPRESSION_COMPRESSED:
 139          /* For SIMD16 instruction compression, use the first set of 16 bits
 140           * since we don't do SIMD32 dispatch.
 141           */
 142          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 143          break;
 144       default:
 145          assert(!"not reached");
 146          p->current->header.compression_control = GEN6_COMPRESSION_1H;
 147          break;
 148       }
 149    } else {
 150       p->current->header.compression_control = compression_control;
 151    }
 152 }
 153
 154 void brw_set_mask_control( struct brw_compile *p, unsigned value )
 155 {
 156    p->current->header.mask_control = value;
 157 }
 158
 159 void brw_set_saturate( struct brw_compile *p, bool enable )
 160 {
 161    p->current->header.saturate = enable;
 162 }
 163
 164 void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
 165 {
 166    if (p->brw->gen >= 6)
 167       p->current->header.acc_wr_control = value;
 168 }
 169
 170 void brw_push_insn_state( struct brw_compile *p )
 171 {
 172    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 173    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
 174    p->compressed_stack[p->current - p->stack] = p->compressed;
 175    p->current++;
 176 }
 177
 178 void brw_pop_insn_state( struct brw_compile *p )
 179 {
 180    assert(p->current != p->stack);
 181    p->current--;
 182    p->compressed = p->compressed_stack[p->current - p->stack];
 183 }
 184
 185
 186 /***********************************************************************
 187  */
 188 void
 189 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 190 {
 191    memset(p, 0, sizeof(*p));
 192
 193    p->brw = brw;
 194    /*
 195     * Set the initial instruction store array size to 1024, if found that
 196     * isn't enough, then it will double the store size at brw_next_insn()
 197     * until out of memory.
 198     */
 199    p->store_size = 1024;
 200    p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
 201    p->nr_insn = 0;
 202    p->current = p->stack;
 203    p->compressed = false;
 204    memset(p->current, 0, sizeof(p->current[0]));
 205
 206    p->mem_ctx = mem_ctx;
 207
 208    /* Some defaults?
 209     */
 210    brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 211    brw_set_saturate(p, 0);
 212    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 213
 214    /* Set up control flow stack */
 215    p->if_stack_depth = 0;
 216    p->if_stack_array_size = 16;
 217    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 218
 219    p->loop_stack_depth = 0;
 220    p->loop_stack_array_size = 16;
 221    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 222    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 223
 224    brw_init_compaction_tables(brw);
 225 }
 226
 227
 228 const unsigned *brw_get_program( struct brw_compile *p,
 229                                unsigned *sz )
 230 {
 231    *sz = p->next_insn_offset;
 232    return (const unsigned *)p->store;
 233 }
 234
 235 void
 236 brw_disassemble(struct brw_context *brw,
 237                 void *assembly, int start, int end, FILE *out)
 238 {
 239    bool dump_hex = false;
 240
 241    for (int offset = start; offset < end;) {
 242       struct brw_instruction *insn = assembly + offset;
 243       struct brw_instruction uncompacted;
 244       bool compacted = insn->header.cmpt_control;
 245       fprintf(out, "0x%08x: ", offset);
 246
 247       if (insn->header.cmpt_control) {
 248          struct brw_compact_instruction *compacted = (void *)insn;
 249          if (dump_hex) {
 250             fprintf(out, "0x%08x 0x%08x                       ",
 251                     ((uint32_t *)insn)[1],
 252                     ((uint32_t *)insn)[0]);
 253          }
 254
 255          brw_uncompact_instruction(brw, &uncompacted, compacted);
 256          insn = &uncompacted;
 257          offset += 8;
 258       } else {
 259          if (dump_hex) {
 260             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 261                     ((uint32_t *)insn)[3],
 262                     ((uint32_t *)insn)[2],
 263                     ((uint32_t *)insn)[1],
 264                     ((uint32_t *)insn)[0]);
 265          }
 266          offset += 16;
 267       }
 268
 269       brw_disassemble_inst(out, insn, brw->gen, compacted);
 270    }
 271 }