src/mesa/drivers/dri/i965/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include "brw_structs.h"
  37 #include "brw_defines.h"
  38 #include "shader/prog_instruction.h"
  39
  40 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
  41 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
  42
  43 #define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)
  44 #define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)
  45 #define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)
  46 #define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)
  47
  48
  49 #define REG_SIZE (8*4)
  50
  51
  52 /* These aren't hardware structs, just something useful for us to pass around:
  53  *
  54  * Align1 operation has a lot of control over input ranges.  Used in
  55  * WM programs to implement shaders decomposed into "channel serial"
  56  * or "structure of array" form:
  57  */
  58 struct brw_reg
  59 {
  60    GLuint type:4;
  61    GLuint file:2;
  62    GLuint nr:8;
  63    GLuint subnr:5;              /* :1 in align16 */
  64    GLuint negate:1;             /* source only */
  65    GLuint abs:1;                /* source only */
  66    GLuint vstride:4;            /* source only */
  67    GLuint width:3;              /* src only, align1 only */
  68    GLuint hstride:2;            /* align1 only */
  69    GLuint address_mode:1;       /* relative addressing, hopefully! */
  70    GLuint pad0:1;
  71
  72    union {
  73       struct {
  74          GLuint swizzle:8;              /* src only, align16 only */
  75          GLuint writemask:4;            /* dest only, align16 only */
  76          GLint  indirect_offset:10;     /* relative addressing offset */
  77          GLuint pad1:10;                /* two dwords total */
  78       } bits;
  79
  80       GLfloat f;
  81       GLint   d;
  82       GLuint ud;
  83    } dw1;
  84 };
  85
  86
  87 struct brw_indirect {
  88    GLuint addr_subnr:4;
  89    GLint addr_offset:10;
  90    GLuint pad:18;
  91 };
  92
  93
  94 #define BRW_EU_MAX_INSN_STACK 5
  95 #define BRW_EU_MAX_INSN 1200
  96
  97 struct brw_compile {
  98    struct brw_instruction store[BRW_EU_MAX_INSN];
  99    GLuint nr_insn;
 100
 101    /* Allow clients to push/pop instruction state:
 102     */
 103    struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
 104    struct brw_instruction *current;
 105
 106    GLuint flag_value;
 107    GLboolean single_program_flow;
 108    struct brw_context *brw;
 109 };
 110
 111
 112
 113 static INLINE int type_sz( GLuint type )
 114 {
 115    switch( type ) {
 116    case BRW_REGISTER_TYPE_UD:
 117    case BRW_REGISTER_TYPE_D:
 118    case BRW_REGISTER_TYPE_F:
 119       return 4;
 120    case BRW_REGISTER_TYPE_HF:
 121    case BRW_REGISTER_TYPE_UW:
 122    case BRW_REGISTER_TYPE_W:
 123       return 2;
 124    case BRW_REGISTER_TYPE_UB:
 125    case BRW_REGISTER_TYPE_B:
 126       return 1;
 127    default:
 128       return 0;
 129    }
 130 }
 131
 132 /**
 133  * Construct a brw_reg.
 134  * \param file  one of the BRW_x_REGISTER_FILE values
 135  * \param nr  register number/index
 136  * \param subnr  register sub number
 137  * \param type  one of BRW_REGISTER_TYPE_x
 138  * \param vstride  one of BRW_VERTICAL_STRIDE_x
 139  * \param width  one of BRW_WIDTH_x
 140  * \param hstride  one of BRW_HORIZONTAL_STRIDE_x
 141  * \param swizzle  one of BRW_SWIZZLE_x
 142  * \param writemask  WRITEMASK_X/Y/Z/W bitfield
 143  */
 144 static INLINE struct brw_reg brw_reg( GLuint file,
 145                                       GLuint nr,
 146                                       GLuint subnr,
 147                                       GLuint type,
 148                                       GLuint vstride,
 149                                       GLuint width,
 150                                       GLuint hstride,
 151                                       GLuint swizzle,
 152                                       GLuint writemask )
 153 {
 154    struct brw_reg reg;
 155    reg.type = type;
 156    reg.file = file;
 157    reg.nr = nr;
 158    reg.subnr = subnr * type_sz(type);
 159    reg.negate = 0;
 160    reg.abs = 0;
 161    reg.vstride = vstride;
 162    reg.width = width;
 163    reg.hstride = hstride;
 164    reg.address_mode = BRW_ADDRESS_DIRECT;
 165    reg.pad0 = 0;
 166
 167    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
 168     * set swizzle and writemask to W, as the lower bits of subnr will
 169     * be lost when converted to align16.  This is probably too much to
 170     * keep track of as you'd want it adjusted by suboffset(), etc.
 171     * Perhaps fix up when converting to align16?
 172     */
 173    reg.dw1.bits.swizzle = swizzle;
 174    reg.dw1.bits.writemask = writemask;
 175    reg.dw1.bits.indirect_offset = 0;
 176    reg.dw1.bits.pad1 = 0;
 177    return reg;
 178 }
 179
 180 /** Construct float[16] register */
 181 static INLINE struct brw_reg brw_vec16_reg( GLuint file,
 182                                               GLuint nr,
 183                                               GLuint subnr )
 184 {
 185    return brw_reg(file,
 186                   nr,
 187                   subnr,
 188                   BRW_REGISTER_TYPE_F,
 189                   BRW_VERTICAL_STRIDE_16,
 190                   BRW_WIDTH_16,
 191                   BRW_HORIZONTAL_STRIDE_1,
 192                   BRW_SWIZZLE_XYZW,
 193                   WRITEMASK_XYZW);
 194 }
 195
 196 /** Construct float[8] register */
 197 static INLINE struct brw_reg brw_vec8_reg( GLuint file,
 198                                              GLuint nr,
 199                                              GLuint subnr )
 200 {
 201    return brw_reg(file,
 202                   nr,
 203                   subnr,
 204                   BRW_REGISTER_TYPE_F,
 205                   BRW_VERTICAL_STRIDE_8,
 206                   BRW_WIDTH_8,
 207                   BRW_HORIZONTAL_STRIDE_1,
 208                   BRW_SWIZZLE_XYZW,
 209                   WRITEMASK_XYZW);
 210 }
 211
 212 /** Construct float[4] register */
 213 static INLINE struct brw_reg brw_vec4_reg( GLuint file,
 214                                               GLuint nr,
 215                                               GLuint subnr )
 216 {
 217    return brw_reg(file,
 218                   nr,
 219                   subnr,
 220                   BRW_REGISTER_TYPE_F,
 221                   BRW_VERTICAL_STRIDE_4,
 222                   BRW_WIDTH_4,
 223                   BRW_HORIZONTAL_STRIDE_1,
 224                   BRW_SWIZZLE_XYZW,
 225                   WRITEMASK_XYZW);
 226 }
 227
 228 /** Construct float[2] register */
 229 static INLINE struct brw_reg brw_vec2_reg( GLuint file,
 230                                               GLuint nr,
 231                                               GLuint subnr )
 232 {
 233    return brw_reg(file,
 234                   nr,
 235                   subnr,
 236                   BRW_REGISTER_TYPE_F,
 237                   BRW_VERTICAL_STRIDE_2,
 238                   BRW_WIDTH_2,
 239                   BRW_HORIZONTAL_STRIDE_1,
 240                   BRW_SWIZZLE_XYXY,
 241                   WRITEMASK_XY);
 242 }
 243
 244 /** Construct float[1] register */
 245 static INLINE struct brw_reg brw_vec1_reg( GLuint file,
 246                                              GLuint nr,
 247                                              GLuint subnr )
 248 {
 249    return brw_reg(file,
 250                   nr,
 251                   subnr,
 252                   BRW_REGISTER_TYPE_F,
 253                   BRW_VERTICAL_STRIDE_0,
 254                   BRW_WIDTH_1,
 255                   BRW_HORIZONTAL_STRIDE_0,
 256                   BRW_SWIZZLE_XXXX,
 257                   WRITEMASK_X);
 258 }
 259
 260
 261 static INLINE struct brw_reg retype( struct brw_reg reg,
 262                                        GLuint type )
 263 {
 264    reg.type = type;
 265    return reg;
 266 }
 267
 268 static INLINE struct brw_reg suboffset( struct brw_reg reg,
 269                                           GLuint delta )
 270 {
 271    reg.subnr += delta * type_sz(reg.type);
 272    return reg;
 273 }
 274
 275
 276 static INLINE struct brw_reg offset( struct brw_reg reg,
 277                                        GLuint delta )
 278 {
 279    reg.nr += delta;
 280    return reg;
 281 }
 282
 283
 284 static INLINE struct brw_reg byte_offset( struct brw_reg reg,
 285                                             GLuint bytes )
 286 {
 287    GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
 288    reg.nr = newoffset / REG_SIZE;
 289    reg.subnr = newoffset % REG_SIZE;
 290    return reg;
 291 }
 292
 293
 294 /** Construct unsigned word[16] register */
 295 static INLINE struct brw_reg brw_uw16_reg( GLuint file,
 296                                              GLuint nr,
 297                                              GLuint subnr )
 298 {
 299    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 300 }
 301
 302 /** Construct unsigned word[8] register */
 303 static INLINE struct brw_reg brw_uw8_reg( GLuint file,
 304                                             GLuint nr,
 305                                             GLuint subnr )
 306 {
 307    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 308 }
 309
 310 /** Construct unsigned word[1] register */
 311 static INLINE struct brw_reg brw_uw1_reg( GLuint file,
 312                                             GLuint nr,
 313                                             GLuint subnr )
 314 {
 315    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 316 }
 317
 318 static INLINE struct brw_reg brw_imm_reg( GLuint type )
 319 {
 320    return brw_reg( BRW_IMMEDIATE_VALUE,
 321                    0,
 322                    0,
 323                    type,
 324                    BRW_VERTICAL_STRIDE_0,
 325                    BRW_WIDTH_1,
 326                    BRW_HORIZONTAL_STRIDE_0,
 327                    0,
 328                    0);
 329 }
 330
 331 /** Construct float immediate register */
 332 static INLINE struct brw_reg brw_imm_f( GLfloat f )
 333 {
 334    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
 335    imm.dw1.f = f;
 336    return imm;
 337 }
 338
 339 /** Construct integer immediate register */
 340 static INLINE struct brw_reg brw_imm_d( GLint d )
 341 {
 342    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
 343    imm.dw1.d = d;
 344    return imm;
 345 }
 346
 347 /** Construct uint immediate register */
 348 static INLINE struct brw_reg brw_imm_ud( GLuint ud )
 349 {
 350    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
 351    imm.dw1.ud = ud;
 352    return imm;
 353 }
 354
 355 /** Construct ushort immediate register */
 356 static INLINE struct brw_reg brw_imm_uw( GLushort uw )
 357 {
 358    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
 359    imm.dw1.ud = uw | (uw << 16);
 360    return imm;
 361 }
 362
 363 /** Construct short immediate register */
 364 static INLINE struct brw_reg brw_imm_w( GLshort w )
 365 {
 366    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
 367    imm.dw1.d = w | (w << 16);
 368    return imm;
 369 }
 370
 371 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
 372  * numbers alias with _V and _VF below:
 373  */
 374
 375 /** Construct vector of eight signed half-byte values */
 376 static INLINE struct brw_reg brw_imm_v( GLuint v )
 377 {
 378    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
 379    imm.vstride = BRW_VERTICAL_STRIDE_0;
 380    imm.width = BRW_WIDTH_8;
 381    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 382    imm.dw1.ud = v;
 383    return imm;
 384 }
 385
 386 /** Construct vector of four 8-bit float values */
 387 static INLINE struct brw_reg brw_imm_vf( GLuint v )
 388 {
 389    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 390    imm.vstride = BRW_VERTICAL_STRIDE_0;
 391    imm.width = BRW_WIDTH_4;
 392    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 393    imm.dw1.ud = v;
 394    return imm;
 395 }
 396
 397 #define VF_ZERO 0x0
 398 #define VF_ONE  0x30
 399 #define VF_NEG  (1<<7)
 400
 401 static INLINE struct brw_reg brw_imm_vf4( GLuint v0,
 402                                             GLuint v1,
 403                                             GLuint v2,
 404                                             GLuint v3)
 405 {
 406    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 407    imm.vstride = BRW_VERTICAL_STRIDE_0;
 408    imm.width = BRW_WIDTH_4;
 409    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 410    imm.dw1.ud = ((v0 << 0) |
 411                  (v1 << 8) |
 412                  (v2 << 16) |
 413                  (v3 << 24));
 414    return imm;
 415 }
 416
 417
 418 static INLINE struct brw_reg brw_address( struct brw_reg reg )
 419 {
 420    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 421 }
 422
 423 /** Construct float[1] general-purpose register */
 424 static INLINE struct brw_reg brw_vec1_grf( GLuint nr, GLuint subnr )
 425 {
 426    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 427 }
 428
 429 /** Construct float[2] general-purpose register */
 430 static INLINE struct brw_reg brw_vec2_grf( GLuint nr, GLuint subnr )
 431 {
 432    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 433 }
 434
 435 /** Construct float[4] general-purpose register */
 436 static INLINE struct brw_reg brw_vec4_grf( GLuint nr, GLuint subnr )
 437 {
 438    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 439 }
 440
 441 /** Construct float[8] general-purpose register */
 442 static INLINE struct brw_reg brw_vec8_grf( GLuint nr, GLuint subnr )
 443 {
 444    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 445 }
 446
 447
 448 static INLINE struct brw_reg brw_uw8_grf( GLuint nr, GLuint subnr )
 449 {
 450    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 451 }
 452
 453 static INLINE struct brw_reg brw_uw16_grf( GLuint nr, GLuint subnr )
 454 {
 455    return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 456 }
 457
 458
 459 /** Construct null register (usually used for setting condition codes) */
 460 static INLINE struct brw_reg brw_null_reg( void )
 461 {
 462    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 463                        BRW_ARF_NULL,
 464                        0);
 465 }
 466
 467 static INLINE struct brw_reg brw_address_reg( GLuint subnr )
 468 {
 469    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 470                       BRW_ARF_ADDRESS,
 471                       subnr);
 472 }
 473
 474 /* If/else instructions break in align16 mode if writemask & swizzle
 475  * aren't xyzw.  This goes against the convention for other scalar
 476  * regs:
 477  */
 478 static INLINE struct brw_reg brw_ip_reg( void )
 479 {
 480    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 481                   BRW_ARF_IP,
 482                   0,
 483                   BRW_REGISTER_TYPE_UD,
 484                   BRW_VERTICAL_STRIDE_4, /* ? */
 485                   BRW_WIDTH_1,
 486                   BRW_HORIZONTAL_STRIDE_0,
 487                   BRW_SWIZZLE_XYZW, /* NOTE! */
 488                   WRITEMASK_XYZW); /* NOTE! */
 489 }
 490
 491 static INLINE struct brw_reg brw_acc_reg( void )
 492 {
 493    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 494                        BRW_ARF_ACCUMULATOR,
 495                        0);
 496 }
 497
 498
 499 static INLINE struct brw_reg brw_flag_reg( void )
 500 {
 501    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 502                       BRW_ARF_FLAG,
 503                       0);
 504 }
 505
 506
 507 static INLINE struct brw_reg brw_mask_reg( GLuint subnr )
 508 {
 509    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 510                       BRW_ARF_MASK,
 511                       subnr);
 512 }
 513
 514 static INLINE struct brw_reg brw_message_reg( GLuint nr )
 515 {
 516    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE,
 517                        nr,
 518                        0);
 519 }
 520
 521
 522
 523
 524 /* This is almost always called with a numeric constant argument, so
 525  * make things easy to evaluate at compile time:
 526  */
 527 static INLINE GLuint cvt( GLuint val )
 528 {
 529    switch (val) {
 530    case 0: return 0;
 531    case 1: return 1;
 532    case 2: return 2;
 533    case 4: return 3;
 534    case 8: return 4;
 535    case 16: return 5;
 536    case 32: return 6;
 537    }
 538    return 0;
 539 }
 540
 541 static INLINE struct brw_reg stride( struct brw_reg reg,
 542                                        GLuint vstride,
 543                                        GLuint width,
 544                                        GLuint hstride )
 545 {
 546    reg.vstride = cvt(vstride);
 547    reg.width = cvt(width) - 1;
 548    reg.hstride = cvt(hstride);
 549    return reg;
 550 }
 551
 552
 553 static INLINE struct brw_reg vec16( struct brw_reg reg )
 554 {
 555    return stride(reg, 16,16,1);
 556 }
 557
 558 static INLINE struct brw_reg vec8( struct brw_reg reg )
 559 {
 560    return stride(reg, 8,8,1);
 561 }
 562
 563 static INLINE struct brw_reg vec4( struct brw_reg reg )
 564 {
 565    return stride(reg, 4,4,1);
 566 }
 567
 568 static INLINE struct brw_reg vec2( struct brw_reg reg )
 569 {
 570    return stride(reg, 2,2,1);
 571 }
 572
 573 static INLINE struct brw_reg vec1( struct brw_reg reg )
 574 {
 575    return stride(reg, 0,1,0);
 576 }
 577
 578
 579 static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt )
 580 {
 581    return vec1(suboffset(reg, elt));
 582 }
 583
 584 static INLINE struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt )
 585 {
 586    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
 587 }
 588
 589
 590 static INLINE struct brw_reg brw_swizzle( struct brw_reg reg,
 591                                             GLuint x,
 592                                             GLuint y,
 593                                             GLuint z,
 594                                             GLuint w)
 595 {
 596    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
 597                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
 598                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
 599                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
 600    return reg;
 601 }
 602
 603
 604 static INLINE struct brw_reg brw_swizzle1( struct brw_reg reg,
 605                                              GLuint x )
 606 {
 607    return brw_swizzle(reg, x, x, x, x);
 608 }
 609
 610 static INLINE struct brw_reg brw_writemask( struct brw_reg reg,
 611                                               GLuint mask )
 612 {
 613    reg.dw1.bits.writemask &= mask;
 614    return reg;
 615 }
 616
 617 static INLINE struct brw_reg brw_set_writemask( struct brw_reg reg,
 618                                                   GLuint mask )
 619 {
 620    reg.dw1.bits.writemask = mask;
 621    return reg;
 622 }
 623
 624 static INLINE struct brw_reg negate( struct brw_reg reg )
 625 {
 626    reg.negate ^= 1;
 627    return reg;
 628 }
 629
 630 static INLINE struct brw_reg brw_abs( struct brw_reg reg )
 631 {
 632    reg.abs = 1;
 633    return reg;
 634 }
 635
 636 /***********************************************************************
 637  */
 638 static INLINE struct brw_reg brw_vec4_indirect( GLuint subnr,
 639                                                   GLint offset )
 640 {
 641    struct brw_reg reg =  brw_vec4_grf(0, 0);
 642    reg.subnr = subnr;
 643    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 644    reg.dw1.bits.indirect_offset = offset;
 645    return reg;
 646 }
 647
 648 static INLINE struct brw_reg brw_vec1_indirect( GLuint subnr,
 649                                                   GLint offset )
 650 {
 651    struct brw_reg reg =  brw_vec1_grf(0, 0);
 652    reg.subnr = subnr;
 653    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 654    reg.dw1.bits.indirect_offset = offset;
 655    return reg;
 656 }
 657
 658 static INLINE struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset)
 659 {
 660    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 661 }
 662
 663 static INLINE struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset)
 664 {
 665    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 666 }
 667
 668 static INLINE struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset)
 669 {
 670    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
 671 }
 672
 673 static INLINE struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset)
 674 {
 675    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
 676 }
 677
 678 static INLINE struct brw_reg deref_1d(struct brw_indirect ptr, GLint offset)
 679 {
 680    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
 681 }
 682
 683 static INLINE struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset)
 684 {
 685    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
 686 }
 687
 688 static INLINE struct brw_reg get_addr_reg(struct brw_indirect ptr)
 689 {
 690    return brw_address_reg(ptr.addr_subnr);
 691 }
 692
 693 static INLINE struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset )
 694 {
 695    ptr.addr_offset += offset;
 696    return ptr;
 697 }
 698
 699 static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset )
 700 {
 701    struct brw_indirect ptr;
 702    ptr.addr_subnr = addr_subnr;
 703    ptr.addr_offset = offset;
 704    ptr.pad = 0;
 705    return ptr;
 706 }
 707
 708 static INLINE struct brw_instruction *current_insn( struct brw_compile *p)
 709 {
 710    return &p->store[p->nr_insn];
 711 }
 712
 713 void brw_pop_insn_state( struct brw_compile *p );
 714 void brw_push_insn_state( struct brw_compile *p );
 715 void brw_set_mask_control( struct brw_compile *p, GLuint value );
 716 void brw_set_saturate( struct brw_compile *p, GLuint value );
 717 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );
 718 void brw_set_compression_control( struct brw_compile *p, GLboolean control );
 719 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
 720 void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
 721 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
 722
 723 void brw_init_compile( struct brw_context *, struct brw_compile *p );
 724 const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
 725
 726
 727 /* Helpers for regular instructions:
 728  */
 729 #define ALU1(OP)                                        \
 730 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 731               struct brw_reg dest,                      \
 732               struct brw_reg src0);
 733
 734 #define ALU2(OP)                                        \
 735 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 736               struct brw_reg dest,                      \
 737               struct brw_reg src0,                      \
 738               struct brw_reg src1);
 739
 740 ALU1(MOV)
 741 ALU2(SEL)
 742 ALU1(NOT)
 743 ALU2(AND)
 744 ALU2(OR)
 745 ALU2(XOR)
 746 ALU2(SHR)
 747 ALU2(SHL)
 748 ALU2(RSR)
 749 ALU2(RSL)
 750 ALU2(ASR)
 751 ALU2(JMPI)
 752 ALU2(ADD)
 753 ALU2(MUL)
 754 ALU1(FRC)
 755 ALU1(RNDD)
 756 ALU2(MAC)
 757 ALU2(MACH)
 758 ALU1(LZD)
 759 ALU2(DP4)
 760 ALU2(DPH)
 761 ALU2(DP3)
 762 ALU2(DP2)
 763 ALU2(LINE)
 764
 765 #undef ALU1
 766 #undef ALU2
 767
 768
 769
 770 /* Helpers for SEND instruction:
 771  */
 772 void brw_urb_WRITE(struct brw_compile *p,
 773                    struct brw_reg dest,
 774                    GLuint msg_reg_nr,
 775                    struct brw_reg src0,
 776                    GLboolean allocate,
 777                    GLboolean used,
 778                    GLuint msg_length,
 779                    GLuint response_length,
 780                    GLboolean eot,
 781                    GLboolean writes_complete,
 782                    GLuint offset,
 783                    GLuint swizzle);
 784
 785 void brw_fb_WRITE(struct brw_compile *p,
 786                    struct brw_reg dest,
 787                    GLuint msg_reg_nr,
 788                    struct brw_reg src0,
 789                    GLuint binding_table_index,
 790                    GLuint msg_length,
 791                    GLuint response_length,
 792                    GLboolean eot);
 793
 794 void brw_SAMPLE(struct brw_compile *p,
 795                 struct brw_reg dest,
 796                 GLuint msg_reg_nr,
 797                 struct brw_reg src0,
 798                 GLuint binding_table_index,
 799                 GLuint sampler,
 800                 GLuint writemask,
 801                 GLuint msg_type,
 802                 GLuint response_length,
 803                 GLuint msg_length,
 804                 GLboolean eot);
 805
 806 void brw_math_16( struct brw_compile *p,
 807                   struct brw_reg dest,
 808                   GLuint function,
 809                   GLuint saturate,
 810                   GLuint msg_reg_nr,
 811                   struct brw_reg src,
 812                   GLuint precision );
 813
 814 void brw_math( struct brw_compile *p,
 815                struct brw_reg dest,
 816                GLuint function,
 817                GLuint saturate,
 818                GLuint msg_reg_nr,
 819                struct brw_reg src,
 820                GLuint data_type,
 821                GLuint precision );
 822
 823 void brw_dp_READ_16( struct brw_compile *p,
 824                      struct brw_reg dest,
 825                      GLuint msg_reg_nr,
 826                      GLuint scratch_offset );
 827
 828 void brw_dp_WRITE_16( struct brw_compile *p,
 829                       struct brw_reg src,
 830                       GLuint msg_reg_nr,
 831                       GLuint scratch_offset );
 832
 833 /* If/else/endif.  Works by manipulating the execution flags on each
 834  * channel.
 835  */
 836 struct brw_instruction *brw_IF(struct brw_compile *p,
 837                                GLuint execute_size);
 838
 839 struct brw_instruction *brw_ELSE(struct brw_compile *p,
 840                                  struct brw_instruction *if_insn);
 841
 842 void brw_ENDIF(struct brw_compile *p,
 843                struct brw_instruction *if_or_else_insn);
 844
 845
 846 /* DO/WHILE loops:
 847  */
 848 struct brw_instruction *brw_DO(struct brw_compile *p,
 849                                GLuint execute_size);
 850
 851 struct brw_instruction *brw_WHILE(struct brw_compile *p,
 852                struct brw_instruction *patch_insn);
 853
 854 struct brw_instruction *brw_BREAK(struct brw_compile *p);
 855 struct brw_instruction *brw_CONT(struct brw_compile *p);
 856 /* Forward jumps:
 857  */
 858 void brw_land_fwd_jump(struct brw_compile *p,
 859                        struct brw_instruction *jmp_insn);
 860
 861
 862
 863 void brw_NOP(struct brw_compile *p);
 864
 865 /* Special case: there is never a destination, execution size will be
 866  * taken from src0:
 867  */
 868 void brw_CMP(struct brw_compile *p,
 869              struct brw_reg dest,
 870              GLuint conditional,
 871              struct brw_reg src0,
 872              struct brw_reg src1);
 873
 874 void brw_print_reg( struct brw_reg reg );
 875
 876
 877 /***********************************************************************
 878  * brw_eu_util.c:
 879  */
 880
 881 void brw_copy_indirect_to_indirect(struct brw_compile *p,
 882                                    struct brw_indirect dst_ptr,
 883                                    struct brw_indirect src_ptr,
 884                                    GLuint count);
 885
 886 void brw_copy_from_indirect(struct brw_compile *p,
 887                             struct brw_reg dst,
 888                             struct brw_indirect ptr,
 889                             GLuint count);
 890
 891 void brw_copy4(struct brw_compile *p,
 892                struct brw_reg dst,
 893                struct brw_reg src,
 894                GLuint count);
 895
 896 void brw_copy8(struct brw_compile *p,
 897                struct brw_reg dst,
 898                struct brw_reg src,
 899                GLuint count);
 900
 901 void brw_math_invert( struct brw_compile *p,
 902                       struct brw_reg dst,
 903                       struct brw_reg src);
 904
 905 void brw_set_src1( struct brw_instruction *insn,
 906                           struct brw_reg reg );
 907 #endif