2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
36 #include "brw_structs.h"
37 #include "brw_defines.h"
38 #include "shader/prog_instruction.h"
40 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
41 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
43 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
44 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
45 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
46 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
49 #define REG_SIZE (8*4)
52 /* These aren't hardware structs, just something useful for us to pass around:
54 * Align1 operation has a lot of control over input ranges. Used in
55 * WM programs to implement shaders decomposed into "channel serial"
56 * or "structure of array" form:
63 GLuint subnr
:5; /* :1 in align16 */
64 GLuint negate
:1; /* source only */
65 GLuint abs
:1; /* source only */
66 GLuint vstride
:4; /* source only */
67 GLuint width
:3; /* src only, align1 only */
68 GLuint hstride
:2; /* align1 only */
69 GLuint address_mode
:1; /* relative addressing, hopefully! */
74 GLuint swizzle
:8; /* src only, align16 only */
75 GLuint writemask
:4; /* dest only, align16 only */
76 GLint indirect_offset
:10; /* relative addressing offset */
77 GLuint pad1
:10; /* two dwords total */
94 #define BRW_EU_MAX_INSN_STACK 5
95 #define BRW_EU_MAX_INSN 1200
98 struct brw_instruction store
[BRW_EU_MAX_INSN
];
101 /* Allow clients to push/pop instruction state:
103 struct brw_instruction stack
[BRW_EU_MAX_INSN_STACK
];
104 struct brw_instruction
*current
;
107 GLboolean single_program_flow
;
108 struct brw_context
*brw
;
113 static INLINE
int type_sz( GLuint type
)
116 case BRW_REGISTER_TYPE_UD
:
117 case BRW_REGISTER_TYPE_D
:
118 case BRW_REGISTER_TYPE_F
:
120 case BRW_REGISTER_TYPE_HF
:
121 case BRW_REGISTER_TYPE_UW
:
122 case BRW_REGISTER_TYPE_W
:
124 case BRW_REGISTER_TYPE_UB
:
125 case BRW_REGISTER_TYPE_B
:
132 static INLINE
struct brw_reg
brw_reg( GLuint file
,
147 reg
.subnr
= subnr
* type_sz(type
);
150 reg
.vstride
= vstride
;
152 reg
.hstride
= hstride
;
153 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
156 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
157 * set swizzle and writemask to W, as the lower bits of subnr will
158 * be lost when converted to align16. This is probably too much to
159 * keep track of as you'd want it adjusted by suboffset(), etc.
160 * Perhaps fix up when converting to align16?
162 reg
.dw1
.bits
.swizzle
= swizzle
;
163 reg
.dw1
.bits
.writemask
= writemask
;
164 reg
.dw1
.bits
.indirect_offset
= 0;
165 reg
.dw1
.bits
.pad1
= 0;
169 static INLINE
struct brw_reg
brw_vec16_reg( GLuint file
,
177 BRW_VERTICAL_STRIDE_16
,
179 BRW_HORIZONTAL_STRIDE_1
,
184 static INLINE
struct brw_reg
brw_vec8_reg( GLuint file
,
192 BRW_VERTICAL_STRIDE_8
,
194 BRW_HORIZONTAL_STRIDE_1
,
200 static INLINE
struct brw_reg
brw_vec4_reg( GLuint file
,
208 BRW_VERTICAL_STRIDE_4
,
210 BRW_HORIZONTAL_STRIDE_1
,
216 static INLINE
struct brw_reg
brw_vec2_reg( GLuint file
,
224 BRW_VERTICAL_STRIDE_2
,
226 BRW_HORIZONTAL_STRIDE_1
,
231 static INLINE
struct brw_reg
brw_vec1_reg( GLuint file
,
239 BRW_VERTICAL_STRIDE_0
,
241 BRW_HORIZONTAL_STRIDE_0
,
247 static INLINE
struct brw_reg
retype( struct brw_reg reg
,
254 static INLINE
struct brw_reg
suboffset( struct brw_reg reg
,
257 reg
.subnr
+= delta
* type_sz(reg
.type
);
262 static INLINE
struct brw_reg
offset( struct brw_reg reg
,
270 static INLINE
struct brw_reg
byte_offset( struct brw_reg reg
,
273 GLuint newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
274 reg
.nr
= newoffset
/ REG_SIZE
;
275 reg
.subnr
= newoffset
% REG_SIZE
;
280 static INLINE
struct brw_reg
brw_uw16_reg( GLuint file
,
284 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
287 static INLINE
struct brw_reg
brw_uw8_reg( GLuint file
,
291 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
294 static INLINE
struct brw_reg
brw_uw1_reg( GLuint file
,
298 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
301 static INLINE
struct brw_reg
brw_imm_reg( GLuint type
)
303 return brw_reg( BRW_IMMEDIATE_VALUE
,
307 BRW_VERTICAL_STRIDE_0
,
309 BRW_HORIZONTAL_STRIDE_0
,
314 static INLINE
struct brw_reg
brw_imm_f( GLfloat f
)
316 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
321 static INLINE
struct brw_reg
brw_imm_d( GLint d
)
323 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
328 static INLINE
struct brw_reg
brw_imm_ud( GLuint ud
)
330 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
335 static INLINE
struct brw_reg
brw_imm_uw( GLushort uw
)
337 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
338 imm
.dw1
.ud
= uw
| (uw
<< 16);
342 static INLINE
struct brw_reg
brw_imm_w( GLshort w
)
344 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
345 imm
.dw1
.d
= w
| (w
<< 16);
349 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
350 * numbers alias with _V and _VF below:
353 /* Vector of eight signed half-byte values:
355 static INLINE
struct brw_reg
brw_imm_v( GLuint v
)
357 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
358 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
359 imm
.width
= BRW_WIDTH_8
;
360 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
365 /* Vector of four 8-bit float values:
367 static INLINE
struct brw_reg
brw_imm_vf( GLuint v
)
369 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
370 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
371 imm
.width
= BRW_WIDTH_4
;
372 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
379 #define VF_NEG (1<<7)
381 static INLINE
struct brw_reg
brw_imm_vf4( GLuint v0
,
386 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
387 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
388 imm
.width
= BRW_WIDTH_4
;
389 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
390 imm
.dw1
.ud
= ((v0
<< 0) |
398 static INLINE
struct brw_reg
brw_address( struct brw_reg reg
)
400 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
404 static INLINE
struct brw_reg
brw_vec1_grf( GLuint nr
,
407 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
410 static INLINE
struct brw_reg
brw_vec8_grf( GLuint nr
,
413 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
416 static INLINE
struct brw_reg
brw_vec4_grf( GLuint nr
,
419 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
423 static INLINE
struct brw_reg
brw_vec2_grf( GLuint nr
,
426 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
429 static INLINE
struct brw_reg
brw_uw8_grf( GLuint nr
,
432 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
435 static INLINE
struct brw_reg
brw_uw16_grf( GLuint nr
,
438 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
441 static INLINE
struct brw_reg
brw_null_reg( void )
443 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
448 static INLINE
struct brw_reg
brw_address_reg( GLuint subnr
)
450 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
455 /* If/else instructions break in align16 mode if writemask & swizzle
456 * aren't xyzw. This goes against the convention for other scalar
459 static INLINE
struct brw_reg
brw_ip_reg( void )
461 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
464 BRW_REGISTER_TYPE_UD
,
465 BRW_VERTICAL_STRIDE_4
, /* ? */
467 BRW_HORIZONTAL_STRIDE_0
,
468 BRW_SWIZZLE_XYZW
, /* NOTE! */
469 WRITEMASK_XYZW
); /* NOTE! */
472 static INLINE
struct brw_reg
brw_acc_reg( void )
474 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
480 static INLINE
struct brw_reg
brw_flag_reg( void )
482 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
488 static INLINE
struct brw_reg
brw_mask_reg( GLuint subnr
)
490 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
495 static INLINE
struct brw_reg
brw_message_reg( GLuint nr
)
497 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
,
505 /* This is almost always called with a numeric constant argument, so
506 * make things easy to evaluate at compile time:
508 static INLINE GLuint
cvt( GLuint val
)
522 static INLINE
struct brw_reg
stride( struct brw_reg reg
,
528 reg
.vstride
= cvt(vstride
);
529 reg
.width
= cvt(width
) - 1;
530 reg
.hstride
= cvt(hstride
);
534 static INLINE
struct brw_reg
vec16( struct brw_reg reg
)
536 return stride(reg
, 16,16,1);
539 static INLINE
struct brw_reg
vec8( struct brw_reg reg
)
541 return stride(reg
, 8,8,1);
544 static INLINE
struct brw_reg
vec4( struct brw_reg reg
)
546 return stride(reg
, 4,4,1);
549 static INLINE
struct brw_reg
vec2( struct brw_reg reg
)
551 return stride(reg
, 2,2,1);
554 static INLINE
struct brw_reg
vec1( struct brw_reg reg
)
556 return stride(reg
, 0,1,0);
559 static INLINE
struct brw_reg
get_element( struct brw_reg reg
, GLuint elt
)
561 return vec1(suboffset(reg
, elt
));
564 static INLINE
struct brw_reg
get_element_ud( struct brw_reg reg
, GLuint elt
)
566 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
570 static INLINE
struct brw_reg
brw_swizzle( struct brw_reg reg
,
576 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, x
),
577 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, y
),
578 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, z
),
579 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, w
));
584 static INLINE
struct brw_reg
brw_swizzle1( struct brw_reg reg
,
587 return brw_swizzle(reg
, x
, x
, x
, x
);
590 static INLINE
struct brw_reg
brw_writemask( struct brw_reg reg
,
593 reg
.dw1
.bits
.writemask
&= mask
;
597 static INLINE
struct brw_reg
brw_set_writemask( struct brw_reg reg
,
600 reg
.dw1
.bits
.writemask
= mask
;
604 static INLINE
struct brw_reg
negate( struct brw_reg reg
)
610 static INLINE
struct brw_reg
brw_abs( struct brw_reg reg
)
616 /***********************************************************************
618 static INLINE
struct brw_reg
brw_vec4_indirect( GLuint subnr
,
621 struct brw_reg reg
= brw_vec4_grf(0, 0);
623 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
624 reg
.dw1
.bits
.indirect_offset
= offset
;
628 static INLINE
struct brw_reg
brw_vec1_indirect( GLuint subnr
,
631 struct brw_reg reg
= brw_vec1_grf(0, 0);
633 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
634 reg
.dw1
.bits
.indirect_offset
= offset
;
638 static INLINE
struct brw_reg
deref_4f(struct brw_indirect ptr
, GLint offset
)
640 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
643 static INLINE
struct brw_reg
deref_1f(struct brw_indirect ptr
, GLint offset
)
645 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
648 static INLINE
struct brw_reg
deref_4b(struct brw_indirect ptr
, GLint offset
)
650 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
653 static INLINE
struct brw_reg
deref_1uw(struct brw_indirect ptr
, GLint offset
)
655 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
658 static INLINE
struct brw_reg
deref_1d(struct brw_indirect ptr
, GLint offset
)
660 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
663 static INLINE
struct brw_reg
deref_1ud(struct brw_indirect ptr
, GLint offset
)
665 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
668 static INLINE
struct brw_reg
get_addr_reg(struct brw_indirect ptr
)
670 return brw_address_reg(ptr
.addr_subnr
);
673 static INLINE
struct brw_indirect
brw_indirect_offset( struct brw_indirect ptr
, GLint offset
)
675 ptr
.addr_offset
+= offset
;
679 static INLINE
struct brw_indirect
brw_indirect( GLuint addr_subnr
, GLint offset
)
681 struct brw_indirect ptr
;
682 ptr
.addr_subnr
= addr_subnr
;
683 ptr
.addr_offset
= offset
;
688 static INLINE
struct brw_instruction
*current_insn( struct brw_compile
*p
)
690 return &p
->store
[p
->nr_insn
];
693 void brw_pop_insn_state( struct brw_compile
*p
);
694 void brw_push_insn_state( struct brw_compile
*p
);
695 void brw_set_mask_control( struct brw_compile
*p
, GLuint value
);
696 void brw_set_saturate( struct brw_compile
*p
, GLuint value
);
697 void brw_set_access_mode( struct brw_compile
*p
, GLuint access_mode
);
698 void brw_set_compression_control( struct brw_compile
*p
, GLboolean control
);
699 void brw_set_predicate_control_flag_value( struct brw_compile
*p
, GLuint value
);
700 void brw_set_predicate_control( struct brw_compile
*p
, GLuint pc
);
701 void brw_set_conditionalmod( struct brw_compile
*p
, GLuint conditional
);
703 void brw_init_compile( struct brw_context
*, struct brw_compile
*p
);
704 const GLuint
*brw_get_program( struct brw_compile
*p
, GLuint
*sz
);
707 /* Helpers for regular instructions:
710 struct brw_instruction *brw_##OP(struct brw_compile *p, \
711 struct brw_reg dest, \
712 struct brw_reg src0);
715 struct brw_instruction *brw_##OP(struct brw_compile *p, \
716 struct brw_reg dest, \
717 struct brw_reg src0, \
718 struct brw_reg src1);
750 /* Helpers for SEND instruction:
752 void brw_urb_WRITE(struct brw_compile
*p
,
759 GLuint response_length
,
761 GLboolean writes_complete
,
765 void brw_fb_WRITE(struct brw_compile
*p
,
769 GLuint binding_table_index
,
771 GLuint response_length
,
774 void brw_SAMPLE(struct brw_compile
*p
,
778 GLuint binding_table_index
,
782 GLuint response_length
,
786 void brw_math_16( struct brw_compile
*p
,
794 void brw_math( struct brw_compile
*p
,
803 void brw_dp_READ_16( struct brw_compile
*p
,
806 GLuint scratch_offset
);
808 void brw_dp_WRITE_16( struct brw_compile
*p
,
811 GLuint scratch_offset
);
813 /* If/else/endif. Works by manipulating the execution flags on each
816 struct brw_instruction
*brw_IF(struct brw_compile
*p
,
817 GLuint execute_size
);
819 struct brw_instruction
*brw_ELSE(struct brw_compile
*p
,
820 struct brw_instruction
*if_insn
);
822 void brw_ENDIF(struct brw_compile
*p
,
823 struct brw_instruction
*if_or_else_insn
);
828 struct brw_instruction
*brw_DO(struct brw_compile
*p
,
829 GLuint execute_size
);
831 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
,
832 struct brw_instruction
*patch_insn
);
834 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
);
835 struct brw_instruction
*brw_CONT(struct brw_compile
*p
);
838 void brw_land_fwd_jump(struct brw_compile
*p
,
839 struct brw_instruction
*jmp_insn
);
843 void brw_NOP(struct brw_compile
*p
);
845 /* Special case: there is never a destination, execution size will be
848 void brw_CMP(struct brw_compile
*p
,
852 struct brw_reg src1
);
854 void brw_print_reg( struct brw_reg reg
);
857 /***********************************************************************
861 void brw_copy_indirect_to_indirect(struct brw_compile
*p
,
862 struct brw_indirect dst_ptr
,
863 struct brw_indirect src_ptr
,
866 void brw_copy_from_indirect(struct brw_compile
*p
,
868 struct brw_indirect ptr
,
871 void brw_copy4(struct brw_compile
*p
,
876 void brw_copy8(struct brw_compile
*p
,
881 void brw_math_invert( struct brw_compile
*p
,
885 void brw_set_src1( struct brw_instruction
*insn
,
886 struct brw_reg reg
);