2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
38 #include "brw_defines.h"
40 #include "intel_asm_annotation.h"
46 #define BRW_EU_MAX_INSN_STACK 5
48 /* A helper for accessing the last instruction emitted. This makes it easy
49 * to set various bits on an instruction without having to create temporary
50 * variable and assign the emitted instruction to those.
52 #define brw_last_inst (&p->store[p->nr_insn - 1])
58 unsigned int next_insn_offset
;
62 /* Allow clients to push/pop instruction state:
64 brw_inst stack
[BRW_EU_MAX_INSN_STACK
];
65 bool compressed_stack
[BRW_EU_MAX_INSN_STACK
];
68 bool single_program_flow
;
70 const struct brw_device_info
*devinfo
;
72 /* Control flow stacks:
73 * - if_stack contains IF and ELSE instructions which must be patched
74 * (and popped) once the matching ENDIF instruction is encountered.
76 * Just store the instruction pointer(an index).
80 int if_stack_array_size
;
83 * loop_stack contains the instruction pointers of the starts of loops which
84 * must be patched (and popped) once the matching WHILE instruction is
89 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
90 * blocks they were popping out of, to fix up the mask stack. This tracks
91 * the IF/ENDIF nesting in each current nested loop level.
93 int *if_depth_in_loop
;
95 int loop_stack_array_size
;
98 void brw_pop_insn_state( struct brw_codegen
*p
);
99 void brw_push_insn_state( struct brw_codegen
*p
);
100 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
101 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
102 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
103 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
104 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
105 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
106 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
107 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
108 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
110 void brw_init_codegen(const struct brw_device_info
*, struct brw_codegen
*p
,
112 void brw_disassemble(const struct brw_device_info
*devinfo
, void *assembly
,
113 int start
, int end
, FILE *out
);
114 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
116 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
117 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
118 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
120 void gen6_resolve_implied_move(struct brw_codegen
*p
,
122 unsigned msg_reg_nr
);
124 /* Helpers for regular instructions:
127 brw_inst *brw_##OP(struct brw_codegen *p, \
128 struct brw_reg dest, \
129 struct brw_reg src0);
132 brw_inst *brw_##OP(struct brw_codegen *p, \
133 struct brw_reg dest, \
134 struct brw_reg src0, \
135 struct brw_reg src1);
138 brw_inst *brw_##OP(struct brw_codegen *p, \
139 struct brw_reg dest, \
140 struct brw_reg src0, \
141 struct brw_reg src1, \
142 struct brw_reg src2);
145 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
194 /* Helpers for SEND instruction:
196 void brw_set_sampler_message(struct brw_codegen
*p
,
198 unsigned binding_table_index
,
201 unsigned response_length
,
203 unsigned header_present
,
205 unsigned return_format
);
207 void brw_set_message_descriptor(struct brw_codegen
*p
,
209 enum brw_message_target sfid
,
211 unsigned response_length
,
215 void brw_set_dp_read_message(struct brw_codegen
*p
,
217 unsigned binding_table_index
,
218 unsigned msg_control
,
220 unsigned target_cache
,
223 unsigned response_length
);
225 void brw_set_dp_write_message(struct brw_codegen
*p
,
227 unsigned binding_table_index
,
228 unsigned msg_control
,
232 unsigned last_render_target
,
233 unsigned response_length
,
234 unsigned end_of_thread
,
235 unsigned send_commit_msg
);
237 void brw_urb_WRITE(struct brw_codegen
*p
,
241 enum brw_urb_write_flags flags
,
243 unsigned response_length
,
248 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
249 * desc. If \p desc is not an immediate it will be transparently loaded to an
250 * address register using an OR instruction. The returned instruction can be
251 * passed as argument to the usual brw_set_*_message() functions in order to
252 * specify any additional descriptor bits -- If \p desc is an immediate this
253 * will be the SEND instruction itself, otherwise it will be the OR
257 brw_send_indirect_message(struct brw_codegen
*p
,
260 struct brw_reg payload
,
261 struct brw_reg desc
);
263 void brw_ff_sync(struct brw_codegen
*p
,
268 unsigned response_length
,
271 void brw_svb_write(struct brw_codegen
*p
,
275 unsigned binding_table_index
,
276 bool send_commit_msg
);
278 void brw_fb_WRITE(struct brw_codegen
*p
,
280 struct brw_reg payload
,
281 struct brw_reg implied_header
,
282 unsigned msg_control
,
283 unsigned binding_table_index
,
285 unsigned response_length
,
287 bool last_render_target
,
288 bool header_present
);
290 void brw_SAMPLE(struct brw_codegen
*p
,
294 unsigned binding_table_index
,
297 unsigned response_length
,
299 unsigned header_present
,
301 unsigned return_format
);
303 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
304 struct brw_reg header
,
305 struct brw_reg sampler_index
);
307 void gen4_math(struct brw_codegen
*p
,
312 unsigned precision
);
314 void gen6_math(struct brw_codegen
*p
,
318 struct brw_reg src1
);
320 void brw_oword_block_read(struct brw_codegen
*p
,
324 uint32_t bind_table_index
);
326 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
328 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
334 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
339 void gen7_block_read_scratch(struct brw_codegen
*p
,
344 void brw_shader_time_add(struct brw_codegen
*p
,
345 struct brw_reg payload
,
346 uint32_t surf_index
);
349 * Return the generation-specific jump distance scaling factor.
351 * Given the number of instructions to jump, we need to scale by
352 * some number to obtain the actual jump distance to program in an
355 static inline unsigned
356 brw_jump_scale(const struct brw_device_info
*devinfo
)
358 /* Broadwell measures jump targets in bytes. */
359 if (devinfo
->gen
>= 8)
362 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
363 * (to support compaction), so each 128-bit instruction requires 2 chunks.
365 if (devinfo
->gen
>= 5)
368 /* Gen4 simply uses the number of 128-bit instructions. */
372 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
374 /* If/else/endif. Works by manipulating the execution flags on each
377 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
378 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
379 struct brw_reg src0
, struct brw_reg src1
);
381 void brw_ELSE(struct brw_codegen
*p
);
382 void brw_ENDIF(struct brw_codegen
*p
);
386 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
388 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
390 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
391 brw_inst
*brw_CONT(struct brw_codegen
*p
);
392 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
396 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
398 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
399 unsigned predicate_control
);
401 void brw_NOP(struct brw_codegen
*p
);
403 void brw_WAIT(struct brw_codegen
*p
);
405 /* Special case: there is never a destination, execution size will be
408 void brw_CMP(struct brw_codegen
*p
,
410 unsigned conditional
,
412 struct brw_reg src1
);
415 brw_untyped_atomic(struct brw_codegen
*p
,
417 struct brw_reg payload
,
418 struct brw_reg surface
,
421 bool response_expected
);
424 brw_untyped_surface_read(struct brw_codegen
*p
,
426 struct brw_reg payload
,
427 struct brw_reg surface
,
429 unsigned num_channels
);
432 brw_untyped_surface_write(struct brw_codegen
*p
,
433 struct brw_reg payload
,
434 struct brw_reg surface
,
436 unsigned num_channels
);
439 brw_typed_atomic(struct brw_codegen
*p
,
441 struct brw_reg payload
,
442 struct brw_reg surface
,
445 bool response_expected
);
448 brw_typed_surface_read(struct brw_codegen
*p
,
450 struct brw_reg payload
,
451 struct brw_reg surface
,
453 unsigned num_channels
);
456 brw_typed_surface_write(struct brw_codegen
*p
,
457 struct brw_reg payload
,
458 struct brw_reg surface
,
460 unsigned num_channels
);
463 brw_memory_fence(struct brw_codegen
*p
,
467 brw_pixel_interpolator_query(struct brw_codegen
*p
,
474 unsigned response_length
);
477 brw_find_live_channel(struct brw_codegen
*p
,
481 brw_broadcast(struct brw_codegen
*p
,
486 /***********************************************************************
490 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
491 struct brw_indirect dst_ptr
,
492 struct brw_indirect src_ptr
,
495 void brw_copy_from_indirect(struct brw_codegen
*p
,
497 struct brw_indirect ptr
,
500 void brw_copy4(struct brw_codegen
*p
,
505 void brw_copy8(struct brw_codegen
*p
,
510 void brw_math_invert( struct brw_codegen
*p
,
514 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
516 void brw_set_uip_jip(struct brw_codegen
*p
);
518 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
519 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
521 /* brw_eu_compact.c */
522 void brw_init_compaction_tables(const struct brw_device_info
*devinfo
);
523 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
524 int num_annotations
, struct annotation
*annotation
);
525 void brw_uncompact_instruction(const struct brw_device_info
*devinfo
,
526 brw_inst
*dst
, brw_compact_inst
*src
);
527 bool brw_try_compact_instruction(const struct brw_device_info
*devinfo
,
528 brw_compact_inst
*dst
, brw_inst
*src
);
530 void brw_debug_compact_uncompact(const struct brw_device_info
*devinfo
,
531 brw_inst
*orig
, brw_inst
*uncompacted
);
533 /* brw_eu_validate.c */
534 bool brw_validate_instructions(const struct brw_codegen
*p
, int start_offset
,
535 struct annotation_info
*annotation
);
538 next_offset(const struct brw_device_info
*devinfo
, void *store
, int offset
)
540 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
542 if (brw_inst_cmpt_control(devinfo
, insn
))
549 /* The union is an implementation detail used by brw_opcode_desc() to handle
550 * opcodes that have been reused for different instructions across hardware
553 * The gens field acts as a tag. If it is non-zero, name points to a string
554 * containing the instruction mnemonic. If it is zero, the table field is
555 * valid and either points to a secondary opcode_desc table with 'size'
556 * elements or is NULL and no such instruction exists for the opcode.
564 const struct opcode_desc
*table
;
572 const struct opcode_desc
*
573 brw_opcode_desc(const struct brw_device_info
*devinfo
, enum opcode opcode
);
576 is_3src(const struct brw_device_info
*devinfo
, enum opcode opcode
)
578 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
579 return desc
&& desc
->nsrc
== 3;
582 /** Maximum SEND message length */
583 #define BRW_MAX_MSG_LENGTH 15
585 /** First MRF register used by pull loads */
586 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
588 /** First MRF register used by spills */
589 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)