src/mesa/drivers/dri/i965/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include "brw_structs.h"
  37 #include "brw_defines.h"
  38 #include "shader/program.h"
  39
  40 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
  41 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
  42
  43 #define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)
  44 #define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)
  45 #define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)
  46 #define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)
  47
  48
  49 #define REG_SIZE (8*4)
  50
  51
  52 /* These aren't hardware structs, just something useful for us to pass around:
  53  *
  54  * Align1 operation has a lot of control over input ranges.  Used in
  55  * WM programs to implement shaders decomposed into "channel serial"
  56  * or "structure of array" form:
  57  */
  58 struct brw_reg
  59 {
  60    GLuint type:4;
  61    GLuint file:2;
  62    GLuint nr:8;
  63    GLuint subnr:5;              /* :1 in align16 */
  64    GLuint negate:1;             /* source only */
  65    GLuint abs:1;                /* source only */
  66    GLuint vstride:4;            /* source only */
  67    GLuint width:3;              /* src only, align1 only */
  68    GLuint hstride:2;            /* src only, align1 only */
  69    GLuint address_mode:1;       /* relative addressing, hopefully! */
  70    GLuint pad0:1;
  71
  72    union {
  73       struct {
  74          GLuint swizzle:8;              /* src only, align16 only */
  75          GLuint writemask:4;            /* dest only, align16 only */
  76          GLint  indirect_offset:10;     /* relative addressing offset */
  77          GLuint pad1:10;                /* two dwords total */
  78       } bits;
  79
  80       GLfloat f;
  81       GLint   d;
  82       GLuint ud;
  83    } dw1;
  84 };
  85
  86
  87 struct brw_indirect {
  88    GLuint addr_subnr:4;
  89    GLint addr_offset:10;
  90    GLuint pad:18;
  91 };
  92
  93
  94 #define BRW_EU_MAX_INSN_STACK 5
  95 #define BRW_EU_MAX_INSN 1200
  96
  97 struct brw_compile {
  98    struct brw_instruction store[BRW_EU_MAX_INSN];
  99    GLuint nr_insn;
 100
 101    /* Allow clients to push/pop instruction state:
 102     */
 103    struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
 104    struct brw_instruction *current;
 105
 106    GLuint flag_value;
 107    GLboolean single_program_flow;
 108 };
 109
 110
 111
 112 static __inline int type_sz( GLuint type )
 113 {
 114    switch( type ) {
 115    case BRW_REGISTER_TYPE_UD:
 116    case BRW_REGISTER_TYPE_D:
 117    case BRW_REGISTER_TYPE_F:
 118       return 4;
 119    case BRW_REGISTER_TYPE_HF:
 120    case BRW_REGISTER_TYPE_UW:
 121    case BRW_REGISTER_TYPE_W:
 122       return 2;
 123    case BRW_REGISTER_TYPE_UB:
 124    case BRW_REGISTER_TYPE_B:
 125       return 1;
 126    default:
 127       return 0;
 128    }
 129 }
 130
 131 static __inline struct brw_reg brw_reg( GLuint file,
 132                                         GLuint nr,
 133                                         GLuint subnr,
 134                                         GLuint type,
 135                                         GLuint vstride,
 136                                         GLuint width,
 137                                         GLuint hstride,
 138                                         GLuint swizzle,
 139                                         GLuint writemask)
 140 {
 141
 142    struct brw_reg reg;
 143    reg.type = type;
 144    reg.file = file;
 145    reg.nr = nr;
 146    reg.subnr = subnr * type_sz(type);
 147    reg.negate = 0;
 148    reg.abs = 0;
 149    reg.vstride = vstride;
 150    reg.width = width;
 151    reg.hstride = hstride;
 152    reg.address_mode = BRW_ADDRESS_DIRECT;
 153    reg.pad0 = 0;
 154
 155    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
 156     * set swizzle and writemask to W, as the lower bits of subnr will
 157     * be lost when converted to align16.  This is probably too much to
 158     * keep track of as you'd want it adjusted by suboffset(), etc.
 159     * Perhaps fix up when converting to align16?
 160     */
 161    reg.dw1.bits.swizzle = swizzle;
 162    reg.dw1.bits.writemask = writemask;
 163    reg.dw1.bits.indirect_offset = 0;
 164    reg.dw1.bits.pad1 = 0;
 165    return reg;
 166 }
 167
 168 static __inline struct brw_reg brw_vec16_reg( GLuint file,
 169                                               GLuint nr,
 170                                               GLuint subnr )
 171 {
 172    return brw_reg(file,
 173                   nr,
 174                   subnr,
 175                   BRW_REGISTER_TYPE_F,
 176                   BRW_VERTICAL_STRIDE_16,
 177                   BRW_WIDTH_16,
 178                   BRW_HORIZONTAL_STRIDE_1,
 179                   BRW_SWIZZLE_XYZW,
 180                   WRITEMASK_XYZW);
 181 }
 182
 183 static __inline struct brw_reg brw_vec8_reg( GLuint file,
 184                                              GLuint nr,
 185                                              GLuint subnr )
 186 {
 187    return brw_reg(file,
 188                   nr,
 189                   subnr,
 190                   BRW_REGISTER_TYPE_F,
 191                   BRW_VERTICAL_STRIDE_8,
 192                   BRW_WIDTH_8,
 193                   BRW_HORIZONTAL_STRIDE_1,
 194                   BRW_SWIZZLE_XYZW,
 195                   WRITEMASK_XYZW);
 196 }
 197
 198
 199 static __inline struct brw_reg brw_vec4_reg( GLuint file,
 200                                               GLuint nr,
 201                                               GLuint subnr )
 202 {
 203    return brw_reg(file,
 204                   nr,
 205                   subnr,
 206                   BRW_REGISTER_TYPE_F,
 207                   BRW_VERTICAL_STRIDE_4,
 208                   BRW_WIDTH_4,
 209                   BRW_HORIZONTAL_STRIDE_1,
 210                   BRW_SWIZZLE_XYZW,
 211                   WRITEMASK_XYZW);
 212 }
 213
 214
 215 static __inline struct brw_reg brw_vec2_reg( GLuint file,
 216                                               GLuint nr,
 217                                               GLuint subnr )
 218 {
 219    return brw_reg(file,
 220                   nr,
 221                   subnr,
 222                   BRW_REGISTER_TYPE_F,
 223                   BRW_VERTICAL_STRIDE_2,
 224                   BRW_WIDTH_2,
 225                   BRW_HORIZONTAL_STRIDE_1,
 226                   BRW_SWIZZLE_XYXY,
 227                   WRITEMASK_XY);
 228 }
 229
 230 static __inline struct brw_reg brw_vec1_reg( GLuint file,
 231                                              GLuint nr,
 232                                              GLuint subnr )
 233 {
 234    return brw_reg(file,
 235                   nr,
 236                   subnr,
 237                   BRW_REGISTER_TYPE_F,
 238                   BRW_VERTICAL_STRIDE_0,
 239                   BRW_WIDTH_1,
 240                   BRW_HORIZONTAL_STRIDE_0,
 241                   BRW_SWIZZLE_XXXX,
 242                   WRITEMASK_X);
 243 }
 244
 245
 246 static __inline struct brw_reg retype( struct brw_reg reg,
 247                                        GLuint type )
 248 {
 249    reg.type = type;
 250    return reg;
 251 }
 252
 253 static __inline struct brw_reg suboffset( struct brw_reg reg,
 254                                           GLuint delta )
 255 {
 256    reg.subnr += delta * type_sz(reg.type);
 257    return reg;
 258 }
 259
 260
 261 static __inline struct brw_reg offset( struct brw_reg reg,
 262                                        GLuint delta )
 263 {
 264    reg.nr += delta;
 265    return reg;
 266 }
 267
 268
 269 static __inline struct brw_reg byte_offset( struct brw_reg reg,
 270                                             GLuint bytes )
 271 {
 272    GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
 273    reg.nr = newoffset / REG_SIZE;
 274    reg.subnr = newoffset % REG_SIZE;
 275    return reg;
 276 }
 277
 278
 279 static __inline struct brw_reg brw_uw16_reg( GLuint file,
 280                                              GLuint nr,
 281                                              GLuint subnr )
 282 {
 283    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 284 }
 285
 286 static __inline struct brw_reg brw_uw8_reg( GLuint file,
 287                                             GLuint nr,
 288                                             GLuint subnr )
 289 {
 290    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 291 }
 292
 293 static __inline struct brw_reg brw_uw1_reg( GLuint file,
 294                                             GLuint nr,
 295                                             GLuint subnr )
 296 {
 297    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 298 }
 299
 300 static __inline struct brw_reg brw_imm_reg( GLuint type )
 301 {
 302    return brw_reg( BRW_IMMEDIATE_VALUE,
 303                    0,
 304                    0,
 305                    type,
 306                    BRW_VERTICAL_STRIDE_0,
 307                    BRW_WIDTH_1,
 308                    BRW_HORIZONTAL_STRIDE_0,
 309                    0,
 310                    0);
 311 }
 312
 313 static __inline struct brw_reg brw_imm_f( GLfloat f )
 314 {
 315    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
 316    imm.dw1.f = f;
 317    return imm;
 318 }
 319
 320 static __inline struct brw_reg brw_imm_d( GLint d )
 321 {
 322    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
 323    imm.dw1.d = d;
 324    return imm;
 325 }
 326
 327 static __inline struct brw_reg brw_imm_ud( GLuint ud )
 328 {
 329    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
 330    imm.dw1.ud = ud;
 331    return imm;
 332 }
 333
 334 static __inline struct brw_reg brw_imm_uw( GLushort uw )
 335 {
 336    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
 337    imm.dw1.ud = uw;
 338    return imm;
 339 }
 340
 341 static __inline struct brw_reg brw_imm_w( GLshort w )
 342 {
 343    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
 344    imm.dw1.d = w;
 345    return imm;
 346 }
 347
 348 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
 349  * numbers alias with _V and _VF below:
 350  */
 351
 352 /* Vector of eight signed half-byte values:
 353  */
 354 static __inline struct brw_reg brw_imm_v( GLuint v )
 355 {
 356    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
 357    imm.vstride = BRW_VERTICAL_STRIDE_0;
 358    imm.width = BRW_WIDTH_8;
 359    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 360    imm.dw1.ud = v;
 361    return imm;
 362 }
 363
 364 /* Vector of four 8-bit float values:
 365  */
 366 static __inline struct brw_reg brw_imm_vf( GLuint v )
 367 {
 368    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 369    imm.vstride = BRW_VERTICAL_STRIDE_0;
 370    imm.width = BRW_WIDTH_4;
 371    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 372    imm.dw1.ud = v;
 373    return imm;
 374 }
 375
 376 #define VF_ZERO 0x0
 377 #define VF_ONE  0x30
 378 #define VF_NEG  (1<<7)
 379
 380 static __inline struct brw_reg brw_imm_vf4( GLuint v0,
 381                                             GLuint v1,
 382                                             GLuint v2,
 383                                             GLuint v3)
 384 {
 385    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 386    imm.vstride = BRW_VERTICAL_STRIDE_0;
 387    imm.width = BRW_WIDTH_4;
 388    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 389    imm.dw1.ud = ((v0 << 0) |
 390                  (v1 << 8) |
 391                  (v2 << 16) |
 392                  (v3 << 24));
 393    return imm;
 394 }
 395
 396
 397 static __inline struct brw_reg brw_address( struct brw_reg reg )
 398 {
 399    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 400 }
 401
 402
 403 static __inline struct brw_reg brw_vec1_grf( GLuint nr,
 404                                                GLuint subnr )
 405 {
 406    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 407 }
 408
 409 static __inline struct brw_reg brw_vec8_grf( GLuint nr,
 410                                              GLuint subnr )
 411 {
 412    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 413 }
 414
 415 static __inline struct brw_reg brw_vec4_grf( GLuint nr,
 416                                              GLuint subnr )
 417 {
 418    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 419 }
 420
 421
 422 static __inline struct brw_reg brw_vec2_grf( GLuint nr,
 423                                              GLuint subnr )
 424 {
 425    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 426 }
 427
 428 static __inline struct brw_reg brw_uw8_grf( GLuint nr,
 429                                             GLuint subnr )
 430 {
 431    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 432 }
 433
 434 static __inline struct brw_reg brw_null_reg( void )
 435 {
 436    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 437                        BRW_ARF_NULL,
 438                        0);
 439 }
 440
 441 static __inline struct brw_reg brw_address_reg( GLuint subnr )
 442 {
 443    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 444                       BRW_ARF_ADDRESS,
 445                       subnr);
 446 }
 447
 448 /* If/else instructions break in align16 mode if writemask & swizzle
 449  * aren't xyzw.  This goes against the convention for other scalar
 450  * regs:
 451  */
 452 static __inline struct brw_reg brw_ip_reg( void )
 453 {
 454    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 455                   BRW_ARF_IP,
 456                   0,
 457                   BRW_REGISTER_TYPE_UD,
 458                   BRW_VERTICAL_STRIDE_4, /* ? */
 459                   BRW_WIDTH_1,
 460                   BRW_HORIZONTAL_STRIDE_0,
 461                   BRW_SWIZZLE_XYZW, /* NOTE! */
 462                   WRITEMASK_XYZW); /* NOTE! */
 463 }
 464
 465 static __inline struct brw_reg brw_acc_reg( void )
 466 {
 467    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 468                        BRW_ARF_ACCUMULATOR,
 469                        0);
 470 }
 471
 472
 473 static __inline struct brw_reg brw_flag_reg( void )
 474 {
 475    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 476                       BRW_ARF_FLAG,
 477                       0);
 478 }
 479
 480
 481 static __inline struct brw_reg brw_mask_reg( GLuint subnr )
 482 {
 483    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 484                       BRW_ARF_MASK,
 485                       subnr);
 486 }
 487
 488 static __inline struct brw_reg brw_message_reg( GLuint nr )
 489 {
 490    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE,
 491                        nr,
 492                        0);
 493 }
 494
 495
 496
 497
 498 /* This is almost always called with a numeric constant argument, so
 499  * make things easy to evaluate at compile time:
 500  */
 501 static __inline GLuint cvt( GLuint val )
 502 {
 503    switch (val) {
 504    case 0: return 0;
 505    case 1: return 1;
 506    case 2: return 2;
 507    case 4: return 3;
 508    case 8: return 4;
 509    case 16: return 5;
 510    case 32: return 6;
 511    }
 512    return 0;
 513 }
 514
 515 static __inline struct brw_reg stride( struct brw_reg reg,
 516                                        GLuint vstride,
 517                                        GLuint width,
 518                                        GLuint hstride )
 519 {
 520
 521    reg.vstride = cvt(vstride);
 522    reg.width = cvt(width) - 1;
 523    reg.hstride = cvt(hstride);
 524    return reg;
 525 }
 526
 527 static __inline struct brw_reg vec16( struct brw_reg reg )
 528 {
 529    return stride(reg, 16,16,1);
 530 }
 531
 532 static __inline struct brw_reg vec8( struct brw_reg reg )
 533 {
 534    return stride(reg, 8,8,1);
 535 }
 536
 537 static __inline struct brw_reg vec4( struct brw_reg reg )
 538 {
 539    return stride(reg, 4,4,1);
 540 }
 541
 542 static __inline struct brw_reg vec2( struct brw_reg reg )
 543 {
 544    return stride(reg, 2,2,1);
 545 }
 546
 547 static __inline struct brw_reg vec1( struct brw_reg reg )
 548 {
 549    return stride(reg, 0,1,0);
 550 }
 551
 552 static __inline struct brw_reg get_element( struct brw_reg reg, GLuint elt )
 553 {
 554    return vec1(suboffset(reg, elt));
 555 }
 556
 557 static __inline struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt )
 558 {
 559    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
 560 }
 561
 562
 563 static __inline struct brw_reg brw_swizzle( struct brw_reg reg,
 564                                             GLuint x,
 565                                             GLuint y,
 566                                             GLuint z,
 567                                             GLuint w)
 568 {
 569    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
 570                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
 571                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
 572                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
 573    return reg;
 574 }
 575
 576
 577 static __inline struct brw_reg brw_swizzle1( struct brw_reg reg,
 578                                              GLuint x )
 579 {
 580    return brw_swizzle(reg, x, x, x, x);
 581 }
 582
 583 static __inline struct brw_reg brw_writemask( struct brw_reg reg,
 584                                               GLuint mask )
 585 {
 586    reg.dw1.bits.writemask &= mask;
 587    return reg;
 588 }
 589
 590 static __inline struct brw_reg brw_set_writemask( struct brw_reg reg,
 591                                                   GLuint mask )
 592 {
 593    reg.dw1.bits.writemask = mask;
 594    return reg;
 595 }
 596
 597 static __inline struct brw_reg negate( struct brw_reg reg )
 598 {
 599    reg.negate ^= 1;
 600    return reg;
 601 }
 602
 603 static __inline struct brw_reg brw_abs( struct brw_reg reg )
 604 {
 605    reg.abs = 1;
 606    return reg;
 607 }
 608
 609 /***********************************************************************
 610  */
 611 static __inline struct brw_reg brw_vec4_indirect( GLuint subnr,
 612                                                   GLint offset )
 613 {
 614    struct brw_reg reg =  brw_vec4_grf(0, 0);
 615    reg.subnr = subnr;
 616    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 617    reg.dw1.bits.indirect_offset = offset;
 618    return reg;
 619 }
 620
 621 static __inline struct brw_reg brw_vec1_indirect( GLuint subnr,
 622                                                   GLint offset )
 623 {
 624    struct brw_reg reg =  brw_vec1_grf(0, 0);
 625    reg.subnr = subnr;
 626    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 627    reg.dw1.bits.indirect_offset = offset;
 628    return reg;
 629 }
 630
 631 static __inline struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset)
 632 {
 633    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 634 }
 635
 636 static __inline struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset)
 637 {
 638    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 639 }
 640
 641 static __inline struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset)
 642 {
 643    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
 644 }
 645
 646 static __inline struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset)
 647 {
 648    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
 649 }
 650
 651 static __inline struct brw_reg get_addr_reg(struct brw_indirect ptr)
 652 {
 653    return brw_address_reg(ptr.addr_subnr);
 654 }
 655
 656 static __inline struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset )
 657 {
 658    ptr.addr_offset += offset;
 659    return ptr;
 660 }
 661
 662 static __inline struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset )
 663 {
 664    struct brw_indirect ptr;
 665    ptr.addr_subnr = addr_subnr;
 666    ptr.addr_offset = offset;
 667    ptr.pad = 0;
 668    return ptr;
 669 }
 670
 671
 672
 673 void brw_pop_insn_state( struct brw_compile *p );
 674 void brw_push_insn_state( struct brw_compile *p );
 675 void brw_set_mask_control( struct brw_compile *p, GLuint value );
 676 void brw_set_saturate( struct brw_compile *p, GLuint value );
 677 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );
 678 void brw_set_compression_control( struct brw_compile *p, GLboolean control );
 679 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
 680 void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
 681 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
 682
 683 void brw_init_compile( struct brw_compile *p );
 684 const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
 685
 686
 687 /* Helpers for regular instructions:
 688  */
 689 #define ALU1(OP)                                        \
 690 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 691               struct brw_reg dest,                      \
 692               struct brw_reg src0);
 693
 694 #define ALU2(OP)                                        \
 695 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 696               struct brw_reg dest,                      \
 697               struct brw_reg src0,                      \
 698               struct brw_reg src1);
 699
 700 ALU1(MOV)
 701 ALU2(SEL)
 702 ALU1(NOT)
 703 ALU2(AND)
 704 ALU2(OR)
 705 ALU2(XOR)
 706 ALU2(SHR)
 707 ALU2(SHL)
 708 ALU2(RSR)
 709 ALU2(RSL)
 710 ALU2(ASR)
 711 ALU2(JMPI)
 712 ALU2(ADD)
 713 ALU2(MUL)
 714 ALU1(FRC)
 715 ALU1(RNDD)
 716 ALU2(MAC)
 717 ALU2(MACH)
 718 ALU1(LZD)
 719 ALU2(DP4)
 720 ALU2(DPH)
 721 ALU2(DP3)
 722 ALU2(DP2)
 723 ALU2(LINE)
 724
 725 #undef ALU1
 726 #undef ALU2
 727
 728
 729
 730 /* Helpers for SEND instruction:
 731  */
 732 void brw_urb_WRITE(struct brw_compile *p,
 733                    struct brw_reg dest,
 734                    GLuint msg_reg_nr,
 735                    struct brw_reg src0,
 736                    GLboolean allocate,
 737                    GLboolean used,
 738                    GLuint msg_length,
 739                    GLuint response_length,
 740                    GLboolean eot,
 741                    GLboolean writes_complete,
 742                    GLuint offset,
 743                    GLuint swizzle);
 744
 745 void brw_fb_WRITE(struct brw_compile *p,
 746                    struct brw_reg dest,
 747                    GLuint msg_reg_nr,
 748                    struct brw_reg src0,
 749                    GLuint binding_table_index,
 750                    GLuint msg_length,
 751                    GLuint response_length,
 752                    GLboolean eot);
 753
 754 void brw_SAMPLE(struct brw_compile *p,
 755                 struct brw_reg dest,
 756                 GLuint msg_reg_nr,
 757                 struct brw_reg src0,
 758                 GLuint binding_table_index,
 759                 GLuint sampler,
 760                 GLuint writemask,
 761                 GLuint msg_type,
 762                 GLuint response_length,
 763                 GLuint msg_length,
 764                 GLboolean eot);
 765
 766 void brw_math_16( struct brw_compile *p,
 767                   struct brw_reg dest,
 768                   GLuint function,
 769                   GLuint saturate,
 770                   GLuint msg_reg_nr,
 771                   struct brw_reg src,
 772                   GLuint precision );
 773
 774 void brw_math( struct brw_compile *p,
 775                struct brw_reg dest,
 776                GLuint function,
 777                GLuint saturate,
 778                GLuint msg_reg_nr,
 779                struct brw_reg src,
 780                GLuint data_type,
 781                GLuint precision );
 782
 783 void brw_dp_READ_16( struct brw_compile *p,
 784                      struct brw_reg dest,
 785                      GLuint msg_reg_nr,
 786                      GLuint scratch_offset );
 787
 788 void brw_dp_WRITE_16( struct brw_compile *p,
 789                       struct brw_reg src,
 790                       GLuint msg_reg_nr,
 791                       GLuint scratch_offset );
 792
 793 /* If/else/endif.  Works by manipulating the execution flags on each
 794  * channel.
 795  */
 796 struct brw_instruction *brw_IF(struct brw_compile *p,
 797                                GLuint execute_size);
 798
 799 struct brw_instruction *brw_ELSE(struct brw_compile *p,
 800                                  struct brw_instruction *if_insn);
 801
 802 void brw_ENDIF(struct brw_compile *p,
 803                struct brw_instruction *if_or_else_insn);
 804
 805
 806 /* DO/WHILE loops:
 807  */
 808 struct brw_instruction *brw_DO(struct brw_compile *p,
 809                                GLuint execute_size);
 810
 811 void brw_WHILE(struct brw_compile *p,
 812                struct brw_instruction *patch_insn);
 813
 814 /* Forward jumps:
 815  */
 816 void brw_land_fwd_jump(struct brw_compile *p,
 817                        struct brw_instruction *jmp_insn);
 818
 819
 820
 821 void brw_NOP(struct brw_compile *p);
 822
 823 /* Special case: there is never a destination, execution size will be
 824  * taken from src0:
 825  */
 826 void brw_CMP(struct brw_compile *p,
 827              struct brw_reg dest,
 828              GLuint conditional,
 829              struct brw_reg src0,
 830              struct brw_reg src1);
 831
 832 void brw_print_reg( struct brw_reg reg );
 833
 834
 835 /***********************************************************************
 836  * brw_eu_util.c:
 837  */
 838
 839 void brw_copy_indirect_to_indirect(struct brw_compile *p,
 840                                    struct brw_indirect dst_ptr,
 841                                    struct brw_indirect src_ptr,
 842                                    GLuint count);
 843
 844 void brw_copy_from_indirect(struct brw_compile *p,
 845                             struct brw_reg dst,
 846                             struct brw_indirect ptr,
 847                             GLuint count);
 848
 849 void brw_copy4(struct brw_compile *p,
 850                struct brw_reg dst,
 851                struct brw_reg src,
 852                GLuint count);
 853
 854 void brw_copy8(struct brw_compile *p,
 855                struct brw_reg dst,
 856                struct brw_reg src,
 857                GLuint count);
 858
 859 void brw_math_invert( struct brw_compile *p,
 860                       struct brw_reg dst,
 861                       struct brw_reg src);
 862
 863
 864 #endif