2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "brw_structs.h"
38 #include "brw_defines.h"
39 #include "program/prog_instruction.h"
41 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
42 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
44 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
45 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
46 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
47 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
48 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
49 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
50 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
53 #define REG_SIZE (8*4)
56 /* These aren't hardware structs, just something useful for us to pass around:
58 * Align1 operation has a lot of control over input ranges. Used in
59 * WM programs to implement shaders decomposed into "channel serial"
60 * or "structure of array" form:
67 GLuint subnr
:5; /* :1 in align16 */
68 GLuint negate
:1; /* source only */
69 GLuint abs
:1; /* source only */
70 GLuint vstride
:4; /* source only */
71 GLuint width
:3; /* src only, align1 only */
72 GLuint hstride
:2; /* align1 only */
73 GLuint address_mode
:1; /* relative addressing, hopefully! */
78 GLuint swizzle
:8; /* src only, align16 only */
79 GLuint writemask
:4; /* dest only, align16 only */
80 GLint indirect_offset
:10; /* relative addressing offset */
81 GLuint pad1
:10; /* two dwords total */
98 struct brw_glsl_label
;
103 #define BRW_EU_MAX_INSN_STACK 5
106 struct brw_instruction
*store
;
112 /* Allow clients to push/pop instruction state:
114 struct brw_instruction stack
[BRW_EU_MAX_INSN_STACK
];
115 bool compressed_stack
[BRW_EU_MAX_INSN_STACK
];
116 struct brw_instruction
*current
;
119 bool single_program_flow
;
121 struct brw_context
*brw
;
123 /* Control flow stacks:
124 * - if_stack contains IF and ELSE instructions which must be patched
125 * (and popped) once the matching ENDIF instruction is encountered.
127 * Just store the instruction pointer(an index).
131 int if_stack_array_size
;
134 * loop_stack contains the instruction pointers of the starts of loops which
135 * must be patched (and popped) once the matching WHILE instruction is
140 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
141 * blocks they were popping out of, to fix up the mask stack. This tracks
142 * the IF/ENDIF nesting in each current nested loop level.
144 int *if_depth_in_loop
;
145 int loop_stack_depth
;
146 int loop_stack_array_size
;
148 struct brw_glsl_label
*first_label
; /**< linked list of labels */
149 struct brw_glsl_call
*first_call
; /**< linked list of CALs */
154 brw_save_label(struct brw_compile
*c
, const char *name
, GLuint position
);
157 brw_save_call(struct brw_compile
*c
, const char *name
, GLuint call_pos
);
160 brw_resolve_cals(struct brw_compile
*c
);
164 static INLINE
int type_sz( GLuint type
)
167 case BRW_REGISTER_TYPE_UD
:
168 case BRW_REGISTER_TYPE_D
:
169 case BRW_REGISTER_TYPE_F
:
171 case BRW_REGISTER_TYPE_HF
:
172 case BRW_REGISTER_TYPE_UW
:
173 case BRW_REGISTER_TYPE_W
:
175 case BRW_REGISTER_TYPE_UB
:
176 case BRW_REGISTER_TYPE_B
:
184 * Construct a brw_reg.
185 * \param file one of the BRW_x_REGISTER_FILE values
186 * \param nr register number/index
187 * \param subnr register sub number
188 * \param type one of BRW_REGISTER_TYPE_x
189 * \param vstride one of BRW_VERTICAL_STRIDE_x
190 * \param width one of BRW_WIDTH_x
191 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
192 * \param swizzle one of BRW_SWIZZLE_x
193 * \param writemask WRITEMASK_X/Y/Z/W bitfield
195 static INLINE
struct brw_reg
brw_reg( GLuint file
,
206 if (file
== BRW_GENERAL_REGISTER_FILE
)
207 assert(nr
< BRW_MAX_GRF
);
208 else if (file
== BRW_MESSAGE_REGISTER_FILE
)
209 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
210 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
211 assert(nr
<= BRW_ARF_IP
);
216 reg
.subnr
= subnr
* type_sz(type
);
219 reg
.vstride
= vstride
;
221 reg
.hstride
= hstride
;
222 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
225 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
226 * set swizzle and writemask to W, as the lower bits of subnr will
227 * be lost when converted to align16. This is probably too much to
228 * keep track of as you'd want it adjusted by suboffset(), etc.
229 * Perhaps fix up when converting to align16?
231 reg
.dw1
.bits
.swizzle
= swizzle
;
232 reg
.dw1
.bits
.writemask
= writemask
;
233 reg
.dw1
.bits
.indirect_offset
= 0;
234 reg
.dw1
.bits
.pad1
= 0;
238 /** Construct float[16] register */
239 static INLINE
struct brw_reg
brw_vec16_reg( GLuint file
,
247 BRW_VERTICAL_STRIDE_16
,
249 BRW_HORIZONTAL_STRIDE_1
,
254 /** Construct float[8] register */
255 static INLINE
struct brw_reg
brw_vec8_reg( GLuint file
,
263 BRW_VERTICAL_STRIDE_8
,
265 BRW_HORIZONTAL_STRIDE_1
,
270 /** Construct float[4] register */
271 static INLINE
struct brw_reg
brw_vec4_reg( GLuint file
,
279 BRW_VERTICAL_STRIDE_4
,
281 BRW_HORIZONTAL_STRIDE_1
,
286 /** Construct float[2] register */
287 static INLINE
struct brw_reg
brw_vec2_reg( GLuint file
,
295 BRW_VERTICAL_STRIDE_2
,
297 BRW_HORIZONTAL_STRIDE_1
,
302 /** Construct float[1] register */
303 static INLINE
struct brw_reg
brw_vec1_reg( GLuint file
,
311 BRW_VERTICAL_STRIDE_0
,
313 BRW_HORIZONTAL_STRIDE_0
,
319 static INLINE
struct brw_reg
retype( struct brw_reg reg
,
326 static inline struct brw_reg
327 sechalf(struct brw_reg reg
)
334 static INLINE
struct brw_reg
suboffset( struct brw_reg reg
,
337 reg
.subnr
+= delta
* type_sz(reg
.type
);
342 static INLINE
struct brw_reg
offset( struct brw_reg reg
,
350 static INLINE
struct brw_reg
byte_offset( struct brw_reg reg
,
353 GLuint newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
354 reg
.nr
= newoffset
/ REG_SIZE
;
355 reg
.subnr
= newoffset
% REG_SIZE
;
360 /** Construct unsigned word[16] register */
361 static INLINE
struct brw_reg
brw_uw16_reg( GLuint file
,
365 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
368 /** Construct unsigned word[8] register */
369 static INLINE
struct brw_reg
brw_uw8_reg( GLuint file
,
373 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
376 /** Construct unsigned word[1] register */
377 static INLINE
struct brw_reg
brw_uw1_reg( GLuint file
,
381 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
384 static INLINE
struct brw_reg
brw_imm_reg( GLuint type
)
386 return brw_reg( BRW_IMMEDIATE_VALUE
,
390 BRW_VERTICAL_STRIDE_0
,
392 BRW_HORIZONTAL_STRIDE_0
,
397 /** Construct float immediate register */
398 static INLINE
struct brw_reg
brw_imm_f( GLfloat f
)
400 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
405 /** Construct integer immediate register */
406 static INLINE
struct brw_reg
brw_imm_d( GLint d
)
408 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
413 /** Construct uint immediate register */
414 static INLINE
struct brw_reg
brw_imm_ud( GLuint ud
)
416 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
421 /** Construct ushort immediate register */
422 static INLINE
struct brw_reg
brw_imm_uw( GLushort uw
)
424 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
425 imm
.dw1
.ud
= uw
| (uw
<< 16);
429 /** Construct short immediate register */
430 static INLINE
struct brw_reg
brw_imm_w( GLshort w
)
432 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
433 imm
.dw1
.d
= w
| (w
<< 16);
437 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
438 * numbers alias with _V and _VF below:
441 /** Construct vector of eight signed half-byte values */
442 static INLINE
struct brw_reg
brw_imm_v( GLuint v
)
444 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
445 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
446 imm
.width
= BRW_WIDTH_8
;
447 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
452 /** Construct vector of four 8-bit float values */
453 static INLINE
struct brw_reg
brw_imm_vf( GLuint v
)
455 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
456 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
457 imm
.width
= BRW_WIDTH_4
;
458 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
465 #define VF_NEG (1<<7)
467 static INLINE
struct brw_reg
brw_imm_vf4( GLuint v0
,
472 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
473 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
474 imm
.width
= BRW_WIDTH_4
;
475 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
476 imm
.dw1
.ud
= ((v0
<< 0) |
484 static INLINE
struct brw_reg
brw_address( struct brw_reg reg
)
486 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
489 /** Construct float[1] general-purpose register */
490 static INLINE
struct brw_reg
brw_vec1_grf( GLuint nr
, GLuint subnr
)
492 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
495 /** Construct float[2] general-purpose register */
496 static INLINE
struct brw_reg
brw_vec2_grf( GLuint nr
, GLuint subnr
)
498 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
501 /** Construct float[4] general-purpose register */
502 static INLINE
struct brw_reg
brw_vec4_grf( GLuint nr
, GLuint subnr
)
504 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
507 /** Construct float[8] general-purpose register */
508 static INLINE
struct brw_reg
brw_vec8_grf( GLuint nr
, GLuint subnr
)
510 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
514 static INLINE
struct brw_reg
brw_uw8_grf( GLuint nr
, GLuint subnr
)
516 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
519 static INLINE
struct brw_reg
brw_uw16_grf( GLuint nr
, GLuint subnr
)
521 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
525 /** Construct null register (usually used for setting condition codes) */
526 static INLINE
struct brw_reg
brw_null_reg( void )
528 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
533 static INLINE
struct brw_reg
brw_address_reg( GLuint subnr
)
535 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
540 /* If/else instructions break in align16 mode if writemask & swizzle
541 * aren't xyzw. This goes against the convention for other scalar
544 static INLINE
struct brw_reg
brw_ip_reg( void )
546 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
549 BRW_REGISTER_TYPE_UD
,
550 BRW_VERTICAL_STRIDE_4
, /* ? */
552 BRW_HORIZONTAL_STRIDE_0
,
553 BRW_SWIZZLE_XYZW
, /* NOTE! */
554 WRITEMASK_XYZW
); /* NOTE! */
557 static INLINE
struct brw_reg
brw_acc_reg( void )
559 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
564 static INLINE
struct brw_reg
brw_notification_1_reg(void)
567 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
568 BRW_ARF_NOTIFICATION_COUNT
,
570 BRW_REGISTER_TYPE_UD
,
571 BRW_VERTICAL_STRIDE_0
,
573 BRW_HORIZONTAL_STRIDE_0
,
579 static INLINE
struct brw_reg
brw_flag_reg( void )
581 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
587 static INLINE
struct brw_reg
brw_mask_reg( GLuint subnr
)
589 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
594 static INLINE
struct brw_reg
brw_message_reg( GLuint nr
)
596 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
597 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
,
605 /* This is almost always called with a numeric constant argument, so
606 * make things easy to evaluate at compile time:
608 static INLINE GLuint
cvt( GLuint val
)
622 static INLINE
struct brw_reg
stride( struct brw_reg reg
,
627 reg
.vstride
= cvt(vstride
);
628 reg
.width
= cvt(width
) - 1;
629 reg
.hstride
= cvt(hstride
);
634 static INLINE
struct brw_reg
vec16( struct brw_reg reg
)
636 return stride(reg
, 16,16,1);
639 static INLINE
struct brw_reg
vec8( struct brw_reg reg
)
641 return stride(reg
, 8,8,1);
644 static INLINE
struct brw_reg
vec4( struct brw_reg reg
)
646 return stride(reg
, 4,4,1);
649 static INLINE
struct brw_reg
vec2( struct brw_reg reg
)
651 return stride(reg
, 2,2,1);
654 static INLINE
struct brw_reg
vec1( struct brw_reg reg
)
656 return stride(reg
, 0,1,0);
660 static INLINE
struct brw_reg
get_element( struct brw_reg reg
, GLuint elt
)
662 return vec1(suboffset(reg
, elt
));
665 static INLINE
struct brw_reg
get_element_ud( struct brw_reg reg
, GLuint elt
)
667 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
670 static INLINE
struct brw_reg
get_element_d( struct brw_reg reg
, GLuint elt
)
672 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
676 static INLINE
struct brw_reg
brw_swizzle( struct brw_reg reg
,
682 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
684 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, x
),
685 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, y
),
686 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, z
),
687 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, w
));
692 static INLINE
struct brw_reg
brw_swizzle1( struct brw_reg reg
,
695 return brw_swizzle(reg
, x
, x
, x
, x
);
698 static INLINE
struct brw_reg
brw_writemask( struct brw_reg reg
,
701 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
702 reg
.dw1
.bits
.writemask
&= mask
;
706 static INLINE
struct brw_reg
brw_set_writemask( struct brw_reg reg
,
709 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
710 reg
.dw1
.bits
.writemask
= mask
;
714 static INLINE
struct brw_reg
negate( struct brw_reg reg
)
720 static INLINE
struct brw_reg
brw_abs( struct brw_reg reg
)
727 /***********************************************************************
729 static INLINE
struct brw_reg
brw_vec4_indirect( GLuint subnr
,
732 struct brw_reg reg
= brw_vec4_grf(0, 0);
734 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
735 reg
.dw1
.bits
.indirect_offset
= offset
;
739 static INLINE
struct brw_reg
brw_vec1_indirect( GLuint subnr
,
742 struct brw_reg reg
= brw_vec1_grf(0, 0);
744 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
745 reg
.dw1
.bits
.indirect_offset
= offset
;
749 static INLINE
struct brw_reg
deref_4f(struct brw_indirect ptr
, GLint offset
)
751 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
754 static INLINE
struct brw_reg
deref_1f(struct brw_indirect ptr
, GLint offset
)
756 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
759 static INLINE
struct brw_reg
deref_4b(struct brw_indirect ptr
, GLint offset
)
761 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
764 static INLINE
struct brw_reg
deref_1uw(struct brw_indirect ptr
, GLint offset
)
766 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
769 static INLINE
struct brw_reg
deref_1d(struct brw_indirect ptr
, GLint offset
)
771 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
774 static INLINE
struct brw_reg
deref_1ud(struct brw_indirect ptr
, GLint offset
)
776 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
779 static INLINE
struct brw_reg
get_addr_reg(struct brw_indirect ptr
)
781 return brw_address_reg(ptr
.addr_subnr
);
784 static INLINE
struct brw_indirect
brw_indirect_offset( struct brw_indirect ptr
, GLint offset
)
786 ptr
.addr_offset
+= offset
;
790 static INLINE
struct brw_indirect
brw_indirect( GLuint addr_subnr
, GLint offset
)
792 struct brw_indirect ptr
;
793 ptr
.addr_subnr
= addr_subnr
;
794 ptr
.addr_offset
= offset
;
799 /** Do two brw_regs refer to the same register? */
801 brw_same_reg(struct brw_reg r1
, struct brw_reg r2
)
803 return r1
.file
== r2
.file
&& r1
.nr
== r2
.nr
;
806 static INLINE
struct brw_instruction
*current_insn( struct brw_compile
*p
)
808 return &p
->store
[p
->nr_insn
];
811 void brw_pop_insn_state( struct brw_compile
*p
);
812 void brw_push_insn_state( struct brw_compile
*p
);
813 void brw_set_mask_control( struct brw_compile
*p
, GLuint value
);
814 void brw_set_saturate( struct brw_compile
*p
, GLuint value
);
815 void brw_set_access_mode( struct brw_compile
*p
, GLuint access_mode
);
816 void brw_set_compression_control(struct brw_compile
*p
, enum brw_compression c
);
817 void brw_set_predicate_control_flag_value( struct brw_compile
*p
, GLuint value
);
818 void brw_set_predicate_control( struct brw_compile
*p
, GLuint pc
);
819 void brw_set_predicate_inverse(struct brw_compile
*p
, bool predicate_inverse
);
820 void brw_set_conditionalmod( struct brw_compile
*p
, GLuint conditional
);
821 void brw_set_acc_write_control(struct brw_compile
*p
, GLuint value
);
823 void brw_init_compile(struct brw_context
*, struct brw_compile
*p
,
825 const GLuint
*brw_get_program( struct brw_compile
*p
, GLuint
*sz
);
827 struct brw_instruction
*brw_next_insn(struct brw_compile
*p
, GLuint opcode
);
828 void brw_set_dest(struct brw_compile
*p
, struct brw_instruction
*insn
,
829 struct brw_reg dest
);
830 void brw_set_src0(struct brw_compile
*p
, struct brw_instruction
*insn
,
833 void gen6_resolve_implied_move(struct brw_compile
*p
,
837 /* Helpers for regular instructions:
840 struct brw_instruction *brw_##OP(struct brw_compile *p, \
841 struct brw_reg dest, \
842 struct brw_reg src0);
845 struct brw_instruction *brw_##OP(struct brw_compile *p, \
846 struct brw_reg dest, \
847 struct brw_reg src0, \
848 struct brw_reg src1);
851 void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
888 /* Helpers for SEND instruction:
890 void brw_set_dp_read_message(struct brw_compile
*p
,
891 struct brw_instruction
*insn
,
892 GLuint binding_table_index
,
897 GLuint response_length
);
899 void brw_set_dp_write_message(struct brw_compile
*p
,
900 struct brw_instruction
*insn
,
901 GLuint binding_table_index
,
906 GLuint last_render_target
,
907 GLuint response_length
,
908 GLuint end_of_thread
,
909 GLuint send_commit_msg
);
911 void brw_urb_WRITE(struct brw_compile
*p
,
918 GLuint response_length
,
920 bool writes_complete
,
924 void brw_ff_sync(struct brw_compile
*p
,
929 GLuint response_length
,
932 void brw_svb_write(struct brw_compile
*p
,
936 GLuint binding_table_index
,
937 bool send_commit_msg
);
939 void brw_fb_WRITE(struct brw_compile
*p
,
943 GLuint binding_table_index
,
945 GLuint response_length
,
947 bool header_present
);
949 void brw_SAMPLE(struct brw_compile
*p
,
953 GLuint binding_table_index
,
957 GLuint response_length
,
959 GLuint header_present
,
961 GLuint return_format
);
963 void brw_math_16( struct brw_compile
*p
,
971 void brw_math( struct brw_compile
*p
,
980 void brw_math2(struct brw_compile
*p
,
984 struct brw_reg src1
);
986 void brw_oword_block_read(struct brw_compile
*p
,
990 uint32_t bind_table_index
);
992 void brw_oword_block_read_scratch(struct brw_compile
*p
,
998 void brw_oword_block_write_scratch(struct brw_compile
*p
,
1003 void brw_dword_scattered_read(struct brw_compile
*p
,
1004 struct brw_reg dest
,
1006 uint32_t bind_table_index
);
1008 void brw_dp_READ_4_vs( struct brw_compile
*p
,
1009 struct brw_reg dest
,
1011 GLuint bind_table_index
);
1013 void brw_dp_READ_4_vs_relative(struct brw_compile
*p
,
1014 struct brw_reg dest
,
1015 struct brw_reg addrReg
,
1017 GLuint bind_table_index
);
1019 /* If/else/endif. Works by manipulating the execution flags on each
1022 struct brw_instruction
*brw_IF(struct brw_compile
*p
,
1023 GLuint execute_size
);
1024 struct brw_instruction
*gen6_IF(struct brw_compile
*p
, uint32_t conditional
,
1025 struct brw_reg src0
, struct brw_reg src1
);
1027 void brw_ELSE(struct brw_compile
*p
);
1028 void brw_ENDIF(struct brw_compile
*p
);
1032 struct brw_instruction
*brw_DO(struct brw_compile
*p
,
1033 GLuint execute_size
);
1035 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
);
1037 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
);
1038 struct brw_instruction
*brw_CONT(struct brw_compile
*p
);
1039 struct brw_instruction
*gen6_CONT(struct brw_compile
*p
);
1042 void brw_land_fwd_jump(struct brw_compile
*p
, int jmp_insn_idx
);
1046 void brw_NOP(struct brw_compile
*p
);
1048 void brw_WAIT(struct brw_compile
*p
);
1050 /* Special case: there is never a destination, execution size will be
1053 void brw_CMP(struct brw_compile
*p
,
1054 struct brw_reg dest
,
1056 struct brw_reg src0
,
1057 struct brw_reg src1
);
1059 void brw_print_reg( struct brw_reg reg
);
1062 /***********************************************************************
1066 void brw_copy_indirect_to_indirect(struct brw_compile
*p
,
1067 struct brw_indirect dst_ptr
,
1068 struct brw_indirect src_ptr
,
1071 void brw_copy_from_indirect(struct brw_compile
*p
,
1073 struct brw_indirect ptr
,
1076 void brw_copy4(struct brw_compile
*p
,
1081 void brw_copy8(struct brw_compile
*p
,
1086 void brw_math_invert( struct brw_compile
*p
,
1088 struct brw_reg src
);
1090 void brw_set_src1(struct brw_compile
*p
,
1091 struct brw_instruction
*insn
,
1092 struct brw_reg reg
);
1094 void brw_set_uip_jip(struct brw_compile
*p
);
1096 uint32_t brw_swap_cmod(uint32_t cmod
);
1098 /* brw_optimize.c */
1099 void brw_optimize(struct brw_compile
*p
);
1100 void brw_remove_duplicate_mrf_moves(struct brw_compile
*p
);
1101 void brw_remove_grf_to_mrf_moves(struct brw_compile
*p
);