i965/vec4: Add support for nonconst sampler indexing in VS visitor
[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include "brw_inst.h"
38 #include "brw_structs.h"
39 #include "brw_defines.h"
40 #include "brw_reg.h"
41 #include "intel_asm_annotation.h"
42 #include "program/prog_instruction.h"
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 #define BRW_EU_MAX_INSN_STACK 5
49
50 /* A helper for accessing the last instruction emitted. This makes it easy
51 * to set various bits on an instruction without having to create temporary
52 * variable and assign the emitted instruction to those.
53 */
54 #define brw_last_inst (&p->store[p->nr_insn - 1])
55
56 struct brw_compile {
57 brw_inst *store;
58 int store_size;
59 unsigned nr_insn;
60 unsigned int next_insn_offset;
61
62 void *mem_ctx;
63
64 /* Allow clients to push/pop instruction state:
65 */
66 brw_inst stack[BRW_EU_MAX_INSN_STACK];
67 bool compressed_stack[BRW_EU_MAX_INSN_STACK];
68 brw_inst *current;
69
70 bool single_program_flow;
71 bool compressed;
72 struct brw_context *brw;
73
74 /* Control flow stacks:
75 * - if_stack contains IF and ELSE instructions which must be patched
76 * (and popped) once the matching ENDIF instruction is encountered.
77 *
78 * Just store the instruction pointer(an index).
79 */
80 int *if_stack;
81 int if_stack_depth;
82 int if_stack_array_size;
83
84 /**
85 * loop_stack contains the instruction pointers of the starts of loops which
86 * must be patched (and popped) once the matching WHILE instruction is
87 * encountered.
88 */
89 int *loop_stack;
90 /**
91 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
92 * blocks they were popping out of, to fix up the mask stack. This tracks
93 * the IF/ENDIF nesting in each current nested loop level.
94 */
95 int *if_depth_in_loop;
96 int loop_stack_depth;
97 int loop_stack_array_size;
98 };
99
100 void brw_pop_insn_state( struct brw_compile *p );
101 void brw_push_insn_state( struct brw_compile *p );
102 void brw_set_default_mask_control( struct brw_compile *p, unsigned value );
103 void brw_set_default_saturate( struct brw_compile *p, bool enable );
104 void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode );
105 void brw_set_default_compression_control(struct brw_compile *p, enum brw_compression c);
106 void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc );
107 void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
108 void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg);
109 void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value);
110
111 void brw_init_compile(struct brw_context *, struct brw_compile *p,
112 void *mem_ctx);
113 void brw_disassemble(struct brw_context *brw, void *assembly,
114 int start, int end, FILE *out);
115 const unsigned *brw_get_program( struct brw_compile *p, unsigned *sz );
116
117 brw_inst *brw_next_insn(struct brw_compile *p, unsigned opcode);
118 void brw_set_dest(struct brw_compile *p, brw_inst *insn, struct brw_reg dest);
119 void brw_set_src0(struct brw_compile *p, brw_inst *insn, struct brw_reg reg);
120
121 void gen6_resolve_implied_move(struct brw_compile *p,
122 struct brw_reg *src,
123 unsigned msg_reg_nr);
124
125 /* Helpers for regular instructions:
126 */
127 #define ALU1(OP) \
128 brw_inst *brw_##OP(struct brw_compile *p, \
129 struct brw_reg dest, \
130 struct brw_reg src0);
131
132 #define ALU2(OP) \
133 brw_inst *brw_##OP(struct brw_compile *p, \
134 struct brw_reg dest, \
135 struct brw_reg src0, \
136 struct brw_reg src1);
137
138 #define ALU3(OP) \
139 brw_inst *brw_##OP(struct brw_compile *p, \
140 struct brw_reg dest, \
141 struct brw_reg src0, \
142 struct brw_reg src1, \
143 struct brw_reg src2);
144
145 #define ROUND(OP) \
146 void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
147
148 ALU1(MOV)
149 ALU2(SEL)
150 ALU1(NOT)
151 ALU2(AND)
152 ALU2(OR)
153 ALU2(XOR)
154 ALU2(SHR)
155 ALU2(SHL)
156 ALU2(ASR)
157 ALU1(F32TO16)
158 ALU1(F16TO32)
159 ALU2(ADD)
160 ALU2(AVG)
161 ALU2(MUL)
162 ALU1(FRC)
163 ALU1(RNDD)
164 ALU2(MAC)
165 ALU2(MACH)
166 ALU1(LZD)
167 ALU2(DP4)
168 ALU2(DPH)
169 ALU2(DP3)
170 ALU2(DP2)
171 ALU2(LINE)
172 ALU2(PLN)
173 ALU3(MAD)
174 ALU3(LRP)
175 ALU1(BFREV)
176 ALU3(BFE)
177 ALU2(BFI1)
178 ALU3(BFI2)
179 ALU1(FBH)
180 ALU1(FBL)
181 ALU1(CBIT)
182 ALU2(ADDC)
183 ALU2(SUBB)
184 ALU2(MAC)
185
186 ROUND(RNDZ)
187 ROUND(RNDE)
188
189 #undef ALU1
190 #undef ALU2
191 #undef ALU3
192 #undef ROUND
193
194
195 /* Helpers for SEND instruction:
196 */
197 void brw_set_sampler_message(struct brw_compile *p,
198 brw_inst *insn,
199 unsigned binding_table_index,
200 unsigned sampler,
201 unsigned msg_type,
202 unsigned response_length,
203 unsigned msg_length,
204 unsigned header_present,
205 unsigned simd_mode,
206 unsigned return_format);
207
208 void brw_set_indirect_send_descriptor(struct brw_compile *p,
209 brw_inst *insn,
210 unsigned sfid,
211 struct brw_reg descriptor);
212
213 void brw_set_dp_read_message(struct brw_compile *p,
214 brw_inst *insn,
215 unsigned binding_table_index,
216 unsigned msg_control,
217 unsigned msg_type,
218 unsigned target_cache,
219 unsigned msg_length,
220 bool header_present,
221 unsigned response_length);
222
223 void brw_set_dp_write_message(struct brw_compile *p,
224 brw_inst *insn,
225 unsigned binding_table_index,
226 unsigned msg_control,
227 unsigned msg_type,
228 unsigned msg_length,
229 bool header_present,
230 unsigned last_render_target,
231 unsigned response_length,
232 unsigned end_of_thread,
233 unsigned send_commit_msg);
234
235 void brw_urb_WRITE(struct brw_compile *p,
236 struct brw_reg dest,
237 unsigned msg_reg_nr,
238 struct brw_reg src0,
239 enum brw_urb_write_flags flags,
240 unsigned msg_length,
241 unsigned response_length,
242 unsigned offset,
243 unsigned swizzle);
244
245 void brw_ff_sync(struct brw_compile *p,
246 struct brw_reg dest,
247 unsigned msg_reg_nr,
248 struct brw_reg src0,
249 bool allocate,
250 unsigned response_length,
251 bool eot);
252
253 void brw_svb_write(struct brw_compile *p,
254 struct brw_reg dest,
255 unsigned msg_reg_nr,
256 struct brw_reg src0,
257 unsigned binding_table_index,
258 bool send_commit_msg);
259
260 void brw_fb_WRITE(struct brw_compile *p,
261 int dispatch_width,
262 unsigned msg_reg_nr,
263 struct brw_reg src0,
264 unsigned msg_control,
265 unsigned binding_table_index,
266 unsigned msg_length,
267 unsigned response_length,
268 bool eot,
269 bool header_present);
270
271 void brw_SAMPLE(struct brw_compile *p,
272 struct brw_reg dest,
273 unsigned msg_reg_nr,
274 struct brw_reg src0,
275 unsigned binding_table_index,
276 unsigned sampler,
277 unsigned msg_type,
278 unsigned response_length,
279 unsigned msg_length,
280 unsigned header_present,
281 unsigned simd_mode,
282 unsigned return_format);
283
284 void brw_adjust_sampler_state_pointer(struct brw_compile *p,
285 struct brw_reg header,
286 struct brw_reg sampler_index,
287 struct brw_reg scratch);
288
289 void gen4_math(struct brw_compile *p,
290 struct brw_reg dest,
291 unsigned function,
292 unsigned msg_reg_nr,
293 struct brw_reg src,
294 unsigned data_type,
295 unsigned precision );
296
297 void gen6_math(struct brw_compile *p,
298 struct brw_reg dest,
299 unsigned function,
300 struct brw_reg src0,
301 struct brw_reg src1);
302
303 void brw_oword_block_read(struct brw_compile *p,
304 struct brw_reg dest,
305 struct brw_reg mrf,
306 uint32_t offset,
307 uint32_t bind_table_index);
308
309 void brw_oword_block_read_scratch(struct brw_compile *p,
310 struct brw_reg dest,
311 struct brw_reg mrf,
312 int num_regs,
313 unsigned offset);
314
315 void brw_oword_block_write_scratch(struct brw_compile *p,
316 struct brw_reg mrf,
317 int num_regs,
318 unsigned offset);
319
320 void gen7_block_read_scratch(struct brw_compile *p,
321 struct brw_reg dest,
322 int num_regs,
323 unsigned offset);
324
325 void brw_shader_time_add(struct brw_compile *p,
326 struct brw_reg payload,
327 uint32_t surf_index);
328
329 /**
330 * Return the generation-specific jump distance scaling factor.
331 *
332 * Given the number of instructions to jump, we need to scale by
333 * some number to obtain the actual jump distance to program in an
334 * instruction.
335 */
336 static inline unsigned
337 brw_jump_scale(const struct brw_context *brw)
338 {
339 /* Broadwell measures jump targets in bytes. */
340 if (brw->gen >= 8)
341 return 16;
342
343 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
344 * (to support compaction), so each 128-bit instruction requires 2 chunks.
345 */
346 if (brw->gen >= 5)
347 return 2;
348
349 /* Gen4 simply uses the number of 128-bit instructions. */
350 return 1;
351 }
352
353 /* If/else/endif. Works by manipulating the execution flags on each
354 * channel.
355 */
356 brw_inst *brw_IF(struct brw_compile *p, unsigned execute_size);
357 brw_inst *gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
358 struct brw_reg src0, struct brw_reg src1);
359
360 void brw_ELSE(struct brw_compile *p);
361 void brw_ENDIF(struct brw_compile *p);
362
363 /* DO/WHILE loops:
364 */
365 brw_inst *brw_DO(struct brw_compile *p, unsigned execute_size);
366
367 brw_inst *brw_WHILE(struct brw_compile *p);
368
369 brw_inst *brw_BREAK(struct brw_compile *p);
370 brw_inst *brw_CONT(struct brw_compile *p);
371 brw_inst *gen6_HALT(struct brw_compile *p);
372
373 /* Forward jumps:
374 */
375 void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx);
376
377 brw_inst *brw_JMPI(struct brw_compile *p, struct brw_reg index,
378 unsigned predicate_control);
379
380 void brw_NOP(struct brw_compile *p);
381
382 /* Special case: there is never a destination, execution size will be
383 * taken from src0:
384 */
385 void brw_CMP(struct brw_compile *p,
386 struct brw_reg dest,
387 unsigned conditional,
388 struct brw_reg src0,
389 struct brw_reg src1);
390
391 void
392 brw_untyped_atomic(struct brw_compile *p,
393 struct brw_reg dest,
394 struct brw_reg mrf,
395 unsigned atomic_op,
396 unsigned bind_table_index,
397 unsigned msg_length,
398 unsigned response_length);
399
400 void
401 brw_untyped_surface_read(struct brw_compile *p,
402 struct brw_reg dest,
403 struct brw_reg mrf,
404 unsigned bind_table_index,
405 unsigned msg_length,
406 unsigned response_length);
407
408 void
409 brw_pixel_interpolator_query(struct brw_compile *p,
410 struct brw_reg dest,
411 struct brw_reg mrf,
412 bool noperspective,
413 unsigned mode,
414 unsigned data,
415 unsigned msg_length,
416 unsigned response_length);
417
418 /***********************************************************************
419 * brw_eu_util.c:
420 */
421
422 void brw_copy_indirect_to_indirect(struct brw_compile *p,
423 struct brw_indirect dst_ptr,
424 struct brw_indirect src_ptr,
425 unsigned count);
426
427 void brw_copy_from_indirect(struct brw_compile *p,
428 struct brw_reg dst,
429 struct brw_indirect ptr,
430 unsigned count);
431
432 void brw_copy4(struct brw_compile *p,
433 struct brw_reg dst,
434 struct brw_reg src,
435 unsigned count);
436
437 void brw_copy8(struct brw_compile *p,
438 struct brw_reg dst,
439 struct brw_reg src,
440 unsigned count);
441
442 void brw_math_invert( struct brw_compile *p,
443 struct brw_reg dst,
444 struct brw_reg src);
445
446 void brw_set_src1(struct brw_compile *p, brw_inst *insn, struct brw_reg reg);
447
448 void brw_set_uip_jip(struct brw_compile *p);
449
450 enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
451
452 /* brw_eu_compact.c */
453 void brw_init_compaction_tables(struct brw_context *brw);
454 void brw_compact_instructions(struct brw_compile *p, int start_offset,
455 int num_annotations, struct annotation *annotation);
456 void brw_uncompact_instruction(struct brw_context *brw, brw_inst *dst,
457 brw_compact_inst *src);
458 bool brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
459 brw_inst *src);
460
461 void brw_debug_compact_uncompact(struct brw_context *brw, brw_inst *orig,
462 brw_inst *uncompacted);
463
464 static inline int
465 next_offset(const struct brw_context *brw, void *store, int offset)
466 {
467 brw_inst *insn = (brw_inst *)((char *)store + offset);
468
469 if (brw_inst_cmpt_control(brw, insn))
470 return offset + 8;
471 else
472 return offset + 16;
473 }
474
475 #ifdef __cplusplus
476 }
477 #endif
478
479 #endif