i965/skl: Don't use ALL_SLICES_AT_EACH_LOD
[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include "brw_inst.h"
38 #include "brw_structs.h"
39 #include "brw_defines.h"
40 #include "brw_reg.h"
41 #include "intel_asm_annotation.h"
42 #include "program/prog_instruction.h"
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 #define BRW_EU_MAX_INSN_STACK 5
49
50 /* A helper for accessing the last instruction emitted. This makes it easy
51 * to set various bits on an instruction without having to create temporary
52 * variable and assign the emitted instruction to those.
53 */
54 #define brw_last_inst (&p->store[p->nr_insn - 1])
55
56 struct brw_compile {
57 brw_inst *store;
58 int store_size;
59 unsigned nr_insn;
60 unsigned int next_insn_offset;
61
62 void *mem_ctx;
63
64 /* Allow clients to push/pop instruction state:
65 */
66 brw_inst stack[BRW_EU_MAX_INSN_STACK];
67 bool compressed_stack[BRW_EU_MAX_INSN_STACK];
68 brw_inst *current;
69
70 bool single_program_flow;
71 bool compressed;
72 struct brw_context *brw;
73
74 /* Control flow stacks:
75 * - if_stack contains IF and ELSE instructions which must be patched
76 * (and popped) once the matching ENDIF instruction is encountered.
77 *
78 * Just store the instruction pointer(an index).
79 */
80 int *if_stack;
81 int if_stack_depth;
82 int if_stack_array_size;
83
84 /**
85 * loop_stack contains the instruction pointers of the starts of loops which
86 * must be patched (and popped) once the matching WHILE instruction is
87 * encountered.
88 */
89 int *loop_stack;
90 /**
91 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
92 * blocks they were popping out of, to fix up the mask stack. This tracks
93 * the IF/ENDIF nesting in each current nested loop level.
94 */
95 int *if_depth_in_loop;
96 int loop_stack_depth;
97 int loop_stack_array_size;
98 };
99
100 void brw_pop_insn_state( struct brw_compile *p );
101 void brw_push_insn_state( struct brw_compile *p );
102 void brw_set_default_mask_control( struct brw_compile *p, unsigned value );
103 void brw_set_default_saturate( struct brw_compile *p, bool enable );
104 void brw_set_default_access_mode( struct brw_compile *p, unsigned access_mode );
105 void brw_set_default_compression_control(struct brw_compile *p, enum brw_compression c);
106 void brw_set_default_predicate_control( struct brw_compile *p, unsigned pc );
107 void brw_set_default_predicate_inverse(struct brw_compile *p, bool predicate_inverse);
108 void brw_set_default_flag_reg(struct brw_compile *p, int reg, int subreg);
109 void brw_set_default_acc_write_control(struct brw_compile *p, unsigned value);
110
111 void brw_init_compile(struct brw_context *, struct brw_compile *p,
112 void *mem_ctx);
113 void brw_disassemble(struct brw_context *brw, void *assembly,
114 int start, int end, FILE *out);
115 const unsigned *brw_get_program( struct brw_compile *p, unsigned *sz );
116
117 brw_inst *brw_next_insn(struct brw_compile *p, unsigned opcode);
118 void brw_set_dest(struct brw_compile *p, brw_inst *insn, struct brw_reg dest);
119 void brw_set_src0(struct brw_compile *p, brw_inst *insn, struct brw_reg reg);
120
121 void gen6_resolve_implied_move(struct brw_compile *p,
122 struct brw_reg *src,
123 unsigned msg_reg_nr);
124
125 /* Helpers for regular instructions:
126 */
127 #define ALU1(OP) \
128 brw_inst *brw_##OP(struct brw_compile *p, \
129 struct brw_reg dest, \
130 struct brw_reg src0);
131
132 #define ALU2(OP) \
133 brw_inst *brw_##OP(struct brw_compile *p, \
134 struct brw_reg dest, \
135 struct brw_reg src0, \
136 struct brw_reg src1);
137
138 #define ALU3(OP) \
139 brw_inst *brw_##OP(struct brw_compile *p, \
140 struct brw_reg dest, \
141 struct brw_reg src0, \
142 struct brw_reg src1, \
143 struct brw_reg src2);
144
145 #define ROUND(OP) \
146 void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
147
148 ALU1(MOV)
149 ALU2(SEL)
150 ALU1(NOT)
151 ALU2(AND)
152 ALU2(OR)
153 ALU2(XOR)
154 ALU2(SHR)
155 ALU2(SHL)
156 ALU2(ASR)
157 ALU1(F32TO16)
158 ALU1(F16TO32)
159 ALU2(ADD)
160 ALU2(AVG)
161 ALU2(MUL)
162 ALU1(FRC)
163 ALU1(RNDD)
164 ALU2(MAC)
165 ALU2(MACH)
166 ALU1(LZD)
167 ALU2(DP4)
168 ALU2(DPH)
169 ALU2(DP3)
170 ALU2(DP2)
171 ALU2(LINE)
172 ALU2(PLN)
173 ALU3(MAD)
174 ALU3(LRP)
175 ALU1(BFREV)
176 ALU3(BFE)
177 ALU2(BFI1)
178 ALU3(BFI2)
179 ALU1(FBH)
180 ALU1(FBL)
181 ALU1(CBIT)
182 ALU2(ADDC)
183 ALU2(SUBB)
184 ALU2(MAC)
185
186 ROUND(RNDZ)
187 ROUND(RNDE)
188
189 #undef ALU1
190 #undef ALU2
191 #undef ALU3
192 #undef ROUND
193
194
195 /* Helpers for SEND instruction:
196 */
197 void brw_set_sampler_message(struct brw_compile *p,
198 brw_inst *insn,
199 unsigned binding_table_index,
200 unsigned sampler,
201 unsigned msg_type,
202 unsigned response_length,
203 unsigned msg_length,
204 unsigned header_present,
205 unsigned simd_mode,
206 unsigned return_format);
207
208 void brw_set_dp_read_message(struct brw_compile *p,
209 brw_inst *insn,
210 unsigned binding_table_index,
211 unsigned msg_control,
212 unsigned msg_type,
213 unsigned target_cache,
214 unsigned msg_length,
215 bool header_present,
216 unsigned response_length);
217
218 void brw_set_dp_write_message(struct brw_compile *p,
219 brw_inst *insn,
220 unsigned binding_table_index,
221 unsigned msg_control,
222 unsigned msg_type,
223 unsigned msg_length,
224 bool header_present,
225 unsigned last_render_target,
226 unsigned response_length,
227 unsigned end_of_thread,
228 unsigned send_commit_msg);
229
230 void brw_urb_WRITE(struct brw_compile *p,
231 struct brw_reg dest,
232 unsigned msg_reg_nr,
233 struct brw_reg src0,
234 enum brw_urb_write_flags flags,
235 unsigned msg_length,
236 unsigned response_length,
237 unsigned offset,
238 unsigned swizzle);
239
240 /**
241 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
242 * desc. If \p desc is not an immediate it will be transparently loaded to an
243 * address register using an OR instruction. The returned instruction can be
244 * passed as argument to the usual brw_set_*_message() functions in order to
245 * specify any additional descriptor bits -- If \p desc is an immediate this
246 * will be the SEND instruction itself, otherwise it will be the OR
247 * instruction.
248 */
249 struct brw_inst *
250 brw_send_indirect_message(struct brw_compile *p,
251 unsigned sfid,
252 struct brw_reg dst,
253 struct brw_reg payload,
254 struct brw_reg desc);
255
256 void brw_ff_sync(struct brw_compile *p,
257 struct brw_reg dest,
258 unsigned msg_reg_nr,
259 struct brw_reg src0,
260 bool allocate,
261 unsigned response_length,
262 bool eot);
263
264 void brw_svb_write(struct brw_compile *p,
265 struct brw_reg dest,
266 unsigned msg_reg_nr,
267 struct brw_reg src0,
268 unsigned binding_table_index,
269 bool send_commit_msg);
270
271 void brw_fb_WRITE(struct brw_compile *p,
272 int dispatch_width,
273 struct brw_reg payload,
274 struct brw_reg implied_header,
275 unsigned msg_control,
276 unsigned binding_table_index,
277 unsigned msg_length,
278 unsigned response_length,
279 bool eot,
280 bool last_render_target,
281 bool header_present);
282
283 void brw_SAMPLE(struct brw_compile *p,
284 struct brw_reg dest,
285 unsigned msg_reg_nr,
286 struct brw_reg src0,
287 unsigned binding_table_index,
288 unsigned sampler,
289 unsigned msg_type,
290 unsigned response_length,
291 unsigned msg_length,
292 unsigned header_present,
293 unsigned simd_mode,
294 unsigned return_format);
295
296 void brw_adjust_sampler_state_pointer(struct brw_compile *p,
297 struct brw_reg header,
298 struct brw_reg sampler_index);
299
300 void gen4_math(struct brw_compile *p,
301 struct brw_reg dest,
302 unsigned function,
303 unsigned msg_reg_nr,
304 struct brw_reg src,
305 unsigned precision );
306
307 void gen6_math(struct brw_compile *p,
308 struct brw_reg dest,
309 unsigned function,
310 struct brw_reg src0,
311 struct brw_reg src1);
312
313 void brw_oword_block_read(struct brw_compile *p,
314 struct brw_reg dest,
315 struct brw_reg mrf,
316 uint32_t offset,
317 uint32_t bind_table_index);
318
319 void brw_oword_block_read_scratch(struct brw_compile *p,
320 struct brw_reg dest,
321 struct brw_reg mrf,
322 int num_regs,
323 unsigned offset);
324
325 void brw_oword_block_write_scratch(struct brw_compile *p,
326 struct brw_reg mrf,
327 int num_regs,
328 unsigned offset);
329
330 void gen7_block_read_scratch(struct brw_compile *p,
331 struct brw_reg dest,
332 int num_regs,
333 unsigned offset);
334
335 void brw_shader_time_add(struct brw_compile *p,
336 struct brw_reg payload,
337 uint32_t surf_index);
338
339 /**
340 * Return the generation-specific jump distance scaling factor.
341 *
342 * Given the number of instructions to jump, we need to scale by
343 * some number to obtain the actual jump distance to program in an
344 * instruction.
345 */
346 static inline unsigned
347 brw_jump_scale(const struct brw_context *brw)
348 {
349 /* Broadwell measures jump targets in bytes. */
350 if (brw->gen >= 8)
351 return 16;
352
353 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
354 * (to support compaction), so each 128-bit instruction requires 2 chunks.
355 */
356 if (brw->gen >= 5)
357 return 2;
358
359 /* Gen4 simply uses the number of 128-bit instructions. */
360 return 1;
361 }
362
363 /* If/else/endif. Works by manipulating the execution flags on each
364 * channel.
365 */
366 brw_inst *brw_IF(struct brw_compile *p, unsigned execute_size);
367 brw_inst *gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
368 struct brw_reg src0, struct brw_reg src1);
369
370 void brw_ELSE(struct brw_compile *p);
371 void brw_ENDIF(struct brw_compile *p);
372
373 /* DO/WHILE loops:
374 */
375 brw_inst *brw_DO(struct brw_compile *p, unsigned execute_size);
376
377 brw_inst *brw_WHILE(struct brw_compile *p);
378
379 brw_inst *brw_BREAK(struct brw_compile *p);
380 brw_inst *brw_CONT(struct brw_compile *p);
381 brw_inst *gen6_HALT(struct brw_compile *p);
382
383 /* Forward jumps:
384 */
385 void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx);
386
387 brw_inst *brw_JMPI(struct brw_compile *p, struct brw_reg index,
388 unsigned predicate_control);
389
390 void brw_NOP(struct brw_compile *p);
391
392 /* Special case: there is never a destination, execution size will be
393 * taken from src0:
394 */
395 void brw_CMP(struct brw_compile *p,
396 struct brw_reg dest,
397 unsigned conditional,
398 struct brw_reg src0,
399 struct brw_reg src1);
400
401 void
402 brw_untyped_atomic(struct brw_compile *p,
403 struct brw_reg dest,
404 struct brw_reg payload,
405 unsigned atomic_op,
406 unsigned bind_table_index,
407 unsigned msg_length,
408 bool response_expected);
409
410 void
411 brw_untyped_surface_read(struct brw_compile *p,
412 struct brw_reg dest,
413 struct brw_reg mrf,
414 unsigned bind_table_index,
415 unsigned msg_length,
416 unsigned num_channels);
417
418 void
419 brw_pixel_interpolator_query(struct brw_compile *p,
420 struct brw_reg dest,
421 struct brw_reg mrf,
422 bool noperspective,
423 unsigned mode,
424 unsigned data,
425 unsigned msg_length,
426 unsigned response_length);
427
428 /***********************************************************************
429 * brw_eu_util.c:
430 */
431
432 void brw_copy_indirect_to_indirect(struct brw_compile *p,
433 struct brw_indirect dst_ptr,
434 struct brw_indirect src_ptr,
435 unsigned count);
436
437 void brw_copy_from_indirect(struct brw_compile *p,
438 struct brw_reg dst,
439 struct brw_indirect ptr,
440 unsigned count);
441
442 void brw_copy4(struct brw_compile *p,
443 struct brw_reg dst,
444 struct brw_reg src,
445 unsigned count);
446
447 void brw_copy8(struct brw_compile *p,
448 struct brw_reg dst,
449 struct brw_reg src,
450 unsigned count);
451
452 void brw_math_invert( struct brw_compile *p,
453 struct brw_reg dst,
454 struct brw_reg src);
455
456 void brw_set_src1(struct brw_compile *p, brw_inst *insn, struct brw_reg reg);
457
458 void brw_set_uip_jip(struct brw_compile *p);
459
460 enum brw_conditional_mod brw_negate_cmod(uint32_t cmod);
461 enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
462
463 /* brw_eu_compact.c */
464 void brw_init_compaction_tables(struct brw_context *brw);
465 void brw_compact_instructions(struct brw_compile *p, int start_offset,
466 int num_annotations, struct annotation *annotation);
467 void brw_uncompact_instruction(struct brw_context *brw, brw_inst *dst,
468 brw_compact_inst *src);
469 bool brw_try_compact_instruction(struct brw_context *brw, brw_compact_inst *dst,
470 brw_inst *src);
471
472 void brw_debug_compact_uncompact(struct brw_context *brw, brw_inst *orig,
473 brw_inst *uncompacted);
474
475 static inline int
476 next_offset(const struct brw_context *brw, void *store, int offset)
477 {
478 brw_inst *insn = (brw_inst *)((char *)store + offset);
479
480 if (brw_inst_cmpt_control(brw, insn))
481 return offset + 8;
482 else
483 return offset + 16;
484 }
485
486 #ifdef __cplusplus
487 }
488 #endif
489
490 #endif