src/mesa/drivers/dri/i965/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include "brw_structs.h"
  37 #include "brw_defines.h"
  38 #include "shader/prog_instruction.h"
  39
  40 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
  41 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
  42
  43 #define BRW_SWIZZLE_NOOP      BRW_SWIZZLE4(0,1,2,3)
  44 #define BRW_SWIZZLE_XYZW      BRW_SWIZZLE4(0,1,2,3)
  45 #define BRW_SWIZZLE_XXXX      BRW_SWIZZLE4(0,0,0,0)
  46 #define BRW_SWIZZLE_XYXY      BRW_SWIZZLE4(0,1,0,1)
  47
  48
  49 #define REG_SIZE (8*4)
  50
  51
  52 /* These aren't hardware structs, just something useful for us to pass around:
  53  *
  54  * Align1 operation has a lot of control over input ranges.  Used in
  55  * WM programs to implement shaders decomposed into "channel serial"
  56  * or "structure of array" form:
  57  */
  58 struct brw_reg
  59 {
  60    GLuint type:4;
  61    GLuint file:2;
  62    GLuint nr:8;
  63    GLuint subnr:5;              /* :1 in align16 */
  64    GLuint negate:1;             /* source only */
  65    GLuint abs:1;                /* source only */
  66    GLuint vstride:4;            /* source only */
  67    GLuint width:3;              /* src only, align1 only */
  68    GLuint hstride:2;            /* align1 only */
  69    GLuint address_mode:1;       /* relative addressing, hopefully! */
  70    GLuint pad0:1;
  71
  72    union {
  73       struct {
  74          GLuint swizzle:8;              /* src only, align16 only */
  75          GLuint writemask:4;            /* dest only, align16 only */
  76          GLint  indirect_offset:10;     /* relative addressing offset */
  77          GLuint pad1:10;                /* two dwords total */
  78       } bits;
  79
  80       GLfloat f;
  81       GLint   d;
  82       GLuint ud;
  83    } dw1;
  84 };
  85
  86
  87 struct brw_indirect {
  88    GLuint addr_subnr:4;
  89    GLint addr_offset:10;
  90    GLuint pad:18;
  91 };
  92
  93
  94 #define BRW_EU_MAX_INSN_STACK 5
  95 #define BRW_EU_MAX_INSN 1200
  96
  97 struct brw_compile {
  98    struct brw_instruction store[BRW_EU_MAX_INSN];
  99    GLuint nr_insn;
 100
 101    /* Allow clients to push/pop instruction state:
 102     */
 103    struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
 104    struct brw_instruction *current;
 105
 106    GLuint flag_value;
 107    GLboolean single_program_flow;
 108    struct brw_context *brw;
 109 };
 110
 111
 112
 113 static INLINE int type_sz( GLuint type )
 114 {
 115    switch( type ) {
 116    case BRW_REGISTER_TYPE_UD:
 117    case BRW_REGISTER_TYPE_D:
 118    case BRW_REGISTER_TYPE_F:
 119       return 4;
 120    case BRW_REGISTER_TYPE_HF:
 121    case BRW_REGISTER_TYPE_UW:
 122    case BRW_REGISTER_TYPE_W:
 123       return 2;
 124    case BRW_REGISTER_TYPE_UB:
 125    case BRW_REGISTER_TYPE_B:
 126       return 1;
 127    default:
 128       return 0;
 129    }
 130 }
 131
 132 static INLINE struct brw_reg brw_reg( GLuint file,
 133                                         GLuint nr,
 134                                         GLuint subnr,
 135                                         GLuint type,
 136                                         GLuint vstride,
 137                                         GLuint width,
 138                                         GLuint hstride,
 139                                         GLuint swizzle,
 140                                         GLuint writemask)
 141 {
 142
 143    struct brw_reg reg;
 144    reg.type = type;
 145    reg.file = file;
 146    reg.nr = nr;
 147    reg.subnr = subnr * type_sz(type);
 148    reg.negate = 0;
 149    reg.abs = 0;
 150    reg.vstride = vstride;
 151    reg.width = width;
 152    reg.hstride = hstride;
 153    reg.address_mode = BRW_ADDRESS_DIRECT;
 154    reg.pad0 = 0;
 155
 156    /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
 157     * set swizzle and writemask to W, as the lower bits of subnr will
 158     * be lost when converted to align16.  This is probably too much to
 159     * keep track of as you'd want it adjusted by suboffset(), etc.
 160     * Perhaps fix up when converting to align16?
 161     */
 162    reg.dw1.bits.swizzle = swizzle;
 163    reg.dw1.bits.writemask = writemask;
 164    reg.dw1.bits.indirect_offset = 0;
 165    reg.dw1.bits.pad1 = 0;
 166    return reg;
 167 }
 168
 169 static INLINE struct brw_reg brw_vec16_reg( GLuint file,
 170                                               GLuint nr,
 171                                               GLuint subnr )
 172 {
 173    return brw_reg(file,
 174                   nr,
 175                   subnr,
 176                   BRW_REGISTER_TYPE_F,
 177                   BRW_VERTICAL_STRIDE_16,
 178                   BRW_WIDTH_16,
 179                   BRW_HORIZONTAL_STRIDE_1,
 180                   BRW_SWIZZLE_XYZW,
 181                   WRITEMASK_XYZW);
 182 }
 183
 184 static INLINE struct brw_reg brw_vec8_reg( GLuint file,
 185                                              GLuint nr,
 186                                              GLuint subnr )
 187 {
 188    return brw_reg(file,
 189                   nr,
 190                   subnr,
 191                   BRW_REGISTER_TYPE_F,
 192                   BRW_VERTICAL_STRIDE_8,
 193                   BRW_WIDTH_8,
 194                   BRW_HORIZONTAL_STRIDE_1,
 195                   BRW_SWIZZLE_XYZW,
 196                   WRITEMASK_XYZW);
 197 }
 198
 199
 200 static INLINE struct brw_reg brw_vec4_reg( GLuint file,
 201                                               GLuint nr,
 202                                               GLuint subnr )
 203 {
 204    return brw_reg(file,
 205                   nr,
 206                   subnr,
 207                   BRW_REGISTER_TYPE_F,
 208                   BRW_VERTICAL_STRIDE_4,
 209                   BRW_WIDTH_4,
 210                   BRW_HORIZONTAL_STRIDE_1,
 211                   BRW_SWIZZLE_XYZW,
 212                   WRITEMASK_XYZW);
 213 }
 214
 215
 216 static INLINE struct brw_reg brw_vec2_reg( GLuint file,
 217                                               GLuint nr,
 218                                               GLuint subnr )
 219 {
 220    return brw_reg(file,
 221                   nr,
 222                   subnr,
 223                   BRW_REGISTER_TYPE_F,
 224                   BRW_VERTICAL_STRIDE_2,
 225                   BRW_WIDTH_2,
 226                   BRW_HORIZONTAL_STRIDE_1,
 227                   BRW_SWIZZLE_XYXY,
 228                   WRITEMASK_XY);
 229 }
 230
 231 static INLINE struct brw_reg brw_vec1_reg( GLuint file,
 232                                              GLuint nr,
 233                                              GLuint subnr )
 234 {
 235    return brw_reg(file,
 236                   nr,
 237                   subnr,
 238                   BRW_REGISTER_TYPE_F,
 239                   BRW_VERTICAL_STRIDE_0,
 240                   BRW_WIDTH_1,
 241                   BRW_HORIZONTAL_STRIDE_0,
 242                   BRW_SWIZZLE_XXXX,
 243                   WRITEMASK_X);
 244 }
 245
 246
 247 static INLINE struct brw_reg retype( struct brw_reg reg,
 248                                        GLuint type )
 249 {
 250    reg.type = type;
 251    return reg;
 252 }
 253
 254 static INLINE struct brw_reg suboffset( struct brw_reg reg,
 255                                           GLuint delta )
 256 {
 257    reg.subnr += delta * type_sz(reg.type);
 258    return reg;
 259 }
 260
 261
 262 static INLINE struct brw_reg offset( struct brw_reg reg,
 263                                        GLuint delta )
 264 {
 265    reg.nr += delta;
 266    return reg;
 267 }
 268
 269
 270 static INLINE struct brw_reg byte_offset( struct brw_reg reg,
 271                                             GLuint bytes )
 272 {
 273    GLuint newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
 274    reg.nr = newoffset / REG_SIZE;
 275    reg.subnr = newoffset % REG_SIZE;
 276    return reg;
 277 }
 278
 279
 280 static INLINE struct brw_reg brw_uw16_reg( GLuint file,
 281                                              GLuint nr,
 282                                              GLuint subnr )
 283 {
 284    return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 285 }
 286
 287 static INLINE struct brw_reg brw_uw8_reg( GLuint file,
 288                                             GLuint nr,
 289                                             GLuint subnr )
 290 {
 291    return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 292 }
 293
 294 static INLINE struct brw_reg brw_uw1_reg( GLuint file,
 295                                             GLuint nr,
 296                                             GLuint subnr )
 297 {
 298    return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
 299 }
 300
 301 static INLINE struct brw_reg brw_imm_reg( GLuint type )
 302 {
 303    return brw_reg( BRW_IMMEDIATE_VALUE,
 304                    0,
 305                    0,
 306                    type,
 307                    BRW_VERTICAL_STRIDE_0,
 308                    BRW_WIDTH_1,
 309                    BRW_HORIZONTAL_STRIDE_0,
 310                    0,
 311                    0);
 312 }
 313
 314 static INLINE struct brw_reg brw_imm_f( GLfloat f )
 315 {
 316    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
 317    imm.dw1.f = f;
 318    return imm;
 319 }
 320
 321 static INLINE struct brw_reg brw_imm_d( GLint d )
 322 {
 323    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
 324    imm.dw1.d = d;
 325    return imm;
 326 }
 327
 328 static INLINE struct brw_reg brw_imm_ud( GLuint ud )
 329 {
 330    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
 331    imm.dw1.ud = ud;
 332    return imm;
 333 }
 334
 335 static INLINE struct brw_reg brw_imm_uw( GLushort uw )
 336 {
 337    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
 338    imm.dw1.ud = uw | (uw << 16);
 339    return imm;
 340 }
 341
 342 static INLINE struct brw_reg brw_imm_w( GLshort w )
 343 {
 344    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
 345    imm.dw1.d = w | (w << 16);
 346    return imm;
 347 }
 348
 349 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
 350  * numbers alias with _V and _VF below:
 351  */
 352
 353 /* Vector of eight signed half-byte values:
 354  */
 355 static INLINE struct brw_reg brw_imm_v( GLuint v )
 356 {
 357    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
 358    imm.vstride = BRW_VERTICAL_STRIDE_0;
 359    imm.width = BRW_WIDTH_8;
 360    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 361    imm.dw1.ud = v;
 362    return imm;
 363 }
 364
 365 /* Vector of four 8-bit float values:
 366  */
 367 static INLINE struct brw_reg brw_imm_vf( GLuint v )
 368 {
 369    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 370    imm.vstride = BRW_VERTICAL_STRIDE_0;
 371    imm.width = BRW_WIDTH_4;
 372    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 373    imm.dw1.ud = v;
 374    return imm;
 375 }
 376
 377 #define VF_ZERO 0x0
 378 #define VF_ONE  0x30
 379 #define VF_NEG  (1<<7)
 380
 381 static INLINE struct brw_reg brw_imm_vf4( GLuint v0,
 382                                             GLuint v1,
 383                                             GLuint v2,
 384                                             GLuint v3)
 385 {
 386    struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
 387    imm.vstride = BRW_VERTICAL_STRIDE_0;
 388    imm.width = BRW_WIDTH_4;
 389    imm.hstride = BRW_HORIZONTAL_STRIDE_1;
 390    imm.dw1.ud = ((v0 << 0) |
 391                  (v1 << 8) |
 392                  (v2 << 16) |
 393                  (v3 << 24));
 394    return imm;
 395 }
 396
 397
 398 static INLINE struct brw_reg brw_address( struct brw_reg reg )
 399 {
 400    return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
 401 }
 402
 403
 404 static INLINE struct brw_reg brw_vec1_grf( GLuint nr,
 405                                                GLuint subnr )
 406 {
 407    return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 408 }
 409
 410 static INLINE struct brw_reg brw_vec8_grf( GLuint nr,
 411                                              GLuint subnr )
 412 {
 413    return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 414 }
 415
 416 static INLINE struct brw_reg brw_vec4_grf( GLuint nr,
 417                                              GLuint subnr )
 418 {
 419    return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 420 }
 421
 422
 423 static INLINE struct brw_reg brw_vec2_grf( GLuint nr,
 424                                              GLuint subnr )
 425 {
 426    return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 427 }
 428
 429 static INLINE struct brw_reg brw_uw8_grf( GLuint nr,
 430                                             GLuint subnr )
 431 {
 432    return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 433 }
 434
 435 static INLINE struct brw_reg brw_uw16_grf( GLuint nr,
 436                                             GLuint subnr )
 437 {
 438    return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
 439 }
 440
 441 static INLINE struct brw_reg brw_null_reg( void )
 442 {
 443    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 444                        BRW_ARF_NULL,
 445                        0);
 446 }
 447
 448 static INLINE struct brw_reg brw_address_reg( GLuint subnr )
 449 {
 450    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 451                       BRW_ARF_ADDRESS,
 452                       subnr);
 453 }
 454
 455 /* If/else instructions break in align16 mode if writemask & swizzle
 456  * aren't xyzw.  This goes against the convention for other scalar
 457  * regs:
 458  */
 459 static INLINE struct brw_reg brw_ip_reg( void )
 460 {
 461    return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 462                   BRW_ARF_IP,
 463                   0,
 464                   BRW_REGISTER_TYPE_UD,
 465                   BRW_VERTICAL_STRIDE_4, /* ? */
 466                   BRW_WIDTH_1,
 467                   BRW_HORIZONTAL_STRIDE_0,
 468                   BRW_SWIZZLE_XYZW, /* NOTE! */
 469                   WRITEMASK_XYZW); /* NOTE! */
 470 }
 471
 472 static INLINE struct brw_reg brw_acc_reg( void )
 473 {
 474    return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 475                        BRW_ARF_ACCUMULATOR,
 476                        0);
 477 }
 478
 479
 480 static INLINE struct brw_reg brw_flag_reg( void )
 481 {
 482    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 483                       BRW_ARF_FLAG,
 484                       0);
 485 }
 486
 487
 488 static INLINE struct brw_reg brw_mask_reg( GLuint subnr )
 489 {
 490    return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
 491                       BRW_ARF_MASK,
 492                       subnr);
 493 }
 494
 495 static INLINE struct brw_reg brw_message_reg( GLuint nr )
 496 {
 497    return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE,
 498                        nr,
 499                        0);
 500 }
 501
 502
 503
 504
 505 /* This is almost always called with a numeric constant argument, so
 506  * make things easy to evaluate at compile time:
 507  */
 508 static INLINE GLuint cvt( GLuint val )
 509 {
 510    switch (val) {
 511    case 0: return 0;
 512    case 1: return 1;
 513    case 2: return 2;
 514    case 4: return 3;
 515    case 8: return 4;
 516    case 16: return 5;
 517    case 32: return 6;
 518    }
 519    return 0;
 520 }
 521
 522 static INLINE struct brw_reg stride( struct brw_reg reg,
 523                                        GLuint vstride,
 524                                        GLuint width,
 525                                        GLuint hstride )
 526 {
 527
 528    reg.vstride = cvt(vstride);
 529    reg.width = cvt(width) - 1;
 530    reg.hstride = cvt(hstride);
 531    return reg;
 532 }
 533
 534 static INLINE struct brw_reg vec16( struct brw_reg reg )
 535 {
 536    return stride(reg, 16,16,1);
 537 }
 538
 539 static INLINE struct brw_reg vec8( struct brw_reg reg )
 540 {
 541    return stride(reg, 8,8,1);
 542 }
 543
 544 static INLINE struct brw_reg vec4( struct brw_reg reg )
 545 {
 546    return stride(reg, 4,4,1);
 547 }
 548
 549 static INLINE struct brw_reg vec2( struct brw_reg reg )
 550 {
 551    return stride(reg, 2,2,1);
 552 }
 553
 554 static INLINE struct brw_reg vec1( struct brw_reg reg )
 555 {
 556    return stride(reg, 0,1,0);
 557 }
 558
 559 static INLINE struct brw_reg get_element( struct brw_reg reg, GLuint elt )
 560 {
 561    return vec1(suboffset(reg, elt));
 562 }
 563
 564 static INLINE struct brw_reg get_element_ud( struct brw_reg reg, GLuint elt )
 565 {
 566    return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
 567 }
 568
 569
 570 static INLINE struct brw_reg brw_swizzle( struct brw_reg reg,
 571                                             GLuint x,
 572                                             GLuint y,
 573                                             GLuint z,
 574                                             GLuint w)
 575 {
 576    reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
 577                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
 578                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
 579                                        BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
 580    return reg;
 581 }
 582
 583
 584 static INLINE struct brw_reg brw_swizzle1( struct brw_reg reg,
 585                                              GLuint x )
 586 {
 587    return brw_swizzle(reg, x, x, x, x);
 588 }
 589
 590 static INLINE struct brw_reg brw_writemask( struct brw_reg reg,
 591                                               GLuint mask )
 592 {
 593    reg.dw1.bits.writemask &= mask;
 594    return reg;
 595 }
 596
 597 static INLINE struct brw_reg brw_set_writemask( struct brw_reg reg,
 598                                                   GLuint mask )
 599 {
 600    reg.dw1.bits.writemask = mask;
 601    return reg;
 602 }
 603
 604 static INLINE struct brw_reg negate( struct brw_reg reg )
 605 {
 606    reg.negate ^= 1;
 607    return reg;
 608 }
 609
 610 static INLINE struct brw_reg brw_abs( struct brw_reg reg )
 611 {
 612    reg.abs = 1;
 613    return reg;
 614 }
 615
 616 /***********************************************************************
 617  */
 618 static INLINE struct brw_reg brw_vec4_indirect( GLuint subnr,
 619                                                   GLint offset )
 620 {
 621    struct brw_reg reg =  brw_vec4_grf(0, 0);
 622    reg.subnr = subnr;
 623    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 624    reg.dw1.bits.indirect_offset = offset;
 625    return reg;
 626 }
 627
 628 static INLINE struct brw_reg brw_vec1_indirect( GLuint subnr,
 629                                                   GLint offset )
 630 {
 631    struct brw_reg reg =  brw_vec1_grf(0, 0);
 632    reg.subnr = subnr;
 633    reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
 634    reg.dw1.bits.indirect_offset = offset;
 635    return reg;
 636 }
 637
 638 static INLINE struct brw_reg deref_4f(struct brw_indirect ptr, GLint offset)
 639 {
 640    return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 641 }
 642
 643 static INLINE struct brw_reg deref_1f(struct brw_indirect ptr, GLint offset)
 644 {
 645    return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
 646 }
 647
 648 static INLINE struct brw_reg deref_4b(struct brw_indirect ptr, GLint offset)
 649 {
 650    return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
 651 }
 652
 653 static INLINE struct brw_reg deref_1uw(struct brw_indirect ptr, GLint offset)
 654 {
 655    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
 656 }
 657
 658 static INLINE struct brw_reg deref_1d(struct brw_indirect ptr, GLint offset)
 659 {
 660    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
 661 }
 662
 663 static INLINE struct brw_reg deref_1ud(struct brw_indirect ptr, GLint offset)
 664 {
 665    return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
 666 }
 667
 668 static INLINE struct brw_reg get_addr_reg(struct brw_indirect ptr)
 669 {
 670    return brw_address_reg(ptr.addr_subnr);
 671 }
 672
 673 static INLINE struct brw_indirect brw_indirect_offset( struct brw_indirect ptr, GLint offset )
 674 {
 675    ptr.addr_offset += offset;
 676    return ptr;
 677 }
 678
 679 static INLINE struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offset )
 680 {
 681    struct brw_indirect ptr;
 682    ptr.addr_subnr = addr_subnr;
 683    ptr.addr_offset = offset;
 684    ptr.pad = 0;
 685    return ptr;
 686 }
 687
 688 static INLINE struct brw_instruction *current_insn( struct brw_compile *p)
 689 {
 690         return &p->store[p->nr_insn];
 691 }
 692
 693 void brw_pop_insn_state( struct brw_compile *p );
 694 void brw_push_insn_state( struct brw_compile *p );
 695 void brw_set_mask_control( struct brw_compile *p, GLuint value );
 696 void brw_set_saturate( struct brw_compile *p, GLuint value );
 697 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode );
 698 void brw_set_compression_control( struct brw_compile *p, GLboolean control );
 699 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
 700 void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
 701 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
 702
 703 void brw_init_compile( struct brw_context *, struct brw_compile *p );
 704 const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
 705
 706
 707 /* Helpers for regular instructions:
 708  */
 709 #define ALU1(OP)                                        \
 710 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 711               struct brw_reg dest,                      \
 712               struct brw_reg src0);
 713
 714 #define ALU2(OP)                                        \
 715 struct brw_instruction *brw_##OP(struct brw_compile *p, \
 716               struct brw_reg dest,                      \
 717               struct brw_reg src0,                      \
 718               struct brw_reg src1);
 719
 720 ALU1(MOV)
 721 ALU2(SEL)
 722 ALU1(NOT)
 723 ALU2(AND)
 724 ALU2(OR)
 725 ALU2(XOR)
 726 ALU2(SHR)
 727 ALU2(SHL)
 728 ALU2(RSR)
 729 ALU2(RSL)
 730 ALU2(ASR)
 731 ALU2(JMPI)
 732 ALU2(ADD)
 733 ALU2(MUL)
 734 ALU1(FRC)
 735 ALU1(RNDD)
 736 ALU2(MAC)
 737 ALU2(MACH)
 738 ALU1(LZD)
 739 ALU2(DP4)
 740 ALU2(DPH)
 741 ALU2(DP3)
 742 ALU2(DP2)
 743 ALU2(LINE)
 744
 745 #undef ALU1
 746 #undef ALU2
 747
 748
 749
 750 /* Helpers for SEND instruction:
 751  */
 752 void brw_urb_WRITE(struct brw_compile *p,
 753                    struct brw_reg dest,
 754                    GLuint msg_reg_nr,
 755                    struct brw_reg src0,
 756                    GLboolean allocate,
 757                    GLboolean used,
 758                    GLuint msg_length,
 759                    GLuint response_length,
 760                    GLboolean eot,
 761                    GLboolean writes_complete,
 762                    GLuint offset,
 763                    GLuint swizzle);
 764
 765 void brw_fb_WRITE(struct brw_compile *p,
 766                    struct brw_reg dest,
 767                    GLuint msg_reg_nr,
 768                    struct brw_reg src0,
 769                    GLuint binding_table_index,
 770                    GLuint msg_length,
 771                    GLuint response_length,
 772                    GLboolean eot);
 773
 774 void brw_SAMPLE(struct brw_compile *p,
 775                 struct brw_reg dest,
 776                 GLuint msg_reg_nr,
 777                 struct brw_reg src0,
 778                 GLuint binding_table_index,
 779                 GLuint sampler,
 780                 GLuint writemask,
 781                 GLuint msg_type,
 782                 GLuint response_length,
 783                 GLuint msg_length,
 784                 GLboolean eot);
 785
 786 void brw_math_16( struct brw_compile *p,
 787                   struct brw_reg dest,
 788                   GLuint function,
 789                   GLuint saturate,
 790                   GLuint msg_reg_nr,
 791                   struct brw_reg src,
 792                   GLuint precision );
 793
 794 void brw_math( struct brw_compile *p,
 795                struct brw_reg dest,
 796                GLuint function,
 797                GLuint saturate,
 798                GLuint msg_reg_nr,
 799                struct brw_reg src,
 800                GLuint data_type,
 801                GLuint precision );
 802
 803 void brw_dp_READ_16( struct brw_compile *p,
 804                      struct brw_reg dest,
 805                      GLuint msg_reg_nr,
 806                      GLuint scratch_offset );
 807
 808 void brw_dp_WRITE_16( struct brw_compile *p,
 809                       struct brw_reg src,
 810                       GLuint msg_reg_nr,
 811                       GLuint scratch_offset );
 812
 813 /* If/else/endif.  Works by manipulating the execution flags on each
 814  * channel.
 815  */
 816 struct brw_instruction *brw_IF(struct brw_compile *p,
 817                                GLuint execute_size);
 818
 819 struct brw_instruction *brw_ELSE(struct brw_compile *p,
 820                                  struct brw_instruction *if_insn);
 821
 822 void brw_ENDIF(struct brw_compile *p,
 823                struct brw_instruction *if_or_else_insn);
 824
 825
 826 /* DO/WHILE loops:
 827  */
 828 struct brw_instruction *brw_DO(struct brw_compile *p,
 829                                GLuint execute_size);
 830
 831 struct brw_instruction *brw_WHILE(struct brw_compile *p,
 832                struct brw_instruction *patch_insn);
 833
 834 struct brw_instruction *brw_BREAK(struct brw_compile *p);
 835 struct brw_instruction *brw_CONT(struct brw_compile *p);
 836 /* Forward jumps:
 837  */
 838 void brw_land_fwd_jump(struct brw_compile *p,
 839                        struct brw_instruction *jmp_insn);
 840
 841
 842
 843 void brw_NOP(struct brw_compile *p);
 844
 845 /* Special case: there is never a destination, execution size will be
 846  * taken from src0:
 847  */
 848 void brw_CMP(struct brw_compile *p,
 849              struct brw_reg dest,
 850              GLuint conditional,
 851              struct brw_reg src0,
 852              struct brw_reg src1);
 853
 854 void brw_print_reg( struct brw_reg reg );
 855
 856
 857 /***********************************************************************
 858  * brw_eu_util.c:
 859  */
 860
 861 void brw_copy_indirect_to_indirect(struct brw_compile *p,
 862                                    struct brw_indirect dst_ptr,
 863                                    struct brw_indirect src_ptr,
 864                                    GLuint count);
 865
 866 void brw_copy_from_indirect(struct brw_compile *p,
 867                             struct brw_reg dst,
 868                             struct brw_indirect ptr,
 869                             GLuint count);
 870
 871 void brw_copy4(struct brw_compile *p,
 872                struct brw_reg dst,
 873                struct brw_reg src,
 874                GLuint count);
 875
 876 void brw_copy8(struct brw_compile *p,
 877                struct brw_reg dst,
 878                struct brw_reg src,
 879                GLuint count);
 880
 881 void brw_math_invert( struct brw_compile *p,
 882                       struct brw_reg dst,
 883                       struct brw_reg src);
 884
 885 void brw_set_src1( struct brw_instruction *insn,
 886                           struct brw_reg reg );
 887 #endif