2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 #include "brw_structs.h"
38 #include "brw_defines.h"
39 #include "program/prog_instruction.h"
41 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
42 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
44 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
45 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
46 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
47 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
48 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
49 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
50 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
53 #define REG_SIZE (8*4)
56 /* These aren't hardware structs, just something useful for us to pass around:
58 * Align1 operation has a lot of control over input ranges. Used in
59 * WM programs to implement shaders decomposed into "channel serial"
60 * or "structure of array" form:
67 GLuint subnr
:5; /* :1 in align16 */
68 GLuint negate
:1; /* source only */
69 GLuint abs
:1; /* source only */
70 GLuint vstride
:4; /* source only */
71 GLuint width
:3; /* src only, align1 only */
72 GLuint hstride
:2; /* align1 only */
73 GLuint address_mode
:1; /* relative addressing, hopefully! */
78 GLuint swizzle
:8; /* src only, align16 only */
79 GLuint writemask
:4; /* dest only, align16 only */
80 GLint indirect_offset
:10; /* relative addressing offset */
81 GLuint pad1
:10; /* two dwords total */
98 struct brw_glsl_label
;
103 #define BRW_EU_MAX_INSN_STACK 5
104 #define BRW_EU_MAX_INSN 10000
107 struct brw_instruction store
[BRW_EU_MAX_INSN
];
112 /* Allow clients to push/pop instruction state:
114 struct brw_instruction stack
[BRW_EU_MAX_INSN_STACK
];
115 bool compressed_stack
[BRW_EU_MAX_INSN_STACK
];
116 struct brw_instruction
*current
;
119 bool single_program_flow
;
121 struct brw_context
*brw
;
123 /* Control flow stacks:
124 * - if_stack contains IF and ELSE instructions which must be patched
125 * (and popped) once the matching ENDIF instruction is encountered.
127 struct brw_instruction
**if_stack
;
129 int if_stack_array_size
;
131 struct brw_glsl_label
*first_label
; /**< linked list of labels */
132 struct brw_glsl_call
*first_call
; /**< linked list of CALs */
137 brw_save_label(struct brw_compile
*c
, const char *name
, GLuint position
);
140 brw_save_call(struct brw_compile
*c
, const char *name
, GLuint call_pos
);
143 brw_resolve_cals(struct brw_compile
*c
);
147 static INLINE
int type_sz( GLuint type
)
150 case BRW_REGISTER_TYPE_UD
:
151 case BRW_REGISTER_TYPE_D
:
152 case BRW_REGISTER_TYPE_F
:
154 case BRW_REGISTER_TYPE_HF
:
155 case BRW_REGISTER_TYPE_UW
:
156 case BRW_REGISTER_TYPE_W
:
158 case BRW_REGISTER_TYPE_UB
:
159 case BRW_REGISTER_TYPE_B
:
167 * Construct a brw_reg.
168 * \param file one of the BRW_x_REGISTER_FILE values
169 * \param nr register number/index
170 * \param subnr register sub number
171 * \param type one of BRW_REGISTER_TYPE_x
172 * \param vstride one of BRW_VERTICAL_STRIDE_x
173 * \param width one of BRW_WIDTH_x
174 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
175 * \param swizzle one of BRW_SWIZZLE_x
176 * \param writemask WRITEMASK_X/Y/Z/W bitfield
178 static INLINE
struct brw_reg
brw_reg( GLuint file
,
189 if (file
== BRW_GENERAL_REGISTER_FILE
)
190 assert(nr
< BRW_MAX_GRF
);
191 else if (file
== BRW_MESSAGE_REGISTER_FILE
)
192 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
193 else if (file
== BRW_ARCHITECTURE_REGISTER_FILE
)
194 assert(nr
<= BRW_ARF_IP
);
199 reg
.subnr
= subnr
* type_sz(type
);
202 reg
.vstride
= vstride
;
204 reg
.hstride
= hstride
;
205 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
208 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
209 * set swizzle and writemask to W, as the lower bits of subnr will
210 * be lost when converted to align16. This is probably too much to
211 * keep track of as you'd want it adjusted by suboffset(), etc.
212 * Perhaps fix up when converting to align16?
214 reg
.dw1
.bits
.swizzle
= swizzle
;
215 reg
.dw1
.bits
.writemask
= writemask
;
216 reg
.dw1
.bits
.indirect_offset
= 0;
217 reg
.dw1
.bits
.pad1
= 0;
221 /** Construct float[16] register */
222 static INLINE
struct brw_reg
brw_vec16_reg( GLuint file
,
230 BRW_VERTICAL_STRIDE_16
,
232 BRW_HORIZONTAL_STRIDE_1
,
237 /** Construct float[8] register */
238 static INLINE
struct brw_reg
brw_vec8_reg( GLuint file
,
246 BRW_VERTICAL_STRIDE_8
,
248 BRW_HORIZONTAL_STRIDE_1
,
253 /** Construct float[4] register */
254 static INLINE
struct brw_reg
brw_vec4_reg( GLuint file
,
262 BRW_VERTICAL_STRIDE_4
,
264 BRW_HORIZONTAL_STRIDE_1
,
269 /** Construct float[2] register */
270 static INLINE
struct brw_reg
brw_vec2_reg( GLuint file
,
278 BRW_VERTICAL_STRIDE_2
,
280 BRW_HORIZONTAL_STRIDE_1
,
285 /** Construct float[1] register */
286 static INLINE
struct brw_reg
brw_vec1_reg( GLuint file
,
294 BRW_VERTICAL_STRIDE_0
,
296 BRW_HORIZONTAL_STRIDE_0
,
302 static INLINE
struct brw_reg
retype( struct brw_reg reg
,
309 static inline struct brw_reg
310 sechalf(struct brw_reg reg
)
317 static INLINE
struct brw_reg
suboffset( struct brw_reg reg
,
320 reg
.subnr
+= delta
* type_sz(reg
.type
);
325 static INLINE
struct brw_reg
offset( struct brw_reg reg
,
333 static INLINE
struct brw_reg
byte_offset( struct brw_reg reg
,
336 GLuint newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
337 reg
.nr
= newoffset
/ REG_SIZE
;
338 reg
.subnr
= newoffset
% REG_SIZE
;
343 /** Construct unsigned word[16] register */
344 static INLINE
struct brw_reg
brw_uw16_reg( GLuint file
,
348 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
351 /** Construct unsigned word[8] register */
352 static INLINE
struct brw_reg
brw_uw8_reg( GLuint file
,
356 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
359 /** Construct unsigned word[1] register */
360 static INLINE
struct brw_reg
brw_uw1_reg( GLuint file
,
364 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
367 static INLINE
struct brw_reg
brw_imm_reg( GLuint type
)
369 return brw_reg( BRW_IMMEDIATE_VALUE
,
373 BRW_VERTICAL_STRIDE_0
,
375 BRW_HORIZONTAL_STRIDE_0
,
380 /** Construct float immediate register */
381 static INLINE
struct brw_reg
brw_imm_f( GLfloat f
)
383 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
388 /** Construct integer immediate register */
389 static INLINE
struct brw_reg
brw_imm_d( GLint d
)
391 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
396 /** Construct uint immediate register */
397 static INLINE
struct brw_reg
brw_imm_ud( GLuint ud
)
399 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
404 /** Construct ushort immediate register */
405 static INLINE
struct brw_reg
brw_imm_uw( GLushort uw
)
407 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
408 imm
.dw1
.ud
= uw
| (uw
<< 16);
412 /** Construct short immediate register */
413 static INLINE
struct brw_reg
brw_imm_w( GLshort w
)
415 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
416 imm
.dw1
.d
= w
| (w
<< 16);
420 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
421 * numbers alias with _V and _VF below:
424 /** Construct vector of eight signed half-byte values */
425 static INLINE
struct brw_reg
brw_imm_v( GLuint v
)
427 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
428 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
429 imm
.width
= BRW_WIDTH_8
;
430 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
435 /** Construct vector of four 8-bit float values */
436 static INLINE
struct brw_reg
brw_imm_vf( GLuint v
)
438 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
439 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
440 imm
.width
= BRW_WIDTH_4
;
441 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
448 #define VF_NEG (1<<7)
450 static INLINE
struct brw_reg
brw_imm_vf4( GLuint v0
,
455 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
456 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
457 imm
.width
= BRW_WIDTH_4
;
458 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
459 imm
.dw1
.ud
= ((v0
<< 0) |
467 static INLINE
struct brw_reg
brw_address( struct brw_reg reg
)
469 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
472 /** Construct float[1] general-purpose register */
473 static INLINE
struct brw_reg
brw_vec1_grf( GLuint nr
, GLuint subnr
)
475 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
478 /** Construct float[2] general-purpose register */
479 static INLINE
struct brw_reg
brw_vec2_grf( GLuint nr
, GLuint subnr
)
481 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
484 /** Construct float[4] general-purpose register */
485 static INLINE
struct brw_reg
brw_vec4_grf( GLuint nr
, GLuint subnr
)
487 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
490 /** Construct float[8] general-purpose register */
491 static INLINE
struct brw_reg
brw_vec8_grf( GLuint nr
, GLuint subnr
)
493 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
497 static INLINE
struct brw_reg
brw_uw8_grf( GLuint nr
, GLuint subnr
)
499 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
502 static INLINE
struct brw_reg
brw_uw16_grf( GLuint nr
, GLuint subnr
)
504 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
508 /** Construct null register (usually used for setting condition codes) */
509 static INLINE
struct brw_reg
brw_null_reg( void )
511 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
516 static INLINE
struct brw_reg
brw_address_reg( GLuint subnr
)
518 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
523 /* If/else instructions break in align16 mode if writemask & swizzle
524 * aren't xyzw. This goes against the convention for other scalar
527 static INLINE
struct brw_reg
brw_ip_reg( void )
529 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
532 BRW_REGISTER_TYPE_UD
,
533 BRW_VERTICAL_STRIDE_4
, /* ? */
535 BRW_HORIZONTAL_STRIDE_0
,
536 BRW_SWIZZLE_XYZW
, /* NOTE! */
537 WRITEMASK_XYZW
); /* NOTE! */
540 static INLINE
struct brw_reg
brw_acc_reg( void )
542 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
547 static INLINE
struct brw_reg
brw_notification_1_reg(void)
550 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
551 BRW_ARF_NOTIFICATION_COUNT
,
553 BRW_REGISTER_TYPE_UD
,
554 BRW_VERTICAL_STRIDE_0
,
556 BRW_HORIZONTAL_STRIDE_0
,
562 static INLINE
struct brw_reg
brw_flag_reg( void )
564 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
570 static INLINE
struct brw_reg
brw_mask_reg( GLuint subnr
)
572 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
577 static INLINE
struct brw_reg
brw_message_reg( GLuint nr
)
579 assert((nr
& ~(1 << 7)) < BRW_MAX_MRF
);
580 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
,
588 /* This is almost always called with a numeric constant argument, so
589 * make things easy to evaluate at compile time:
591 static INLINE GLuint
cvt( GLuint val
)
605 static INLINE
struct brw_reg
stride( struct brw_reg reg
,
610 reg
.vstride
= cvt(vstride
);
611 reg
.width
= cvt(width
) - 1;
612 reg
.hstride
= cvt(hstride
);
617 static INLINE
struct brw_reg
vec16( struct brw_reg reg
)
619 return stride(reg
, 16,16,1);
622 static INLINE
struct brw_reg
vec8( struct brw_reg reg
)
624 return stride(reg
, 8,8,1);
627 static INLINE
struct brw_reg
vec4( struct brw_reg reg
)
629 return stride(reg
, 4,4,1);
632 static INLINE
struct brw_reg
vec2( struct brw_reg reg
)
634 return stride(reg
, 2,2,1);
637 static INLINE
struct brw_reg
vec1( struct brw_reg reg
)
639 return stride(reg
, 0,1,0);
643 static INLINE
struct brw_reg
get_element( struct brw_reg reg
, GLuint elt
)
645 return vec1(suboffset(reg
, elt
));
648 static INLINE
struct brw_reg
get_element_ud( struct brw_reg reg
, GLuint elt
)
650 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
653 static INLINE
struct brw_reg
get_element_d( struct brw_reg reg
, GLuint elt
)
655 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_D
), elt
));
659 static INLINE
struct brw_reg
brw_swizzle( struct brw_reg reg
,
665 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
667 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, x
),
668 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, y
),
669 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, z
),
670 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, w
));
675 static INLINE
struct brw_reg
brw_swizzle1( struct brw_reg reg
,
678 return brw_swizzle(reg
, x
, x
, x
, x
);
681 static INLINE
struct brw_reg
brw_writemask( struct brw_reg reg
,
684 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
685 reg
.dw1
.bits
.writemask
&= mask
;
689 static INLINE
struct brw_reg
brw_set_writemask( struct brw_reg reg
,
692 assert(reg
.file
!= BRW_IMMEDIATE_VALUE
);
693 reg
.dw1
.bits
.writemask
= mask
;
697 static INLINE
struct brw_reg
negate( struct brw_reg reg
)
703 static INLINE
struct brw_reg
brw_abs( struct brw_reg reg
)
710 /***********************************************************************
712 static INLINE
struct brw_reg
brw_vec4_indirect( GLuint subnr
,
715 struct brw_reg reg
= brw_vec4_grf(0, 0);
717 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
718 reg
.dw1
.bits
.indirect_offset
= offset
;
722 static INLINE
struct brw_reg
brw_vec1_indirect( GLuint subnr
,
725 struct brw_reg reg
= brw_vec1_grf(0, 0);
727 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
728 reg
.dw1
.bits
.indirect_offset
= offset
;
732 static INLINE
struct brw_reg
deref_4f(struct brw_indirect ptr
, GLint offset
)
734 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
737 static INLINE
struct brw_reg
deref_1f(struct brw_indirect ptr
, GLint offset
)
739 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
742 static INLINE
struct brw_reg
deref_4b(struct brw_indirect ptr
, GLint offset
)
744 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
747 static INLINE
struct brw_reg
deref_1uw(struct brw_indirect ptr
, GLint offset
)
749 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
752 static INLINE
struct brw_reg
deref_1d(struct brw_indirect ptr
, GLint offset
)
754 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
757 static INLINE
struct brw_reg
deref_1ud(struct brw_indirect ptr
, GLint offset
)
759 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
762 static INLINE
struct brw_reg
get_addr_reg(struct brw_indirect ptr
)
764 return brw_address_reg(ptr
.addr_subnr
);
767 static INLINE
struct brw_indirect
brw_indirect_offset( struct brw_indirect ptr
, GLint offset
)
769 ptr
.addr_offset
+= offset
;
773 static INLINE
struct brw_indirect
brw_indirect( GLuint addr_subnr
, GLint offset
)
775 struct brw_indirect ptr
;
776 ptr
.addr_subnr
= addr_subnr
;
777 ptr
.addr_offset
= offset
;
782 /** Do two brw_regs refer to the same register? */
784 brw_same_reg(struct brw_reg r1
, struct brw_reg r2
)
786 return r1
.file
== r2
.file
&& r1
.nr
== r2
.nr
;
789 static INLINE
struct brw_instruction
*current_insn( struct brw_compile
*p
)
791 return &p
->store
[p
->nr_insn
];
794 void brw_pop_insn_state( struct brw_compile
*p
);
795 void brw_push_insn_state( struct brw_compile
*p
);
796 void brw_set_mask_control( struct brw_compile
*p
, GLuint value
);
797 void brw_set_saturate( struct brw_compile
*p
, GLuint value
);
798 void brw_set_access_mode( struct brw_compile
*p
, GLuint access_mode
);
799 void brw_set_compression_control(struct brw_compile
*p
, enum brw_compression c
);
800 void brw_set_predicate_control_flag_value( struct brw_compile
*p
, GLuint value
);
801 void brw_set_predicate_control( struct brw_compile
*p
, GLuint pc
);
802 void brw_set_predicate_inverse(struct brw_compile
*p
, bool predicate_inverse
);
803 void brw_set_conditionalmod( struct brw_compile
*p
, GLuint conditional
);
804 void brw_set_acc_write_control(struct brw_compile
*p
, GLuint value
);
806 void brw_init_compile(struct brw_context
*, struct brw_compile
*p
,
808 const GLuint
*brw_get_program( struct brw_compile
*p
, GLuint
*sz
);
810 struct brw_instruction
*brw_next_insn(struct brw_compile
*p
, GLuint opcode
);
811 void brw_set_dest(struct brw_compile
*p
, struct brw_instruction
*insn
,
812 struct brw_reg dest
);
813 void brw_set_src0(struct brw_compile
*p
, struct brw_instruction
*insn
,
816 void gen6_resolve_implied_move(struct brw_compile
*p
,
820 /* Helpers for regular instructions:
823 struct brw_instruction *brw_##OP(struct brw_compile *p, \
824 struct brw_reg dest, \
825 struct brw_reg src0);
828 struct brw_instruction *brw_##OP(struct brw_compile *p, \
829 struct brw_reg dest, \
830 struct brw_reg src0, \
831 struct brw_reg src1);
834 void brw_##OP(struct brw_compile *p, struct brw_reg dest, struct brw_reg src0);
871 /* Helpers for SEND instruction:
873 void brw_set_dp_read_message(struct brw_compile
*p
,
874 struct brw_instruction
*insn
,
875 GLuint binding_table_index
,
880 GLuint response_length
);
882 void brw_set_dp_write_message(struct brw_compile
*p
,
883 struct brw_instruction
*insn
,
884 GLuint binding_table_index
,
889 GLuint last_render_target
,
890 GLuint response_length
,
891 GLuint end_of_thread
,
892 GLuint send_commit_msg
);
894 void brw_urb_WRITE(struct brw_compile
*p
,
901 GLuint response_length
,
903 bool writes_complete
,
907 void brw_ff_sync(struct brw_compile
*p
,
912 GLuint response_length
,
915 void brw_svb_write(struct brw_compile
*p
,
919 GLuint binding_table_index
,
920 bool send_commit_msg
);
922 void brw_fb_WRITE(struct brw_compile
*p
,
926 GLuint binding_table_index
,
928 GLuint response_length
,
930 bool header_present
);
932 void brw_SAMPLE(struct brw_compile
*p
,
936 GLuint binding_table_index
,
940 GLuint response_length
,
942 GLuint header_present
,
944 GLuint return_format
);
946 void brw_math_16( struct brw_compile
*p
,
954 void brw_math( struct brw_compile
*p
,
963 void brw_math2(struct brw_compile
*p
,
967 struct brw_reg src1
);
969 void brw_oword_block_read(struct brw_compile
*p
,
973 uint32_t bind_table_index
);
975 void brw_oword_block_read_scratch(struct brw_compile
*p
,
981 void brw_oword_block_write_scratch(struct brw_compile
*p
,
986 void brw_dword_scattered_read(struct brw_compile
*p
,
989 uint32_t bind_table_index
);
991 void brw_dp_READ_4_vs( struct brw_compile
*p
,
994 GLuint bind_table_index
);
996 void brw_dp_READ_4_vs_relative(struct brw_compile
*p
,
998 struct brw_reg addrReg
,
1000 GLuint bind_table_index
);
1002 /* If/else/endif. Works by manipulating the execution flags on each
1005 struct brw_instruction
*brw_IF(struct brw_compile
*p
,
1006 GLuint execute_size
);
1007 struct brw_instruction
*gen6_IF(struct brw_compile
*p
, uint32_t conditional
,
1008 struct brw_reg src0
, struct brw_reg src1
);
1010 void brw_ELSE(struct brw_compile
*p
);
1011 void brw_ENDIF(struct brw_compile
*p
);
1015 struct brw_instruction
*brw_DO(struct brw_compile
*p
,
1016 GLuint execute_size
);
1018 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
,
1019 struct brw_instruction
*patch_insn
);
1021 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
, int pop_count
);
1022 struct brw_instruction
*brw_CONT(struct brw_compile
*p
, int pop_count
);
1023 struct brw_instruction
*gen6_CONT(struct brw_compile
*p
,
1024 struct brw_instruction
*do_insn
);
1027 void brw_land_fwd_jump(struct brw_compile
*p
,
1028 struct brw_instruction
*jmp_insn
);
1032 void brw_NOP(struct brw_compile
*p
);
1034 void brw_WAIT(struct brw_compile
*p
);
1036 /* Special case: there is never a destination, execution size will be
1039 void brw_CMP(struct brw_compile
*p
,
1040 struct brw_reg dest
,
1042 struct brw_reg src0
,
1043 struct brw_reg src1
);
1045 void brw_print_reg( struct brw_reg reg
);
1048 /***********************************************************************
1052 void brw_copy_indirect_to_indirect(struct brw_compile
*p
,
1053 struct brw_indirect dst_ptr
,
1054 struct brw_indirect src_ptr
,
1057 void brw_copy_from_indirect(struct brw_compile
*p
,
1059 struct brw_indirect ptr
,
1062 void brw_copy4(struct brw_compile
*p
,
1067 void brw_copy8(struct brw_compile
*p
,
1072 void brw_math_invert( struct brw_compile
*p
,
1074 struct brw_reg src
);
1076 void brw_set_src1(struct brw_compile
*p
,
1077 struct brw_instruction
*insn
,
1078 struct brw_reg reg
);
1080 void brw_set_uip_jip(struct brw_compile
*p
);
1082 uint32_t brw_swap_cmod(uint32_t cmod
);
1084 /* brw_optimize.c */
1085 void brw_optimize(struct brw_compile
*p
);
1086 void brw_remove_duplicate_mrf_moves(struct brw_compile
*p
);
1087 void brw_remove_grf_to_mrf_moves(struct brw_compile
*p
);