2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
36 #include "brw_structs.h"
37 #include "brw_defines.h"
38 #include "shader/prog_instruction.h"
40 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
41 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
43 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
44 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
45 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
46 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
49 #define REG_SIZE (8*4)
52 /* These aren't hardware structs, just something useful for us to pass around:
54 * Align1 operation has a lot of control over input ranges. Used in
55 * WM programs to implement shaders decomposed into "channel serial"
56 * or "structure of array" form:
63 GLuint subnr
:5; /* :1 in align16 */
64 GLuint negate
:1; /* source only */
65 GLuint abs
:1; /* source only */
66 GLuint vstride
:4; /* source only */
67 GLuint width
:3; /* src only, align1 only */
68 GLuint hstride
:2; /* align1 only */
69 GLuint address_mode
:1; /* relative addressing, hopefully! */
74 GLuint swizzle
:8; /* src only, align16 only */
75 GLuint writemask
:4; /* dest only, align16 only */
76 GLint indirect_offset
:10; /* relative addressing offset */
77 GLuint pad1
:10; /* two dwords total */
94 struct brw_glsl_label
;
99 #define BRW_EU_MAX_INSN_STACK 5
100 #define BRW_EU_MAX_INSN 4000
103 struct brw_instruction store
[BRW_EU_MAX_INSN
];
106 /* Allow clients to push/pop instruction state:
108 struct brw_instruction stack
[BRW_EU_MAX_INSN_STACK
];
109 struct brw_instruction
*current
;
112 GLboolean single_program_flow
;
113 struct brw_context
*brw
;
115 struct brw_glsl_label
*first_label
; /**< linked list of labels */
116 struct brw_glsl_call
*first_call
; /**< linked list of CALs */
121 brw_save_label(struct brw_compile
*c
, const char *name
, GLuint position
);
124 brw_save_call(struct brw_compile
*c
, const char *name
, GLuint call_pos
);
127 brw_resolve_cals(struct brw_compile
*c
);
131 static INLINE
int type_sz( GLuint type
)
134 case BRW_REGISTER_TYPE_UD
:
135 case BRW_REGISTER_TYPE_D
:
136 case BRW_REGISTER_TYPE_F
:
138 case BRW_REGISTER_TYPE_HF
:
139 case BRW_REGISTER_TYPE_UW
:
140 case BRW_REGISTER_TYPE_W
:
142 case BRW_REGISTER_TYPE_UB
:
143 case BRW_REGISTER_TYPE_B
:
151 * Construct a brw_reg.
152 * \param file one of the BRW_x_REGISTER_FILE values
153 * \param nr register number/index
154 * \param subnr register sub number
155 * \param type one of BRW_REGISTER_TYPE_x
156 * \param vstride one of BRW_VERTICAL_STRIDE_x
157 * \param width one of BRW_WIDTH_x
158 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
159 * \param swizzle one of BRW_SWIZZLE_x
160 * \param writemask WRITEMASK_X/Y/Z/W bitfield
162 static INLINE
struct brw_reg
brw_reg( GLuint file
,
173 if (type
== BRW_GENERAL_REGISTER_FILE
)
175 else if (type
== BRW_MESSAGE_REGISTER_FILE
)
177 else if (type
== BRW_ARCHITECTURE_REGISTER_FILE
)
178 assert(nr
<= BRW_ARF_IP
);
183 reg
.subnr
= subnr
* type_sz(type
);
186 reg
.vstride
= vstride
;
188 reg
.hstride
= hstride
;
189 reg
.address_mode
= BRW_ADDRESS_DIRECT
;
192 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
193 * set swizzle and writemask to W, as the lower bits of subnr will
194 * be lost when converted to align16. This is probably too much to
195 * keep track of as you'd want it adjusted by suboffset(), etc.
196 * Perhaps fix up when converting to align16?
198 reg
.dw1
.bits
.swizzle
= swizzle
;
199 reg
.dw1
.bits
.writemask
= writemask
;
200 reg
.dw1
.bits
.indirect_offset
= 0;
201 reg
.dw1
.bits
.pad1
= 0;
205 /** Construct float[16] register */
206 static INLINE
struct brw_reg
brw_vec16_reg( GLuint file
,
214 BRW_VERTICAL_STRIDE_16
,
216 BRW_HORIZONTAL_STRIDE_1
,
221 /** Construct float[8] register */
222 static INLINE
struct brw_reg
brw_vec8_reg( GLuint file
,
230 BRW_VERTICAL_STRIDE_8
,
232 BRW_HORIZONTAL_STRIDE_1
,
237 /** Construct float[4] register */
238 static INLINE
struct brw_reg
brw_vec4_reg( GLuint file
,
246 BRW_VERTICAL_STRIDE_4
,
248 BRW_HORIZONTAL_STRIDE_1
,
253 /** Construct float[2] register */
254 static INLINE
struct brw_reg
brw_vec2_reg( GLuint file
,
262 BRW_VERTICAL_STRIDE_2
,
264 BRW_HORIZONTAL_STRIDE_1
,
269 /** Construct float[1] register */
270 static INLINE
struct brw_reg
brw_vec1_reg( GLuint file
,
278 BRW_VERTICAL_STRIDE_0
,
280 BRW_HORIZONTAL_STRIDE_0
,
286 static INLINE
struct brw_reg
retype( struct brw_reg reg
,
293 static INLINE
struct brw_reg
suboffset( struct brw_reg reg
,
296 reg
.subnr
+= delta
* type_sz(reg
.type
);
301 static INLINE
struct brw_reg
offset( struct brw_reg reg
,
309 static INLINE
struct brw_reg
byte_offset( struct brw_reg reg
,
312 GLuint newoffset
= reg
.nr
* REG_SIZE
+ reg
.subnr
+ bytes
;
313 reg
.nr
= newoffset
/ REG_SIZE
;
314 reg
.subnr
= newoffset
% REG_SIZE
;
319 /** Construct unsigned word[16] register */
320 static INLINE
struct brw_reg
brw_uw16_reg( GLuint file
,
324 return suboffset(retype(brw_vec16_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
327 /** Construct unsigned word[8] register */
328 static INLINE
struct brw_reg
brw_uw8_reg( GLuint file
,
332 return suboffset(retype(brw_vec8_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
335 /** Construct unsigned word[1] register */
336 static INLINE
struct brw_reg
brw_uw1_reg( GLuint file
,
340 return suboffset(retype(brw_vec1_reg(file
, nr
, 0), BRW_REGISTER_TYPE_UW
), subnr
);
343 static INLINE
struct brw_reg
brw_imm_reg( GLuint type
)
345 return brw_reg( BRW_IMMEDIATE_VALUE
,
349 BRW_VERTICAL_STRIDE_0
,
351 BRW_HORIZONTAL_STRIDE_0
,
356 /** Construct float immediate register */
357 static INLINE
struct brw_reg
brw_imm_f( GLfloat f
)
359 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_F
);
364 /** Construct integer immediate register */
365 static INLINE
struct brw_reg
brw_imm_d( GLint d
)
367 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_D
);
372 /** Construct uint immediate register */
373 static INLINE
struct brw_reg
brw_imm_ud( GLuint ud
)
375 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UD
);
380 /** Construct ushort immediate register */
381 static INLINE
struct brw_reg
brw_imm_uw( GLushort uw
)
383 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_UW
);
384 imm
.dw1
.ud
= uw
| (uw
<< 16);
388 /** Construct short immediate register */
389 static INLINE
struct brw_reg
brw_imm_w( GLshort w
)
391 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_W
);
392 imm
.dw1
.d
= w
| (w
<< 16);
396 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
397 * numbers alias with _V and _VF below:
400 /** Construct vector of eight signed half-byte values */
401 static INLINE
struct brw_reg
brw_imm_v( GLuint v
)
403 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_V
);
404 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
405 imm
.width
= BRW_WIDTH_8
;
406 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
411 /** Construct vector of four 8-bit float values */
412 static INLINE
struct brw_reg
brw_imm_vf( GLuint v
)
414 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
415 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
416 imm
.width
= BRW_WIDTH_4
;
417 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
424 #define VF_NEG (1<<7)
426 static INLINE
struct brw_reg
brw_imm_vf4( GLuint v0
,
431 struct brw_reg imm
= brw_imm_reg(BRW_REGISTER_TYPE_VF
);
432 imm
.vstride
= BRW_VERTICAL_STRIDE_0
;
433 imm
.width
= BRW_WIDTH_4
;
434 imm
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
435 imm
.dw1
.ud
= ((v0
<< 0) |
443 static INLINE
struct brw_reg
brw_address( struct brw_reg reg
)
445 return brw_imm_uw(reg
.nr
* REG_SIZE
+ reg
.subnr
);
448 /** Construct float[1] general-purpose register */
449 static INLINE
struct brw_reg
brw_vec1_grf( GLuint nr
, GLuint subnr
)
451 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
454 /** Construct float[2] general-purpose register */
455 static INLINE
struct brw_reg
brw_vec2_grf( GLuint nr
, GLuint subnr
)
457 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
460 /** Construct float[4] general-purpose register */
461 static INLINE
struct brw_reg
brw_vec4_grf( GLuint nr
, GLuint subnr
)
463 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
466 /** Construct float[8] general-purpose register */
467 static INLINE
struct brw_reg
brw_vec8_grf( GLuint nr
, GLuint subnr
)
469 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
473 static INLINE
struct brw_reg
brw_uw8_grf( GLuint nr
, GLuint subnr
)
475 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
478 static INLINE
struct brw_reg
brw_uw16_grf( GLuint nr
, GLuint subnr
)
480 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE
, nr
, subnr
);
484 /** Construct null register (usually used for setting condition codes) */
485 static INLINE
struct brw_reg
brw_null_reg( void )
487 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
492 static INLINE
struct brw_reg
brw_address_reg( GLuint subnr
)
494 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
499 /* If/else instructions break in align16 mode if writemask & swizzle
500 * aren't xyzw. This goes against the convention for other scalar
503 static INLINE
struct brw_reg
brw_ip_reg( void )
505 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
508 BRW_REGISTER_TYPE_UD
,
509 BRW_VERTICAL_STRIDE_4
, /* ? */
511 BRW_HORIZONTAL_STRIDE_0
,
512 BRW_SWIZZLE_XYZW
, /* NOTE! */
513 WRITEMASK_XYZW
); /* NOTE! */
516 static INLINE
struct brw_reg
brw_acc_reg( void )
518 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
524 static INLINE
struct brw_reg
brw_flag_reg( void )
526 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
532 static INLINE
struct brw_reg
brw_mask_reg( GLuint subnr
)
534 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
539 static INLINE
struct brw_reg
brw_message_reg( GLuint nr
)
541 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE
,
549 /* This is almost always called with a numeric constant argument, so
550 * make things easy to evaluate at compile time:
552 static INLINE GLuint
cvt( GLuint val
)
566 static INLINE
struct brw_reg
stride( struct brw_reg reg
,
571 reg
.vstride
= cvt(vstride
);
572 reg
.width
= cvt(width
) - 1;
573 reg
.hstride
= cvt(hstride
);
578 static INLINE
struct brw_reg
vec16( struct brw_reg reg
)
580 return stride(reg
, 16,16,1);
583 static INLINE
struct brw_reg
vec8( struct brw_reg reg
)
585 return stride(reg
, 8,8,1);
588 static INLINE
struct brw_reg
vec4( struct brw_reg reg
)
590 return stride(reg
, 4,4,1);
593 static INLINE
struct brw_reg
vec2( struct brw_reg reg
)
595 return stride(reg
, 2,2,1);
598 static INLINE
struct brw_reg
vec1( struct brw_reg reg
)
600 return stride(reg
, 0,1,0);
604 static INLINE
struct brw_reg
get_element( struct brw_reg reg
, GLuint elt
)
606 return vec1(suboffset(reg
, elt
));
609 static INLINE
struct brw_reg
get_element_ud( struct brw_reg reg
, GLuint elt
)
611 return vec1(suboffset(retype(reg
, BRW_REGISTER_TYPE_UD
), elt
));
615 static INLINE
struct brw_reg
brw_swizzle( struct brw_reg reg
,
621 reg
.dw1
.bits
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, x
),
622 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, y
),
623 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, z
),
624 BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, w
));
629 static INLINE
struct brw_reg
brw_swizzle1( struct brw_reg reg
,
632 return brw_swizzle(reg
, x
, x
, x
, x
);
635 static INLINE
struct brw_reg
brw_writemask( struct brw_reg reg
,
638 reg
.dw1
.bits
.writemask
&= mask
;
642 static INLINE
struct brw_reg
brw_set_writemask( struct brw_reg reg
,
645 reg
.dw1
.bits
.writemask
= mask
;
649 static INLINE
struct brw_reg
negate( struct brw_reg reg
)
655 static INLINE
struct brw_reg
brw_abs( struct brw_reg reg
)
661 /***********************************************************************
663 static INLINE
struct brw_reg
brw_vec4_indirect( GLuint subnr
,
666 struct brw_reg reg
= brw_vec4_grf(0, 0);
668 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
669 reg
.dw1
.bits
.indirect_offset
= offset
;
673 static INLINE
struct brw_reg
brw_vec1_indirect( GLuint subnr
,
676 struct brw_reg reg
= brw_vec1_grf(0, 0);
678 reg
.address_mode
= BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
;
679 reg
.dw1
.bits
.indirect_offset
= offset
;
683 static INLINE
struct brw_reg
deref_4f(struct brw_indirect ptr
, GLint offset
)
685 return brw_vec4_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
688 static INLINE
struct brw_reg
deref_1f(struct brw_indirect ptr
, GLint offset
)
690 return brw_vec1_indirect(ptr
.addr_subnr
, ptr
.addr_offset
+ offset
);
693 static INLINE
struct brw_reg
deref_4b(struct brw_indirect ptr
, GLint offset
)
695 return retype(deref_4f(ptr
, offset
), BRW_REGISTER_TYPE_B
);
698 static INLINE
struct brw_reg
deref_1uw(struct brw_indirect ptr
, GLint offset
)
700 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UW
);
703 static INLINE
struct brw_reg
deref_1d(struct brw_indirect ptr
, GLint offset
)
705 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_D
);
708 static INLINE
struct brw_reg
deref_1ud(struct brw_indirect ptr
, GLint offset
)
710 return retype(deref_1f(ptr
, offset
), BRW_REGISTER_TYPE_UD
);
713 static INLINE
struct brw_reg
get_addr_reg(struct brw_indirect ptr
)
715 return brw_address_reg(ptr
.addr_subnr
);
718 static INLINE
struct brw_indirect
brw_indirect_offset( struct brw_indirect ptr
, GLint offset
)
720 ptr
.addr_offset
+= offset
;
724 static INLINE
struct brw_indirect
brw_indirect( GLuint addr_subnr
, GLint offset
)
726 struct brw_indirect ptr
;
727 ptr
.addr_subnr
= addr_subnr
;
728 ptr
.addr_offset
= offset
;
733 /** Do two brw_regs refer to the same register? */
734 static INLINE GLboolean
735 brw_same_reg(struct brw_reg r1
, struct brw_reg r2
)
737 return r1
.file
== r2
.file
&& r1
.nr
== r2
.nr
;
740 static INLINE
struct brw_instruction
*current_insn( struct brw_compile
*p
)
742 return &p
->store
[p
->nr_insn
];
745 void brw_pop_insn_state( struct brw_compile
*p
);
746 void brw_push_insn_state( struct brw_compile
*p
);
747 void brw_set_mask_control( struct brw_compile
*p
, GLuint value
);
748 void brw_set_saturate( struct brw_compile
*p
, GLuint value
);
749 void brw_set_access_mode( struct brw_compile
*p
, GLuint access_mode
);
750 void brw_set_compression_control( struct brw_compile
*p
, GLboolean control
);
751 void brw_set_predicate_control_flag_value( struct brw_compile
*p
, GLuint value
);
752 void brw_set_predicate_control( struct brw_compile
*p
, GLuint pc
);
753 void brw_set_conditionalmod( struct brw_compile
*p
, GLuint conditional
);
755 void brw_init_compile( struct brw_context
*, struct brw_compile
*p
);
756 const GLuint
*brw_get_program( struct brw_compile
*p
, GLuint
*sz
);
759 /* Helpers for regular instructions:
762 struct brw_instruction *brw_##OP(struct brw_compile *p, \
763 struct brw_reg dest, \
764 struct brw_reg src0);
767 struct brw_instruction *brw_##OP(struct brw_compile *p, \
768 struct brw_reg dest, \
769 struct brw_reg src0, \
770 struct brw_reg src1);
803 /* Helpers for SEND instruction:
805 void brw_urb_WRITE(struct brw_compile
*p
,
812 GLuint response_length
,
814 GLboolean writes_complete
,
818 void brw_fb_WRITE(struct brw_compile
*p
,
822 GLuint binding_table_index
,
824 GLuint response_length
,
827 void brw_SAMPLE(struct brw_compile
*p
,
831 GLuint binding_table_index
,
835 GLuint response_length
,
839 void brw_math_16( struct brw_compile
*p
,
847 void brw_math( struct brw_compile
*p
,
856 void brw_dp_READ_16( struct brw_compile
*p
,
859 GLuint scratch_offset
);
861 void brw_dp_READ_4( struct brw_compile
*p
,
865 GLuint scratch_offset
,
866 GLuint bind_table_index
);
868 void brw_dp_WRITE_16( struct brw_compile
*p
,
871 GLuint scratch_offset
);
873 /* If/else/endif. Works by manipulating the execution flags on each
876 struct brw_instruction
*brw_IF(struct brw_compile
*p
,
877 GLuint execute_size
);
879 struct brw_instruction
*brw_ELSE(struct brw_compile
*p
,
880 struct brw_instruction
*if_insn
);
882 void brw_ENDIF(struct brw_compile
*p
,
883 struct brw_instruction
*if_or_else_insn
);
888 struct brw_instruction
*brw_DO(struct brw_compile
*p
,
889 GLuint execute_size
);
891 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
,
892 struct brw_instruction
*patch_insn
);
894 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
);
895 struct brw_instruction
*brw_CONT(struct brw_compile
*p
);
898 void brw_land_fwd_jump(struct brw_compile
*p
,
899 struct brw_instruction
*jmp_insn
);
903 void brw_NOP(struct brw_compile
*p
);
905 /* Special case: there is never a destination, execution size will be
908 void brw_CMP(struct brw_compile
*p
,
912 struct brw_reg src1
);
914 void brw_print_reg( struct brw_reg reg
);
917 /***********************************************************************
921 void brw_copy_indirect_to_indirect(struct brw_compile
*p
,
922 struct brw_indirect dst_ptr
,
923 struct brw_indirect src_ptr
,
926 void brw_copy_from_indirect(struct brw_compile
*p
,
928 struct brw_indirect ptr
,
931 void brw_copy4(struct brw_compile
*p
,
936 void brw_copy8(struct brw_compile
*p
,
941 void brw_math_invert( struct brw_compile
*p
,
945 void brw_set_src1( struct brw_instruction
*insn
,
946 struct brw_reg reg
);