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5 * copy of this software and associated documentation files (the "Software"),
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24 /** @file brw_eu_compact.c
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that. The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
40 * Instruction compaction capabilities vary subtly by generation.
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
68 * else JIP (plus UIP on BDW+)
70 * while JIP (must be negative)
72 * Gen 8 adds support for compacting 3-src instructions.
75 #include "brw_context.h"
77 #include "intel_asm_annotation.h"
78 #include "util/u_atomic.h" /* for p_atomic_cmpxchg */
80 static const uint32_t g45_control_index_table
[32] = {
115 static const uint32_t g45_datatype_table
[32] = {
116 0b001000000000100001,
117 0b001011010110101101,
118 0b001000001000110001,
119 0b001111011110111101,
120 0b001011010110101100,
121 0b001000000110101101,
122 0b001000000000100000,
123 0b010100010110110001,
124 0b001100011000101101,
125 0b001000000000100010,
126 0b001000001000110110,
127 0b010000001000110001,
128 0b001000001000110010,
129 0b011000001000110010,
130 0b001111011110111100,
131 0b001000000100101000,
132 0b010100011000110001,
133 0b001010010100101001,
134 0b001000001000101001,
135 0b010000001000110110,
136 0b101000001000110001,
137 0b001011011000101101,
138 0b001000000100001001,
139 0b001011011000101100,
140 0b110100011000110001,
141 0b001000001110111101,
142 0b110000001000110001,
143 0b011000000100101010,
144 0b101000001000101001,
145 0b001011010110001100,
146 0b001000000110100001,
150 static const uint16_t g45_subreg_table
[32] = {
185 static const uint16_t g45_src_index_table
[32] = {
220 static const uint32_t gen6_control_index_table
[32] = {
255 static const uint32_t gen6_datatype_table
[32] = {
256 0b001001110000000000,
257 0b001000110000100000,
258 0b001001110000000001,
259 0b001000000001100000,
260 0b001010110100101001,
261 0b001000000110101101,
262 0b001100011000101100,
263 0b001011110110101101,
264 0b001000000111101100,
265 0b001000000001100001,
266 0b001000110010100101,
267 0b001000000001000001,
268 0b001000001000110001,
269 0b001000001000101001,
270 0b001000000000100000,
271 0b001000001000110010,
272 0b001010010100101001,
273 0b001011010010100101,
274 0b001000000110100101,
275 0b001100011000101001,
276 0b001011011000101100,
277 0b001011010110100101,
278 0b001011110110100101,
279 0b001111011110111101,
280 0b001111011110111100,
281 0b001111011110111101,
282 0b001111011110011101,
283 0b001111011110111110,
284 0b001000000000100001,
285 0b001000000000100010,
286 0b001001111111011101,
287 0b001000001110111110,
290 static const uint16_t gen6_subreg_table
[32] = {
325 static const uint16_t gen6_src_index_table
[32] = {
360 static const uint32_t gen7_control_index_table
[32] = {
361 0b0000000000000000010,
362 0b0000100000000000000,
363 0b0000100000000000001,
364 0b0000100000000000010,
365 0b0000100000000000011,
366 0b0000100000000000100,
367 0b0000100000000000101,
368 0b0000100000000000111,
369 0b0000100000000001000,
370 0b0000100000000001001,
371 0b0000100000000001101,
372 0b0000110000000000000,
373 0b0000110000000000001,
374 0b0000110000000000010,
375 0b0000110000000000011,
376 0b0000110000000000100,
377 0b0000110000000000101,
378 0b0000110000000000111,
379 0b0000110000000001001,
380 0b0000110000000001101,
381 0b0000110000000010000,
382 0b0000110000100000000,
383 0b0001000000000000000,
384 0b0001000000000000010,
385 0b0001000000000000100,
386 0b0001000000100000000,
387 0b0010110000000000000,
388 0b0010110000000010000,
389 0b0011000000000000000,
390 0b0011000000100000000,
391 0b0101000000000000000,
392 0b0101000000100000000
395 static const uint32_t gen7_datatype_table
[32] = {
396 0b001000000000000001,
397 0b001000000000100000,
398 0b001000000000100001,
399 0b001000000001100001,
400 0b001000000010111101,
401 0b001000001011111101,
402 0b001000001110100001,
403 0b001000001110100101,
404 0b001000001110111101,
405 0b001000010000100001,
406 0b001000110000100000,
407 0b001000110000100001,
408 0b001001010010100101,
409 0b001001110010100100,
410 0b001001110010100101,
411 0b001111001110111101,
412 0b001111011110011101,
413 0b001111011110111100,
414 0b001111011110111101,
415 0b001111111110111100,
416 0b000000001000001100,
417 0b001000000000111101,
418 0b001000000010100101,
419 0b001000010000100000,
420 0b001001010010100100,
421 0b001001110010000100,
422 0b001010010100001001,
423 0b001101111110111101,
424 0b001111111110111101,
425 0b001011110110101100,
426 0b001010010100101000,
430 static const uint16_t gen7_subreg_table
[32] = {
465 static const uint16_t gen7_src_index_table
[32] = {
500 static const uint32_t gen8_control_index_table
[32] = {
501 0b0000000000000000010,
502 0b0000100000000000000,
503 0b0000100000000000001,
504 0b0000100000000000010,
505 0b0000100000000000011,
506 0b0000100000000000100,
507 0b0000100000000000101,
508 0b0000100000000000111,
509 0b0000100000000001000,
510 0b0000100000000001001,
511 0b0000100000000001101,
512 0b0000110000000000000,
513 0b0000110000000000001,
514 0b0000110000000000010,
515 0b0000110000000000011,
516 0b0000110000000000100,
517 0b0000110000000000101,
518 0b0000110000000000111,
519 0b0000110000000001001,
520 0b0000110000000001101,
521 0b0000110000000010000,
522 0b0000110000100000000,
523 0b0001000000000000000,
524 0b0001000000000000010,
525 0b0001000000000000100,
526 0b0001000000100000000,
527 0b0010110000000000000,
528 0b0010110000000010000,
529 0b0011000000000000000,
530 0b0011000000100000000,
531 0b0101000000000000000,
532 0b0101000000100000000
535 static const uint32_t gen8_datatype_table
[32] = {
536 0b001000000000000000001,
537 0b001000000000001000000,
538 0b001000000000001000001,
539 0b001000000000011000001,
540 0b001000000000101011101,
541 0b001000000010111011101,
542 0b001000000011101000001,
543 0b001000000011101000101,
544 0b001000000011101011101,
545 0b001000001000001000001,
546 0b001000011000001000000,
547 0b001000011000001000001,
548 0b001000101000101000101,
549 0b001000111000101000100,
550 0b001000111000101000101,
551 0b001011100011101011101,
552 0b001011101011100011101,
553 0b001011101011101011100,
554 0b001011101011101011101,
555 0b001011111011101011100,
556 0b000000000010000001100,
557 0b001000000000001011101,
558 0b001000000000101000101,
559 0b001000001000001000000,
560 0b001000101000101000100,
561 0b001000111000100000100,
562 0b001001001001000001001,
563 0b001010111011101011101,
564 0b001011111011101011101,
565 0b001001111001101001100,
566 0b001001001001001001000,
567 0b001001011001001001000
570 static const uint16_t gen8_subreg_table
[32] = {
605 static const uint16_t gen8_src_index_table
[32] = {
640 /* This is actually the control index table for Cherryview (26 bits), but the
641 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
644 * The low 24 bits have the same mappings on both hardware.
646 static const uint32_t gen8_3src_control_index_table
[4] = {
647 0b00100000000110000000000001,
648 0b00000000000110000000000001,
649 0b00000000001000000000000001,
650 0b00000000001000000000100001
653 /* This is actually the control index table for Cherryview (49 bits), but the
654 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
657 * The low 44 bits have the same mappings on both hardware, and since the high
658 * three bits on Broadwell are zero, we can reuse Cherryview's table.
660 static const uint64_t gen8_3src_source_index_table
[4] = {
661 0b0000001110010011100100111001000001111000000000000,
662 0b0000001110010011100100111001000001111000000000010,
663 0b0000001110010011100100111001000001111000000001000,
664 0b0000001110010011100100111001000001111000000100000
667 static const uint32_t *control_index_table
;
668 static const uint32_t *datatype_table
;
669 static const uint16_t *subreg_table
;
670 static const uint16_t *src_index_table
;
673 set_control_index(const struct brw_device_info
*devinfo
,
674 brw_compact_inst
*dst
, brw_inst
*src
)
676 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 17b/G45; 19b/IVB+ */
677 ? (brw_inst_bits(src
, 33, 31) << 16) | /* 3b */
678 (brw_inst_bits(src
, 23, 12) << 4) | /* 12b */
679 (brw_inst_bits(src
, 10, 9) << 2) | /* 2b */
680 (brw_inst_bits(src
, 34, 34) << 1) | /* 1b */
681 (brw_inst_bits(src
, 8, 8)) /* 1b */
682 : (brw_inst_bits(src
, 31, 31) << 16) | /* 1b */
683 (brw_inst_bits(src
, 23, 8)); /* 16b */
685 /* On gen7, the flag register and subregister numbers are integrated into
688 if (devinfo
->gen
== 7)
689 uncompacted
|= brw_inst_bits(src
, 90, 89) << 17; /* 2b */
691 for (int i
= 0; i
< 32; i
++) {
692 if (control_index_table
[i
] == uncompacted
) {
693 brw_compact_inst_set_control_index(devinfo
, dst
, i
);
702 set_datatype_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
705 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 18b/G45+; 21b/BDW+ */
706 ? (brw_inst_bits(src
, 63, 61) << 18) | /* 3b */
707 (brw_inst_bits(src
, 94, 89) << 12) | /* 6b */
708 (brw_inst_bits(src
, 46, 35)) /* 12b */
709 : (brw_inst_bits(src
, 63, 61) << 15) | /* 3b */
710 (brw_inst_bits(src
, 46, 32)); /* 15b */
712 for (int i
= 0; i
< 32; i
++) {
713 if (datatype_table
[i
] == uncompacted
) {
714 brw_compact_inst_set_datatype_index(devinfo
, dst
, i
);
723 set_subreg_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
724 brw_inst
*src
, bool is_immediate
)
726 uint16_t uncompacted
= /* 15b */
727 (brw_inst_bits(src
, 52, 48) << 0) | /* 5b */
728 (brw_inst_bits(src
, 68, 64) << 5); /* 5b */
731 uncompacted
|= brw_inst_bits(src
, 100, 96) << 10; /* 5b */
733 for (int i
= 0; i
< 32; i
++) {
734 if (subreg_table
[i
] == uncompacted
) {
735 brw_compact_inst_set_subreg_index(devinfo
, dst
, i
);
744 get_src_index(uint16_t uncompacted
,
747 for (int i
= 0; i
< 32; i
++) {
748 if (src_index_table
[i
] == uncompacted
) {
758 set_src0_index(const struct brw_device_info
*devinfo
,
759 brw_compact_inst
*dst
, brw_inst
*src
)
762 uint16_t uncompacted
= brw_inst_bits(src
, 88, 77); /* 12b */
764 if (!get_src_index(uncompacted
, &compacted
))
767 brw_compact_inst_set_src0_index(devinfo
, dst
, compacted
);
773 set_src1_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
774 brw_inst
*src
, bool is_immediate
)
779 compacted
= (brw_inst_imm_ud(devinfo
, src
) >> 8) & 0x1f;
781 uint16_t uncompacted
= brw_inst_bits(src
, 120, 109); /* 12b */
783 if (!get_src_index(uncompacted
, &compacted
))
787 brw_compact_inst_set_src1_index(devinfo
, dst
, compacted
);
793 set_3src_control_index(const struct brw_device_info
*devinfo
,
794 brw_compact_inst
*dst
, brw_inst
*src
)
796 assert(devinfo
->gen
>= 8);
798 uint32_t uncompacted
= /* 24b/BDW; 26b/CHV */
799 (brw_inst_bits(src
, 34, 32) << 21) | /* 3b */
800 (brw_inst_bits(src
, 28, 8)); /* 21b */
802 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
803 uncompacted
|= brw_inst_bits(src
, 36, 35) << 24; /* 2b */
805 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_control_index_table
); i
++) {
806 if (gen8_3src_control_index_table
[i
] == uncompacted
) {
807 brw_compact_inst_set_3src_control_index(devinfo
, dst
, i
);
816 set_3src_source_index(const struct brw_device_info
*devinfo
,
817 brw_compact_inst
*dst
, brw_inst
*src
)
819 assert(devinfo
->gen
>= 8);
821 uint64_t uncompacted
= /* 46b/BDW; 49b/CHV */
822 (brw_inst_bits(src
, 83, 83) << 43) | /* 1b */
823 (brw_inst_bits(src
, 114, 107) << 35) | /* 8b */
824 (brw_inst_bits(src
, 93, 86) << 27) | /* 8b */
825 (brw_inst_bits(src
, 72, 65) << 19) | /* 8b */
826 (brw_inst_bits(src
, 55, 37)); /* 19b */
828 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
830 (brw_inst_bits(src
, 126, 125) << 47) | /* 2b */
831 (brw_inst_bits(src
, 105, 104) << 45) | /* 2b */
832 (brw_inst_bits(src
, 84, 84) << 44); /* 1b */
835 (brw_inst_bits(src
, 125, 125) << 45) | /* 1b */
836 (brw_inst_bits(src
, 104, 104) << 44); /* 1b */
839 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_source_index_table
); i
++) {
840 if (gen8_3src_source_index_table
[i
] == uncompacted
) {
841 brw_compact_inst_set_3src_source_index(devinfo
, dst
, i
);
850 has_unmapped_bits(const struct brw_device_info
*devinfo
, brw_inst
*src
)
852 /* EOT can only be mapped on a send if the src1 is an immediate */
853 if ((brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SENDC
||
854 brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SEND
) &&
855 brw_inst_eot(devinfo
, src
))
858 /* Check for instruction bits that don't map to any of the fields of the
859 * compacted instruction. The instruction cannot be compacted if any of
860 * them are set. They overlap with:
861 * - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
862 * - Dst.AddrImm[9] (bit 47 on Gen8)
863 * - Src0.AddrImm[9] (bit 95 on Gen8)
864 * - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
865 * - UIP[31] (bit 95 on Gen8)
867 if (devinfo
->gen
>= 8) {
868 assert(!brw_inst_bits(src
, 7, 7));
869 return brw_inst_bits(src
, 95, 95) ||
870 brw_inst_bits(src
, 47, 47) ||
871 brw_inst_bits(src
, 11, 11);
873 assert(!brw_inst_bits(src
, 7, 7) &&
874 !(devinfo
->gen
< 7 && brw_inst_bits(src
, 90, 90)));
875 return brw_inst_bits(src
, 95, 91) ||
876 brw_inst_bits(src
, 47, 47);
881 has_3src_unmapped_bits(const struct brw_device_info
*devinfo
, brw_inst
*src
)
883 /* Check for three-source instruction bits that don't map to any of the
884 * fields of the compacted instruction. All of them seem to be reserved
887 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
888 assert(!brw_inst_bits(src
, 127, 127) &&
889 !brw_inst_bits(src
, 7, 7));
891 assert(devinfo
->gen
>= 8);
892 assert(!brw_inst_bits(src
, 127, 126) &&
893 !brw_inst_bits(src
, 105, 105) &&
894 !brw_inst_bits(src
, 84, 84) &&
895 !brw_inst_bits(src
, 36, 35) &&
896 !brw_inst_bits(src
, 7, 7));
903 brw_try_compact_3src_instruction(const struct brw_device_info
*devinfo
,
904 brw_compact_inst
*dst
, brw_inst
*src
)
906 assert(devinfo
->gen
>= 8);
908 if (has_3src_unmapped_bits(devinfo
, src
))
911 #define compact(field) \
912 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
916 if (!set_3src_control_index(devinfo
, dst
, src
))
919 if (!set_3src_source_index(devinfo
, dst
, src
))
923 compact(src0_rep_ctrl
);
924 brw_compact_inst_set_3src_cmpt_control(devinfo
, dst
, true);
925 compact(debug_control
);
927 compact(src1_rep_ctrl
);
928 compact(src2_rep_ctrl
);
929 compact(src0_reg_nr
);
930 compact(src1_reg_nr
);
931 compact(src2_reg_nr
);
932 compact(src0_subreg_nr
);
933 compact(src1_subreg_nr
);
934 compact(src2_subreg_nr
);
941 /* Compacted instructions have 12-bits for immediate sources, and a 13th bit
942 * that's replicated through the high 20 bits.
944 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
945 * of packed vectors as compactable immediates.
948 is_compactable_immediate(unsigned imm
)
950 /* We get the low 12 bits as-is. */
953 /* We get one bit replicated through the top 20 bits. */
954 return imm
== 0 || imm
== 0xfffff000;
957 /* Returns whether an opcode takes three sources. */
961 return opcode_descs
[op
].nsrc
== 3;
965 * Tries to compact instruction src into dst.
967 * It doesn't modify dst unless src is compactable, which is relied on by
968 * brw_compact_instructions().
971 brw_try_compact_instruction(const struct brw_device_info
*devinfo
,
972 brw_compact_inst
*dst
, brw_inst
*src
)
974 brw_compact_inst temp
;
976 assert(brw_inst_cmpt_control(devinfo
, src
) == 0);
978 if (is_3src(brw_inst_opcode(devinfo
, src
))) {
979 if (devinfo
->gen
>= 8) {
980 memset(&temp
, 0, sizeof(temp
));
981 if (brw_try_compact_3src_instruction(devinfo
, &temp
, src
)) {
993 brw_inst_src0_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
||
994 brw_inst_src1_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
;
997 !is_compactable_immediate(brw_inst_imm_ud(devinfo
, src
)))) {
1001 if (has_unmapped_bits(devinfo
, src
))
1004 memset(&temp
, 0, sizeof(temp
));
1006 #define compact(field) \
1007 brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
1010 compact(debug_control
);
1012 if (!set_control_index(devinfo
, &temp
, src
))
1014 if (!set_datatype_index(devinfo
, &temp
, src
))
1016 if (!set_subreg_index(devinfo
, &temp
, src
, is_immediate
))
1019 if (devinfo
->gen
>= 6) {
1020 compact(acc_wr_control
);
1022 compact(mask_control_ex
);
1025 compact(cond_modifier
);
1027 if (devinfo
->gen
<= 6)
1028 compact(flag_subreg_nr
);
1030 brw_compact_inst_set_cmpt_control(devinfo
, &temp
, true);
1032 if (!set_src0_index(devinfo
, &temp
, src
))
1034 if (!set_src1_index(devinfo
, &temp
, src
, is_immediate
))
1037 brw_compact_inst_set_dst_reg_nr(devinfo
, &temp
,
1038 brw_inst_dst_da_reg_nr(devinfo
, src
));
1039 brw_compact_inst_set_src0_reg_nr(devinfo
, &temp
,
1040 brw_inst_src0_da_reg_nr(devinfo
, src
));
1043 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1044 brw_inst_imm_ud(devinfo
, src
) & 0xff);
1046 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1047 brw_inst_src1_da_reg_nr(devinfo
, src
));
1058 set_uncompacted_control(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1059 brw_compact_inst
*src
)
1061 uint32_t uncompacted
=
1062 control_index_table
[brw_compact_inst_control_index(devinfo
, src
)];
1064 if (devinfo
->gen
>= 8) {
1065 brw_inst_set_bits(dst
, 33, 31, (uncompacted
>> 16));
1066 brw_inst_set_bits(dst
, 23, 12, (uncompacted
>> 4) & 0xfff);
1067 brw_inst_set_bits(dst
, 10, 9, (uncompacted
>> 2) & 0x3);
1068 brw_inst_set_bits(dst
, 34, 34, (uncompacted
>> 1) & 0x1);
1069 brw_inst_set_bits(dst
, 8, 8, (uncompacted
>> 0) & 0x1);
1071 brw_inst_set_bits(dst
, 31, 31, (uncompacted
>> 16) & 0x1);
1072 brw_inst_set_bits(dst
, 23, 8, (uncompacted
& 0xffff));
1074 if (devinfo
->gen
== 7)
1075 brw_inst_set_bits(dst
, 90, 89, uncompacted
>> 17);
1080 set_uncompacted_datatype(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1081 brw_compact_inst
*src
)
1083 uint32_t uncompacted
=
1084 datatype_table
[brw_compact_inst_datatype_index(devinfo
, src
)];
1086 if (devinfo
->gen
>= 8) {
1087 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 18));
1088 brw_inst_set_bits(dst
, 94, 89, (uncompacted
>> 12) & 0x3f);
1089 brw_inst_set_bits(dst
, 46, 35, (uncompacted
>> 0) & 0xfff);
1091 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 15));
1092 brw_inst_set_bits(dst
, 46, 32, (uncompacted
& 0x7fff));
1097 set_uncompacted_subreg(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1098 brw_compact_inst
*src
)
1100 uint16_t uncompacted
=
1101 subreg_table
[brw_compact_inst_subreg_index(devinfo
, src
)];
1103 brw_inst_set_bits(dst
, 100, 96, (uncompacted
>> 10));
1104 brw_inst_set_bits(dst
, 68, 64, (uncompacted
>> 5) & 0x1f);
1105 brw_inst_set_bits(dst
, 52, 48, (uncompacted
>> 0) & 0x1f);
1109 set_uncompacted_src0(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1110 brw_compact_inst
*src
)
1112 uint32_t compacted
= brw_compact_inst_src0_index(devinfo
, src
);
1113 uint16_t uncompacted
= src_index_table
[compacted
];
1115 brw_inst_set_bits(dst
, 88, 77, uncompacted
);
1119 set_uncompacted_src1(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1120 brw_compact_inst
*src
, bool is_immediate
)
1123 signed high5
= brw_compact_inst_src1_index(devinfo
, src
);
1124 /* Replicate top bit of src1_index into high 20 bits of the immediate. */
1125 brw_inst_set_imm_ud(devinfo
, dst
, (high5
<< 27) >> 19);
1127 uint16_t uncompacted
=
1128 src_index_table
[brw_compact_inst_src1_index(devinfo
, src
)];
1130 brw_inst_set_bits(dst
, 120, 109, uncompacted
);
1135 set_uncompacted_3src_control_index(const struct brw_device_info
*devinfo
,
1136 brw_inst
*dst
, brw_compact_inst
*src
)
1138 assert(devinfo
->gen
>= 8);
1140 uint32_t compacted
= brw_compact_inst_3src_control_index(devinfo
, src
);
1141 uint32_t uncompacted
= gen8_3src_control_index_table
[compacted
];
1143 brw_inst_set_bits(dst
, 34, 32, (uncompacted
>> 21) & 0x7);
1144 brw_inst_set_bits(dst
, 28, 8, (uncompacted
>> 0) & 0x1fffff);
1146 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
1147 brw_inst_set_bits(dst
, 36, 35, (uncompacted
>> 24) & 0x3);
1151 set_uncompacted_3src_source_index(const struct brw_device_info
*devinfo
,
1152 brw_inst
*dst
, brw_compact_inst
*src
)
1154 assert(devinfo
->gen
>= 8);
1156 uint32_t compacted
= brw_compact_inst_3src_source_index(devinfo
, src
);
1157 uint64_t uncompacted
= gen8_3src_source_index_table
[compacted
];
1159 brw_inst_set_bits(dst
, 83, 83, (uncompacted
>> 43) & 0x1);
1160 brw_inst_set_bits(dst
, 114, 107, (uncompacted
>> 35) & 0xff);
1161 brw_inst_set_bits(dst
, 93, 86, (uncompacted
>> 27) & 0xff);
1162 brw_inst_set_bits(dst
, 72, 65, (uncompacted
>> 19) & 0xff);
1163 brw_inst_set_bits(dst
, 55, 37, (uncompacted
>> 0) & 0x7ffff);
1165 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
1166 brw_inst_set_bits(dst
, 126, 125, (uncompacted
>> 47) & 0x3);
1167 brw_inst_set_bits(dst
, 105, 104, (uncompacted
>> 45) & 0x3);
1168 brw_inst_set_bits(dst
, 84, 84, (uncompacted
>> 44) & 0x1);
1170 brw_inst_set_bits(dst
, 125, 125, (uncompacted
>> 45) & 0x1);
1171 brw_inst_set_bits(dst
, 104, 104, (uncompacted
>> 44) & 0x1);
1176 brw_uncompact_3src_instruction(const struct brw_device_info
*devinfo
,
1177 brw_inst
*dst
, brw_compact_inst
*src
)
1179 assert(devinfo
->gen
>= 8);
1181 #define uncompact(field) \
1182 brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1186 set_uncompacted_3src_control_index(devinfo
, dst
, src
);
1187 set_uncompacted_3src_source_index(devinfo
, dst
, src
);
1189 uncompact(dst_reg_nr
);
1190 uncompact(src0_rep_ctrl
);
1191 brw_inst_set_3src_cmpt_control(devinfo
, dst
, false);
1192 uncompact(debug_control
);
1193 uncompact(saturate
);
1194 uncompact(src1_rep_ctrl
);
1195 uncompact(src2_rep_ctrl
);
1196 uncompact(src0_reg_nr
);
1197 uncompact(src1_reg_nr
);
1198 uncompact(src2_reg_nr
);
1199 uncompact(src0_subreg_nr
);
1200 uncompact(src1_subreg_nr
);
1201 uncompact(src2_subreg_nr
);
1207 brw_uncompact_instruction(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1208 brw_compact_inst
*src
)
1210 memset(dst
, 0, sizeof(*dst
));
1212 if (devinfo
->gen
>= 8 && is_3src(brw_compact_inst_3src_opcode(devinfo
, src
))) {
1213 brw_uncompact_3src_instruction(devinfo
, dst
, src
);
1217 #define uncompact(field) \
1218 brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
1221 uncompact(debug_control
);
1223 set_uncompacted_control(devinfo
, dst
, src
);
1224 set_uncompacted_datatype(devinfo
, dst
, src
);
1226 /* src0/1 register file fields are in the datatype table. */
1227 bool is_immediate
= brw_inst_src0_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
||
1228 brw_inst_src1_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
;
1230 set_uncompacted_subreg(devinfo
, dst
, src
);
1232 if (devinfo
->gen
>= 6) {
1233 uncompact(acc_wr_control
);
1235 uncompact(mask_control_ex
);
1238 uncompact(cond_modifier
);
1240 if (devinfo
->gen
<= 6)
1241 uncompact(flag_subreg_nr
);
1243 set_uncompacted_src0(devinfo
, dst
, src
);
1244 set_uncompacted_src1(devinfo
, dst
, src
, is_immediate
);
1246 brw_inst_set_dst_da_reg_nr(devinfo
, dst
,
1247 brw_compact_inst_dst_reg_nr(devinfo
, src
));
1248 brw_inst_set_src0_da_reg_nr(devinfo
, dst
,
1249 brw_compact_inst_src0_reg_nr(devinfo
, src
));
1252 brw_inst_set_imm_ud(devinfo
, dst
,
1253 brw_inst_imm_ud(devinfo
, dst
) |
1254 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1256 brw_inst_set_src1_da_reg_nr(devinfo
, dst
,
1257 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1263 void brw_debug_compact_uncompact(const struct brw_device_info
*devinfo
,
1265 brw_inst
*uncompacted
)
1267 fprintf(stderr
, "Instruction compact/uncompact changed (gen%d):\n",
1270 fprintf(stderr
, " before: ");
1271 brw_disassemble_inst(stderr
, devinfo
, orig
, true);
1273 fprintf(stderr
, " after: ");
1274 brw_disassemble_inst(stderr
, devinfo
, uncompacted
, false);
1276 uint32_t *before_bits
= (uint32_t *)orig
;
1277 uint32_t *after_bits
= (uint32_t *)uncompacted
;
1278 fprintf(stderr
, " changed bits:\n");
1279 for (int i
= 0; i
< 128; i
++) {
1280 uint32_t before
= before_bits
[i
/ 32] & (1 << (i
& 31));
1281 uint32_t after
= after_bits
[i
/ 32] & (1 << (i
& 31));
1283 if (before
!= after
) {
1284 fprintf(stderr
, " bit %d, %s to %s\n", i
,
1285 before
? "set" : "unset",
1286 after
? "set" : "unset");
1292 compacted_between(int old_ip
, int old_target_ip
, int *compacted_counts
)
1294 int this_compacted_count
= compacted_counts
[old_ip
];
1295 int target_compacted_count
= compacted_counts
[old_target_ip
];
1296 return target_compacted_count
- this_compacted_count
;
1300 update_uip_jip(const struct brw_device_info
*devinfo
, brw_inst
*insn
,
1301 int this_old_ip
, int *compacted_counts
)
1303 /* JIP and UIP are in units of:
1304 * - bytes on Gen8+; and
1305 * - compacted instructions on Gen6+.
1307 int shift
= devinfo
->gen
>= 8 ? 3 : 0;
1309 int32_t jip_compacted
= brw_inst_jip(devinfo
, insn
) >> shift
;
1310 jip_compacted
-= compacted_between(this_old_ip
,
1311 this_old_ip
+ (jip_compacted
/ 2),
1313 brw_inst_set_jip(devinfo
, insn
, jip_compacted
<< shift
);
1315 if (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ENDIF
||
1316 brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_WHILE
||
1317 (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ELSE
&& devinfo
->gen
<= 7))
1320 int32_t uip_compacted
= brw_inst_uip(devinfo
, insn
) >> shift
;
1321 uip_compacted
-= compacted_between(this_old_ip
,
1322 this_old_ip
+ (uip_compacted
/ 2),
1324 brw_inst_set_uip(devinfo
, insn
, uip_compacted
<< shift
);
1328 update_gen4_jump_count(const struct brw_device_info
*devinfo
, brw_inst
*insn
,
1329 int this_old_ip
, int *compacted_counts
)
1331 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
);
1333 /* Jump Count is in units of:
1334 * - uncompacted instructions on G45; and
1335 * - compacted instructions on Gen5.
1337 int shift
= devinfo
->is_g4x
? 1 : 0;
1339 int jump_count_compacted
= brw_inst_gen4_jump_count(devinfo
, insn
) << shift
;
1341 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1343 int this_compacted_count
= compacted_counts
[this_old_ip
];
1344 int target_compacted_count
= compacted_counts
[target_old_ip
];
1346 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1347 brw_inst_set_gen4_jump_count(devinfo
, insn
, jump_count_compacted
>> shift
);
1351 brw_init_compaction_tables(const struct brw_device_info
*devinfo
)
1353 static bool initialized
;
1354 if (initialized
|| p_atomic_cmpxchg(&initialized
, false, true) != false)
1357 assert(g45_control_index_table
[ARRAY_SIZE(g45_control_index_table
) - 1] != 0);
1358 assert(g45_datatype_table
[ARRAY_SIZE(g45_datatype_table
) - 1] != 0);
1359 assert(g45_subreg_table
[ARRAY_SIZE(g45_subreg_table
) - 1] != 0);
1360 assert(g45_src_index_table
[ARRAY_SIZE(g45_src_index_table
) - 1] != 0);
1361 assert(gen6_control_index_table
[ARRAY_SIZE(gen6_control_index_table
) - 1] != 0);
1362 assert(gen6_datatype_table
[ARRAY_SIZE(gen6_datatype_table
) - 1] != 0);
1363 assert(gen6_subreg_table
[ARRAY_SIZE(gen6_subreg_table
) - 1] != 0);
1364 assert(gen6_src_index_table
[ARRAY_SIZE(gen6_src_index_table
) - 1] != 0);
1365 assert(gen7_control_index_table
[ARRAY_SIZE(gen7_control_index_table
) - 1] != 0);
1366 assert(gen7_datatype_table
[ARRAY_SIZE(gen7_datatype_table
) - 1] != 0);
1367 assert(gen7_subreg_table
[ARRAY_SIZE(gen7_subreg_table
) - 1] != 0);
1368 assert(gen7_src_index_table
[ARRAY_SIZE(gen7_src_index_table
) - 1] != 0);
1369 assert(gen8_control_index_table
[ARRAY_SIZE(gen8_control_index_table
) - 1] != 0);
1370 assert(gen8_datatype_table
[ARRAY_SIZE(gen8_datatype_table
) - 1] != 0);
1371 assert(gen8_subreg_table
[ARRAY_SIZE(gen8_subreg_table
) - 1] != 0);
1372 assert(gen8_src_index_table
[ARRAY_SIZE(gen8_src_index_table
) - 1] != 0);
1374 switch (devinfo
->gen
) {
1377 control_index_table
= gen8_control_index_table
;
1378 datatype_table
= gen8_datatype_table
;
1379 subreg_table
= gen8_subreg_table
;
1380 src_index_table
= gen8_src_index_table
;
1383 control_index_table
= gen7_control_index_table
;
1384 datatype_table
= gen7_datatype_table
;
1385 subreg_table
= gen7_subreg_table
;
1386 src_index_table
= gen7_src_index_table
;
1389 control_index_table
= gen6_control_index_table
;
1390 datatype_table
= gen6_datatype_table
;
1391 subreg_table
= gen6_subreg_table
;
1392 src_index_table
= gen6_src_index_table
;
1396 control_index_table
= g45_control_index_table
;
1397 datatype_table
= g45_datatype_table
;
1398 subreg_table
= g45_subreg_table
;
1399 src_index_table
= g45_src_index_table
;
1402 unreachable("unknown generation");
1407 brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1408 int num_annotations
, struct annotation
*annotation
)
1410 if (unlikely(INTEL_DEBUG
& DEBUG_NO_COMPACTION
))
1413 const struct brw_device_info
*devinfo
= p
->devinfo
;
1414 void *store
= p
->store
+ start_offset
/ 16;
1415 /* For an instruction at byte offset 16*i before compaction, this is the
1416 * number of compacted instructions minus the number of padding NOP/NENOPs
1419 int compacted_counts
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_inst
)];
1420 /* For an instruction at byte offset 8*i after compaction, this was its IP
1421 * (in 16-byte units) before compaction.
1423 int old_ip
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_compact_inst
)];
1425 if (devinfo
->gen
== 4 && !devinfo
->is_g4x
)
1429 int compacted_count
= 0;
1430 for (int src_offset
= 0; src_offset
< p
->next_insn_offset
- start_offset
;
1431 src_offset
+= sizeof(brw_inst
)) {
1432 brw_inst
*src
= store
+ src_offset
;
1433 void *dst
= store
+ offset
;
1435 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1436 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1438 brw_inst saved
= *src
;
1440 if (brw_try_compact_instruction(devinfo
, dst
, src
)) {
1444 brw_inst uncompacted
;
1445 brw_uncompact_instruction(devinfo
, &uncompacted
, dst
);
1446 if (memcmp(&saved
, &uncompacted
, sizeof(uncompacted
))) {
1447 brw_debug_compact_uncompact(devinfo
, &saved
, &uncompacted
);
1451 offset
+= sizeof(brw_compact_inst
);
1453 /* All uncompacted instructions need to be aligned on G45. */
1454 if ((offset
& sizeof(brw_compact_inst
)) != 0 && devinfo
->is_g4x
){
1455 brw_compact_inst
*align
= store
+ offset
;
1456 memset(align
, 0, sizeof(*align
));
1457 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NENOP
);
1458 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1459 offset
+= sizeof(brw_compact_inst
);
1461 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1462 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1464 dst
= store
+ offset
;
1467 /* If we didn't compact this intruction, we need to move it down into
1470 if (offset
!= src_offset
) {
1471 memmove(dst
, src
, sizeof(brw_inst
));
1473 offset
+= sizeof(brw_inst
);
1477 /* Fix up control flow offsets. */
1478 p
->next_insn_offset
= start_offset
+ offset
;
1479 for (offset
= 0; offset
< p
->next_insn_offset
- start_offset
;
1480 offset
= next_offset(devinfo
, store
, offset
)) {
1481 brw_inst
*insn
= store
+ offset
;
1482 int this_old_ip
= old_ip
[offset
/ sizeof(brw_compact_inst
)];
1483 int this_compacted_count
= compacted_counts
[this_old_ip
];
1485 switch (brw_inst_opcode(devinfo
, insn
)) {
1486 case BRW_OPCODE_BREAK
:
1487 case BRW_OPCODE_CONTINUE
:
1488 case BRW_OPCODE_HALT
:
1489 if (devinfo
->gen
>= 6) {
1490 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1492 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1498 case BRW_OPCODE_IFF
:
1499 case BRW_OPCODE_ELSE
:
1500 case BRW_OPCODE_ENDIF
:
1501 case BRW_OPCODE_WHILE
:
1502 if (devinfo
->gen
>= 7) {
1503 if (brw_inst_cmpt_control(devinfo
, insn
)) {
1504 brw_inst uncompacted
;
1505 brw_uncompact_instruction(devinfo
, &uncompacted
,
1506 (brw_compact_inst
*)insn
);
1508 update_uip_jip(devinfo
, &uncompacted
, this_old_ip
,
1511 bool ret
= brw_try_compact_instruction(devinfo
,
1512 (brw_compact_inst
*)insn
,
1514 assert(ret
); (void)ret
;
1516 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1518 } else if (devinfo
->gen
== 6) {
1519 assert(!brw_inst_cmpt_control(devinfo
, insn
));
1521 /* Jump Count is in units of compacted instructions on Gen6. */
1522 int jump_count_compacted
= brw_inst_gen6_jump_count(devinfo
, insn
);
1524 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1525 int target_compacted_count
= compacted_counts
[target_old_ip
];
1526 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1527 brw_inst_set_gen6_jump_count(devinfo
, insn
, jump_count_compacted
);
1529 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1534 case BRW_OPCODE_ADD
:
1535 /* Add instructions modifying the IP register use an immediate src1,
1536 * and Gens that use this cannot compact instructions with immediate
1539 if (brw_inst_cmpt_control(devinfo
, insn
))
1542 if (brw_inst_dst_reg_file(devinfo
, insn
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
1543 brw_inst_dst_da_reg_nr(devinfo
, insn
) == BRW_ARF_IP
) {
1544 assert(brw_inst_src1_reg_file(devinfo
, insn
) == BRW_IMMEDIATE_VALUE
);
1547 int jump_compacted
= brw_inst_imm_d(devinfo
, insn
) >> shift
;
1549 int target_old_ip
= this_old_ip
+ (jump_compacted
/ 2);
1550 int target_compacted_count
= compacted_counts
[target_old_ip
];
1551 jump_compacted
-= (target_compacted_count
- this_compacted_count
);
1552 brw_inst_set_imm_ud(devinfo
, insn
, jump_compacted
<< shift
);
1558 /* p->nr_insn is counting the number of uncompacted instructions still, so
1559 * divide. We do want to be sure there's a valid instruction in any
1560 * alignment padding, so that the next compression pass (for the FS 8/16
1561 * compile passes) parses correctly.
1563 if (p
->next_insn_offset
& sizeof(brw_compact_inst
)) {
1564 brw_compact_inst
*align
= store
+ offset
;
1565 memset(align
, 0, sizeof(*align
));
1566 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NOP
);
1567 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1568 p
->next_insn_offset
+= sizeof(brw_compact_inst
);
1570 p
->nr_insn
= p
->next_insn_offset
/ sizeof(brw_inst
);
1572 /* Update the instruction offsets for each annotation. */
1574 for (int offset
= 0, i
= 0; i
< num_annotations
; i
++) {
1575 while (start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1576 sizeof(brw_inst
) != annotation
[i
].offset
) {
1577 assert(start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1578 sizeof(brw_inst
) < annotation
[i
].offset
);
1579 offset
= next_offset(devinfo
, store
, offset
);
1582 annotation
[i
].offset
= start_offset
+ offset
;
1584 offset
= next_offset(devinfo
, store
, offset
);
1587 annotation
[num_annotations
].offset
= p
->next_insn_offset
;