2 * Copyright © 2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 /** @file brw_eu_compact.c
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that. The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
40 * Instruction compaction capabilities vary subtly by generation.
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
68 * else JIP (plus UIP on BDW+)
70 * while JIP (must be negative)
72 * Gen 8 adds support for compacting 3-src instructions.
75 #include "brw_context.h"
77 #include "intel_asm_annotation.h"
78 #include "util/u_atomic.h" /* for p_atomic_cmpxchg */
80 static const uint32_t g45_control_index_table
[32] = {
115 static const uint32_t g45_datatype_table
[32] = {
116 0b001000000000100001,
117 0b001011010110101101,
118 0b001000001000110001,
119 0b001111011110111101,
120 0b001011010110101100,
121 0b001000000110101101,
122 0b001000000000100000,
123 0b010100010110110001,
124 0b001100011000101101,
125 0b001000000000100010,
126 0b001000001000110110,
127 0b010000001000110001,
128 0b001000001000110010,
129 0b011000001000110010,
130 0b001111011110111100,
131 0b001000000100101000,
132 0b010100011000110001,
133 0b001010010100101001,
134 0b001000001000101001,
135 0b010000001000110110,
136 0b101000001000110001,
137 0b001011011000101101,
138 0b001000000100001001,
139 0b001011011000101100,
140 0b110100011000110001,
141 0b001000001110111101,
142 0b110000001000110001,
143 0b011000000100101010,
144 0b101000001000101001,
145 0b001011010110001100,
146 0b001000000110100001,
150 static const uint16_t g45_subreg_table
[32] = {
185 static const uint16_t g45_src_index_table
[32] = {
220 static const uint32_t gen6_control_index_table
[32] = {
255 static const uint32_t gen6_datatype_table
[32] = {
256 0b001001110000000000,
257 0b001000110000100000,
258 0b001001110000000001,
259 0b001000000001100000,
260 0b001010110100101001,
261 0b001000000110101101,
262 0b001100011000101100,
263 0b001011110110101101,
264 0b001000000111101100,
265 0b001000000001100001,
266 0b001000110010100101,
267 0b001000000001000001,
268 0b001000001000110001,
269 0b001000001000101001,
270 0b001000000000100000,
271 0b001000001000110010,
272 0b001010010100101001,
273 0b001011010010100101,
274 0b001000000110100101,
275 0b001100011000101001,
276 0b001011011000101100,
277 0b001011010110100101,
278 0b001011110110100101,
279 0b001111011110111101,
280 0b001111011110111100,
281 0b001111011110111101,
282 0b001111011110011101,
283 0b001111011110111110,
284 0b001000000000100001,
285 0b001000000000100010,
286 0b001001111111011101,
287 0b001000001110111110,
290 static const uint16_t gen6_subreg_table
[32] = {
325 static const uint16_t gen6_src_index_table
[32] = {
360 static const uint32_t gen7_control_index_table
[32] = {
361 0b0000000000000000010,
362 0b0000100000000000000,
363 0b0000100000000000001,
364 0b0000100000000000010,
365 0b0000100000000000011,
366 0b0000100000000000100,
367 0b0000100000000000101,
368 0b0000100000000000111,
369 0b0000100000000001000,
370 0b0000100000000001001,
371 0b0000100000000001101,
372 0b0000110000000000000,
373 0b0000110000000000001,
374 0b0000110000000000010,
375 0b0000110000000000011,
376 0b0000110000000000100,
377 0b0000110000000000101,
378 0b0000110000000000111,
379 0b0000110000000001001,
380 0b0000110000000001101,
381 0b0000110000000010000,
382 0b0000110000100000000,
383 0b0001000000000000000,
384 0b0001000000000000010,
385 0b0001000000000000100,
386 0b0001000000100000000,
387 0b0010110000000000000,
388 0b0010110000000010000,
389 0b0011000000000000000,
390 0b0011000000100000000,
391 0b0101000000000000000,
392 0b0101000000100000000
395 static const uint32_t gen7_datatype_table
[32] = {
396 0b001000000000000001,
397 0b001000000000100000,
398 0b001000000000100001,
399 0b001000000001100001,
400 0b001000000010111101,
401 0b001000001011111101,
402 0b001000001110100001,
403 0b001000001110100101,
404 0b001000001110111101,
405 0b001000010000100001,
406 0b001000110000100000,
407 0b001000110000100001,
408 0b001001010010100101,
409 0b001001110010100100,
410 0b001001110010100101,
411 0b001111001110111101,
412 0b001111011110011101,
413 0b001111011110111100,
414 0b001111011110111101,
415 0b001111111110111100,
416 0b000000001000001100,
417 0b001000000000111101,
418 0b001000000010100101,
419 0b001000010000100000,
420 0b001001010010100100,
421 0b001001110010000100,
422 0b001010010100001001,
423 0b001101111110111101,
424 0b001111111110111101,
425 0b001011110110101100,
426 0b001010010100101000,
430 static const uint16_t gen7_subreg_table
[32] = {
465 static const uint16_t gen7_src_index_table
[32] = {
500 static const uint32_t gen8_control_index_table
[32] = {
501 0b0000000000000000010,
502 0b0000100000000000000,
503 0b0000100000000000001,
504 0b0000100000000000010,
505 0b0000100000000000011,
506 0b0000100000000000100,
507 0b0000100000000000101,
508 0b0000100000000000111,
509 0b0000100000000001000,
510 0b0000100000000001001,
511 0b0000100000000001101,
512 0b0000110000000000000,
513 0b0000110000000000001,
514 0b0000110000000000010,
515 0b0000110000000000011,
516 0b0000110000000000100,
517 0b0000110000000000101,
518 0b0000110000000000111,
519 0b0000110000000001001,
520 0b0000110000000001101,
521 0b0000110000000010000,
522 0b0000110000100000000,
523 0b0001000000000000000,
524 0b0001000000000000010,
525 0b0001000000000000100,
526 0b0001000000100000000,
527 0b0010110000000000000,
528 0b0010110000000010000,
529 0b0011000000000000000,
530 0b0011000000100000000,
531 0b0101000000000000000,
532 0b0101000000100000000
535 static const uint32_t gen8_datatype_table
[32] = {
536 0b001000000000000000001,
537 0b001000000000001000000,
538 0b001000000000001000001,
539 0b001000000000011000001,
540 0b001000000000101011101,
541 0b001000000010111011101,
542 0b001000000011101000001,
543 0b001000000011101000101,
544 0b001000000011101011101,
545 0b001000001000001000001,
546 0b001000011000001000000,
547 0b001000011000001000001,
548 0b001000101000101000101,
549 0b001000111000101000100,
550 0b001000111000101000101,
551 0b001011100011101011101,
552 0b001011101011100011101,
553 0b001011101011101011100,
554 0b001011101011101011101,
555 0b001011111011101011100,
556 0b000000000010000001100,
557 0b001000000000001011101,
558 0b001000000000101000101,
559 0b001000001000001000000,
560 0b001000101000101000100,
561 0b001000111000100000100,
562 0b001001001001000001001,
563 0b001010111011101011101,
564 0b001011111011101011101,
565 0b001001111001101001100,
566 0b001001001001001001000,
567 0b001001011001001001000
570 static const uint16_t gen8_subreg_table
[32] = {
605 static const uint16_t gen8_src_index_table
[32] = {
640 /* This is actually the control index table for Cherryview (26 bits), but the
641 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
644 * The low 24 bits have the same mappings on both hardware.
646 static const uint32_t gen8_3src_control_index_table
[4] = {
647 0b00100000000110000000000001,
648 0b00000000000110000000000001,
649 0b00000000001000000000000001,
650 0b00000000001000000000100001
653 /* This is actually the control index table for Cherryview (49 bits), but the
654 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
657 * The low 44 bits have the same mappings on both hardware, and since the high
658 * three bits on Broadwell are zero, we can reuse Cherryview's table.
660 static const uint64_t gen8_3src_source_index_table
[4] = {
661 0b0000001110010011100100111001000001111000000000000,
662 0b0000001110010011100100111001000001111000000000010,
663 0b0000001110010011100100111001000001111000000001000,
664 0b0000001110010011100100111001000001111000000100000
667 static const uint32_t *control_index_table
;
668 static const uint32_t *datatype_table
;
669 static const uint16_t *subreg_table
;
670 static const uint16_t *src_index_table
;
673 set_control_index(const struct brw_device_info
*devinfo
,
674 brw_compact_inst
*dst
, brw_inst
*src
)
676 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 17b/G45; 19b/IVB+ */
677 ? (brw_inst_bits(src
, 33, 31) << 16) | /* 3b */
678 (brw_inst_bits(src
, 23, 12) << 4) | /* 12b */
679 (brw_inst_bits(src
, 10, 9) << 2) | /* 2b */
680 (brw_inst_bits(src
, 34, 34) << 1) | /* 1b */
681 (brw_inst_bits(src
, 8, 8)) /* 1b */
682 : (brw_inst_bits(src
, 31, 31) << 16) | /* 1b */
683 (brw_inst_bits(src
, 23, 8)); /* 16b */
685 /* On gen7, the flag register and subregister numbers are integrated into
688 if (devinfo
->gen
== 7)
689 uncompacted
|= brw_inst_bits(src
, 90, 89) << 17; /* 2b */
691 for (int i
= 0; i
< 32; i
++) {
692 if (control_index_table
[i
] == uncompacted
) {
693 brw_compact_inst_set_control_index(dst
, i
);
702 set_datatype_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
705 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 18b/G45+; 21b/BDW+ */
706 ? (brw_inst_bits(src
, 63, 61) << 18) | /* 3b */
707 (brw_inst_bits(src
, 94, 89) << 12) | /* 6b */
708 (brw_inst_bits(src
, 46, 35)) /* 12b */
709 : (brw_inst_bits(src
, 63, 61) << 15) | /* 3b */
710 (brw_inst_bits(src
, 46, 32)); /* 15b */
712 for (int i
= 0; i
< 32; i
++) {
713 if (datatype_table
[i
] == uncompacted
) {
714 brw_compact_inst_set_datatype_index(dst
, i
);
723 set_subreg_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
724 brw_inst
*src
, bool is_immediate
)
726 uint16_t uncompacted
= /* 15b */
727 (brw_inst_bits(src
, 52, 48) << 0) | /* 5b */
728 (brw_inst_bits(src
, 68, 64) << 5); /* 5b */
731 uncompacted
|= brw_inst_bits(src
, 100, 96) << 10; /* 5b */
733 for (int i
= 0; i
< 32; i
++) {
734 if (subreg_table
[i
] == uncompacted
) {
735 brw_compact_inst_set_subreg_index(dst
, i
);
744 get_src_index(uint16_t uncompacted
,
747 for (int i
= 0; i
< 32; i
++) {
748 if (src_index_table
[i
] == uncompacted
) {
758 set_src0_index(const struct brw_device_info
*devinfo
,
759 brw_compact_inst
*dst
, brw_inst
*src
)
762 uint16_t uncompacted
= brw_inst_bits(src
, 88, 77); /* 12b */
764 if (!get_src_index(uncompacted
, &compacted
))
767 brw_compact_inst_set_src0_index(dst
, compacted
);
773 set_src1_index(const struct brw_device_info
*devinfo
, brw_compact_inst
*dst
,
774 brw_inst
*src
, bool is_immediate
)
779 compacted
= (brw_inst_imm_ud(devinfo
, src
) >> 8) & 0x1f;
781 uint16_t uncompacted
= brw_inst_bits(src
, 120, 109); /* 12b */
783 if (!get_src_index(uncompacted
, &compacted
))
787 brw_compact_inst_set_src1_index(dst
, compacted
);
793 set_3src_control_index(const struct brw_device_info
*devinfo
,
794 brw_compact_inst
*dst
, brw_inst
*src
)
796 assert(devinfo
->gen
>= 8);
798 uint32_t uncompacted
= /* 24b/BDW; 26b/CHV */
799 (brw_inst_bits(src
, 34, 32) << 21) | /* 3b */
800 (brw_inst_bits(src
, 28, 8)); /* 21b */
802 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
803 uncompacted
|= brw_inst_bits(src
, 36, 35) << 24; /* 2b */
805 for (int i
= 0; i
< ARRAY_SIZE(gen8_3src_control_index_table
); i
++) {
806 if (gen8_3src_control_index_table
[i
] == uncompacted
) {
807 brw_compact_inst_set_3src_control_index(dst
, i
);
816 set_3src_source_index(const struct brw_device_info
*devinfo
,
817 brw_compact_inst
*dst
, brw_inst
*src
)
819 assert(devinfo
->gen
>= 8);
821 uint64_t uncompacted
= /* 46b/BDW; 49b/CHV */
822 (brw_inst_bits(src
, 83, 83) << 43) | /* 1b */
823 (brw_inst_bits(src
, 114, 107) << 35) | /* 8b */
824 (brw_inst_bits(src
, 93, 86) << 27) | /* 8b */
825 (brw_inst_bits(src
, 72, 65) << 19) | /* 8b */
826 (brw_inst_bits(src
, 55, 37)); /* 19b */
828 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
830 (brw_inst_bits(src
, 126, 125) << 47) | /* 2b */
831 (brw_inst_bits(src
, 105, 104) << 45) | /* 2b */
832 (brw_inst_bits(src
, 84, 84) << 44); /* 1b */
835 (brw_inst_bits(src
, 125, 125) << 45) | /* 1b */
836 (brw_inst_bits(src
, 104, 104) << 44); /* 1b */
839 for (int i
= 0; i
< ARRAY_SIZE(gen8_3src_source_index_table
); i
++) {
840 if (gen8_3src_source_index_table
[i
] == uncompacted
) {
841 brw_compact_inst_set_3src_source_index(dst
, i
);
850 has_unmapped_bits(const struct brw_device_info
*devinfo
, brw_inst
*src
)
852 /* Check for instruction bits that don't map to any of the fields of the
853 * compacted instruction. The instruction cannot be compacted if any of
854 * them are set. They overlap with:
855 * - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
856 * - Dst.AddrImm[9] (bit 47 on Gen8)
857 * - Src0.AddrImm[9] (bit 95 on Gen8)
858 * - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
859 * - UIP[31] (bit 95 on Gen8)
861 if (devinfo
->gen
>= 8) {
862 assert(!brw_inst_bits(src
, 7, 7));
863 return brw_inst_bits(src
, 95, 95) ||
864 brw_inst_bits(src
, 47, 47) ||
865 brw_inst_bits(src
, 11, 11);
867 assert(!brw_inst_bits(src
, 7, 7) &&
868 !(devinfo
->gen
< 7 && brw_inst_bits(src
, 90, 90)));
869 return brw_inst_bits(src
, 95, 91) ||
870 brw_inst_bits(src
, 47, 47);
875 has_3src_unmapped_bits(const struct brw_device_info
*devinfo
, brw_inst
*src
)
877 /* Check for three-source instruction bits that don't map to any of the
878 * fields of the compacted instruction. All of them seem to be reserved
881 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
882 assert(!brw_inst_bits(src
, 127, 127) &&
883 !brw_inst_bits(src
, 7, 7));
885 assert(devinfo
->gen
>= 8);
886 assert(!brw_inst_bits(src
, 127, 126) &&
887 !brw_inst_bits(src
, 105, 105) &&
888 !brw_inst_bits(src
, 84, 84) &&
889 !brw_inst_bits(src
, 36, 35) &&
890 !brw_inst_bits(src
, 7, 7));
897 brw_try_compact_3src_instruction(const struct brw_device_info
*devinfo
,
898 brw_compact_inst
*dst
, brw_inst
*src
)
900 assert(devinfo
->gen
>= 8);
902 if (has_3src_unmapped_bits(devinfo
, src
))
905 #define compact(field) \
906 brw_compact_inst_set_3src_##field(dst, brw_inst_3src_##field(devinfo, src))
910 if (!set_3src_control_index(devinfo
, dst
, src
))
913 if (!set_3src_source_index(devinfo
, dst
, src
))
917 compact(src0_rep_ctrl
);
918 brw_compact_inst_set_3src_cmpt_control(dst
, true);
919 compact(debug_control
);
921 compact(src1_rep_ctrl
);
922 compact(src2_rep_ctrl
);
923 compact(src0_reg_nr
);
924 compact(src1_reg_nr
);
925 compact(src2_reg_nr
);
926 compact(src0_subreg_nr
);
927 compact(src1_subreg_nr
);
928 compact(src2_subreg_nr
);
935 /* Compacted instructions have 12-bits for immediate sources, and a 13th bit
936 * that's replicated through the high 20 bits.
938 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
939 * of packed vectors as compactable immediates.
942 is_compactable_immediate(unsigned imm
)
944 /* We get the low 12 bits as-is. */
947 /* We get one bit replicated through the top 20 bits. */
948 return imm
== 0 || imm
== 0xfffff000;
951 /* Returns whether an opcode takes three sources. */
955 return opcode_descs
[op
].nsrc
== 3;
959 * Tries to compact instruction src into dst.
961 * It doesn't modify dst unless src is compactable, which is relied on by
962 * brw_compact_instructions().
965 brw_try_compact_instruction(const struct brw_device_info
*devinfo
,
966 brw_compact_inst
*dst
, brw_inst
*src
)
968 brw_compact_inst temp
;
970 assert(brw_inst_cmpt_control(devinfo
, src
) == 0);
972 if (is_3src(brw_inst_opcode(devinfo
, src
))) {
973 if (devinfo
->gen
>= 8) {
974 memset(&temp
, 0, sizeof(temp
));
975 if (brw_try_compact_3src_instruction(devinfo
, &temp
, src
)) {
987 brw_inst_src0_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
||
988 brw_inst_src1_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
;
991 !is_compactable_immediate(brw_inst_imm_ud(devinfo
, src
)))) {
995 if (has_unmapped_bits(devinfo
, src
))
998 memset(&temp
, 0, sizeof(temp
));
1000 brw_compact_inst_set_opcode(&temp
, brw_inst_opcode(devinfo
, src
));
1001 brw_compact_inst_set_debug_control(&temp
, brw_inst_debug_control(devinfo
, src
));
1002 if (!set_control_index(devinfo
, &temp
, src
))
1004 if (!set_datatype_index(devinfo
, &temp
, src
))
1006 if (!set_subreg_index(devinfo
, &temp
, src
, is_immediate
))
1008 brw_compact_inst_set_acc_wr_control(&temp
,
1009 brw_inst_acc_wr_control(devinfo
, src
));
1010 brw_compact_inst_set_cond_modifier(&temp
,
1011 brw_inst_cond_modifier(devinfo
, src
));
1012 if (devinfo
->gen
<= 6)
1013 brw_compact_inst_set_flag_subreg_nr(&temp
,
1014 brw_inst_flag_subreg_nr(devinfo
, src
));
1015 brw_compact_inst_set_cmpt_control(&temp
, true);
1016 if (!set_src0_index(devinfo
, &temp
, src
))
1018 if (!set_src1_index(devinfo
, &temp
, src
, is_immediate
))
1020 brw_compact_inst_set_dst_reg_nr(&temp
, brw_inst_dst_da_reg_nr(devinfo
, src
));
1021 brw_compact_inst_set_src0_reg_nr(&temp
, brw_inst_src0_da_reg_nr(devinfo
, src
));
1023 brw_compact_inst_set_src1_reg_nr(&temp
,
1024 brw_inst_imm_ud(devinfo
, src
) & 0xff);
1026 brw_compact_inst_set_src1_reg_nr(&temp
,
1027 brw_inst_src1_da_reg_nr(devinfo
, src
));
1036 set_uncompacted_control(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1037 brw_compact_inst
*src
)
1039 uint32_t uncompacted
=
1040 control_index_table
[brw_compact_inst_control_index(src
)];
1042 if (devinfo
->gen
>= 8) {
1043 brw_inst_set_bits(dst
, 33, 31, (uncompacted
>> 16));
1044 brw_inst_set_bits(dst
, 23, 12, (uncompacted
>> 4) & 0xfff);
1045 brw_inst_set_bits(dst
, 10, 9, (uncompacted
>> 2) & 0x3);
1046 brw_inst_set_bits(dst
, 34, 34, (uncompacted
>> 1) & 0x1);
1047 brw_inst_set_bits(dst
, 8, 8, (uncompacted
>> 0) & 0x1);
1049 brw_inst_set_bits(dst
, 31, 31, (uncompacted
>> 16) & 0x1);
1050 brw_inst_set_bits(dst
, 23, 8, (uncompacted
& 0xffff));
1052 if (devinfo
->gen
== 7)
1053 brw_inst_set_bits(dst
, 90, 89, uncompacted
>> 17);
1058 set_uncompacted_datatype(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1059 brw_compact_inst
*src
)
1061 uint32_t uncompacted
= datatype_table
[brw_compact_inst_datatype_index(src
)];
1063 if (devinfo
->gen
>= 8) {
1064 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 18));
1065 brw_inst_set_bits(dst
, 94, 89, (uncompacted
>> 12) & 0x3f);
1066 brw_inst_set_bits(dst
, 46, 35, (uncompacted
>> 0) & 0xfff);
1068 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 15));
1069 brw_inst_set_bits(dst
, 46, 32, (uncompacted
& 0x7fff));
1074 set_uncompacted_subreg(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1075 brw_compact_inst
*src
)
1077 uint16_t uncompacted
= subreg_table
[brw_compact_inst_subreg_index(src
)];
1079 brw_inst_set_bits(dst
, 100, 96, (uncompacted
>> 10));
1080 brw_inst_set_bits(dst
, 68, 64, (uncompacted
>> 5) & 0x1f);
1081 brw_inst_set_bits(dst
, 52, 48, (uncompacted
>> 0) & 0x1f);
1085 set_uncompacted_src0(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1086 brw_compact_inst
*src
)
1088 uint32_t compacted
= brw_compact_inst_src0_index(src
);
1089 uint16_t uncompacted
= src_index_table
[compacted
];
1091 brw_inst_set_bits(dst
, 88, 77, uncompacted
);
1095 set_uncompacted_src1(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1096 brw_compact_inst
*src
, bool is_immediate
)
1099 signed high5
= brw_compact_inst_src1_index(src
);
1100 /* Replicate top bit of src1_index into high 20 bits of the immediate. */
1101 brw_inst_set_imm_ud(devinfo
, dst
, (high5
<< 27) >> 19);
1103 uint16_t uncompacted
= src_index_table
[brw_compact_inst_src1_index(src
)];
1105 brw_inst_set_bits(dst
, 120, 109, uncompacted
);
1110 set_uncompacted_3src_control_index(const struct brw_device_info
*devinfo
,
1111 brw_inst
*dst
, brw_compact_inst
*src
)
1113 assert(devinfo
->gen
>= 8);
1115 uint32_t compacted
= brw_compact_inst_3src_control_index(src
);
1116 uint32_t uncompacted
= gen8_3src_control_index_table
[compacted
];
1118 brw_inst_set_bits(dst
, 34, 32, (uncompacted
>> 21) & 0x7);
1119 brw_inst_set_bits(dst
, 28, 8, (uncompacted
>> 0) & 0x1fffff);
1121 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
1122 brw_inst_set_bits(dst
, 36, 35, (uncompacted
>> 24) & 0x3);
1126 set_uncompacted_3src_source_index(const struct brw_device_info
*devinfo
,
1127 brw_inst
*dst
, brw_compact_inst
*src
)
1129 assert(devinfo
->gen
>= 8);
1131 uint32_t compacted
= brw_compact_inst_3src_source_index(src
);
1132 uint64_t uncompacted
= gen8_3src_source_index_table
[compacted
];
1134 brw_inst_set_bits(dst
, 83, 83, (uncompacted
>> 43) & 0x1);
1135 brw_inst_set_bits(dst
, 114, 107, (uncompacted
>> 35) & 0xff);
1136 brw_inst_set_bits(dst
, 93, 86, (uncompacted
>> 27) & 0xff);
1137 brw_inst_set_bits(dst
, 72, 65, (uncompacted
>> 19) & 0xff);
1138 brw_inst_set_bits(dst
, 55, 37, (uncompacted
>> 0) & 0x7ffff);
1140 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
1141 brw_inst_set_bits(dst
, 126, 125, (uncompacted
>> 47) & 0x3);
1142 brw_inst_set_bits(dst
, 105, 104, (uncompacted
>> 45) & 0x3);
1143 brw_inst_set_bits(dst
, 84, 84, (uncompacted
>> 44) & 0x1);
1145 brw_inst_set_bits(dst
, 125, 125, (uncompacted
>> 45) & 0x1);
1146 brw_inst_set_bits(dst
, 104, 104, (uncompacted
>> 44) & 0x1);
1151 brw_uncompact_3src_instruction(const struct brw_device_info
*devinfo
,
1152 brw_inst
*dst
, brw_compact_inst
*src
)
1154 assert(devinfo
->gen
>= 8);
1156 #define uncompact(field) \
1157 brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(src))
1161 set_uncompacted_3src_control_index(devinfo
, dst
, src
);
1162 set_uncompacted_3src_source_index(devinfo
, dst
, src
);
1164 uncompact(dst_reg_nr
);
1165 uncompact(src0_rep_ctrl
);
1166 brw_inst_set_3src_cmpt_control(devinfo
, dst
, false);
1167 uncompact(debug_control
);
1168 uncompact(saturate
);
1169 uncompact(src1_rep_ctrl
);
1170 uncompact(src2_rep_ctrl
);
1171 uncompact(src0_reg_nr
);
1172 uncompact(src1_reg_nr
);
1173 uncompact(src2_reg_nr
);
1174 uncompact(src0_subreg_nr
);
1175 uncompact(src1_subreg_nr
);
1176 uncompact(src2_subreg_nr
);
1182 brw_uncompact_instruction(const struct brw_device_info
*devinfo
, brw_inst
*dst
,
1183 brw_compact_inst
*src
)
1185 memset(dst
, 0, sizeof(*dst
));
1187 if (devinfo
->gen
>= 8 && is_3src(brw_compact_inst_3src_opcode(src
))) {
1188 brw_uncompact_3src_instruction(devinfo
, dst
, src
);
1192 brw_inst_set_opcode(devinfo
, dst
, brw_compact_inst_opcode(src
));
1193 brw_inst_set_debug_control(devinfo
, dst
, brw_compact_inst_debug_control(src
));
1195 set_uncompacted_control(devinfo
, dst
, src
);
1196 set_uncompacted_datatype(devinfo
, dst
, src
);
1198 /* src0/1 register file fields are in the datatype table. */
1199 bool is_immediate
= brw_inst_src0_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
||
1200 brw_inst_src1_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
;
1202 set_uncompacted_subreg(devinfo
, dst
, src
);
1203 brw_inst_set_acc_wr_control(devinfo
, dst
, brw_compact_inst_acc_wr_control(src
));
1204 brw_inst_set_cond_modifier(devinfo
, dst
, brw_compact_inst_cond_modifier(src
));
1205 if (devinfo
->gen
<= 6)
1206 brw_inst_set_flag_subreg_nr(devinfo
, dst
,
1207 brw_compact_inst_flag_subreg_nr(src
));
1208 set_uncompacted_src0(devinfo
, dst
, src
);
1209 set_uncompacted_src1(devinfo
, dst
, src
, is_immediate
);
1210 brw_inst_set_dst_da_reg_nr(devinfo
, dst
, brw_compact_inst_dst_reg_nr(src
));
1211 brw_inst_set_src0_da_reg_nr(devinfo
, dst
, brw_compact_inst_src0_reg_nr(src
));
1213 brw_inst_set_imm_ud(devinfo
, dst
,
1214 brw_inst_imm_ud(devinfo
, dst
) |
1215 brw_compact_inst_src1_reg_nr(src
));
1217 brw_inst_set_src1_da_reg_nr(devinfo
, dst
, brw_compact_inst_src1_reg_nr(src
));
1221 void brw_debug_compact_uncompact(const struct brw_device_info
*devinfo
,
1223 brw_inst
*uncompacted
)
1225 fprintf(stderr
, "Instruction compact/uncompact changed (gen%d):\n",
1228 fprintf(stderr
, " before: ");
1229 brw_disassemble_inst(stderr
, devinfo
, orig
, true);
1231 fprintf(stderr
, " after: ");
1232 brw_disassemble_inst(stderr
, devinfo
, uncompacted
, false);
1234 uint32_t *before_bits
= (uint32_t *)orig
;
1235 uint32_t *after_bits
= (uint32_t *)uncompacted
;
1236 fprintf(stderr
, " changed bits:\n");
1237 for (int i
= 0; i
< 128; i
++) {
1238 uint32_t before
= before_bits
[i
/ 32] & (1 << (i
& 31));
1239 uint32_t after
= after_bits
[i
/ 32] & (1 << (i
& 31));
1241 if (before
!= after
) {
1242 fprintf(stderr
, " bit %d, %s to %s\n", i
,
1243 before
? "set" : "unset",
1244 after
? "set" : "unset");
1250 compacted_between(int old_ip
, int old_target_ip
, int *compacted_counts
)
1252 int this_compacted_count
= compacted_counts
[old_ip
];
1253 int target_compacted_count
= compacted_counts
[old_target_ip
];
1254 return target_compacted_count
- this_compacted_count
;
1258 update_uip_jip(const struct brw_device_info
*devinfo
, brw_inst
*insn
,
1259 int this_old_ip
, int *compacted_counts
)
1261 /* JIP and UIP are in units of:
1262 * - bytes on Gen8+; and
1263 * - compacted instructions on Gen6+.
1265 int shift
= devinfo
->gen
>= 8 ? 3 : 0;
1267 int32_t jip_compacted
= brw_inst_jip(devinfo
, insn
) >> shift
;
1268 jip_compacted
-= compacted_between(this_old_ip
,
1269 this_old_ip
+ (jip_compacted
/ 2),
1271 brw_inst_set_jip(devinfo
, insn
, jip_compacted
<< shift
);
1273 if (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ENDIF
||
1274 brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_WHILE
||
1275 (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ELSE
&& devinfo
->gen
<= 7))
1278 int32_t uip_compacted
= brw_inst_uip(devinfo
, insn
) >> shift
;
1279 uip_compacted
-= compacted_between(this_old_ip
,
1280 this_old_ip
+ (uip_compacted
/ 2),
1282 brw_inst_set_uip(devinfo
, insn
, uip_compacted
<< shift
);
1286 update_gen4_jump_count(const struct brw_device_info
*devinfo
, brw_inst
*insn
,
1287 int this_old_ip
, int *compacted_counts
)
1289 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
);
1291 /* Jump Count is in units of:
1292 * - uncompacted instructions on G45; and
1293 * - compacted instructions on Gen5.
1295 int shift
= devinfo
->is_g4x
? 1 : 0;
1297 int jump_count_compacted
= brw_inst_gen4_jump_count(devinfo
, insn
) << shift
;
1299 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1301 int this_compacted_count
= compacted_counts
[this_old_ip
];
1302 int target_compacted_count
= compacted_counts
[target_old_ip
];
1304 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1305 brw_inst_set_gen4_jump_count(devinfo
, insn
, jump_count_compacted
>> shift
);
1309 brw_init_compaction_tables(const struct brw_device_info
*devinfo
)
1311 static bool initialized
;
1312 if (initialized
|| p_atomic_cmpxchg(&initialized
, false, true) != false)
1315 assert(g45_control_index_table
[ARRAY_SIZE(g45_control_index_table
) - 1] != 0);
1316 assert(g45_datatype_table
[ARRAY_SIZE(g45_datatype_table
) - 1] != 0);
1317 assert(g45_subreg_table
[ARRAY_SIZE(g45_subreg_table
) - 1] != 0);
1318 assert(g45_src_index_table
[ARRAY_SIZE(g45_src_index_table
) - 1] != 0);
1319 assert(gen6_control_index_table
[ARRAY_SIZE(gen6_control_index_table
) - 1] != 0);
1320 assert(gen6_datatype_table
[ARRAY_SIZE(gen6_datatype_table
) - 1] != 0);
1321 assert(gen6_subreg_table
[ARRAY_SIZE(gen6_subreg_table
) - 1] != 0);
1322 assert(gen6_src_index_table
[ARRAY_SIZE(gen6_src_index_table
) - 1] != 0);
1323 assert(gen7_control_index_table
[ARRAY_SIZE(gen7_control_index_table
) - 1] != 0);
1324 assert(gen7_datatype_table
[ARRAY_SIZE(gen7_datatype_table
) - 1] != 0);
1325 assert(gen7_subreg_table
[ARRAY_SIZE(gen7_subreg_table
) - 1] != 0);
1326 assert(gen7_src_index_table
[ARRAY_SIZE(gen7_src_index_table
) - 1] != 0);
1327 assert(gen8_control_index_table
[ARRAY_SIZE(gen8_control_index_table
) - 1] != 0);
1328 assert(gen8_datatype_table
[ARRAY_SIZE(gen8_datatype_table
) - 1] != 0);
1329 assert(gen8_subreg_table
[ARRAY_SIZE(gen8_subreg_table
) - 1] != 0);
1330 assert(gen8_src_index_table
[ARRAY_SIZE(gen8_src_index_table
) - 1] != 0);
1332 switch (devinfo
->gen
) {
1335 control_index_table
= gen8_control_index_table
;
1336 datatype_table
= gen8_datatype_table
;
1337 subreg_table
= gen8_subreg_table
;
1338 src_index_table
= gen8_src_index_table
;
1341 control_index_table
= gen7_control_index_table
;
1342 datatype_table
= gen7_datatype_table
;
1343 subreg_table
= gen7_subreg_table
;
1344 src_index_table
= gen7_src_index_table
;
1347 control_index_table
= gen6_control_index_table
;
1348 datatype_table
= gen6_datatype_table
;
1349 subreg_table
= gen6_subreg_table
;
1350 src_index_table
= gen6_src_index_table
;
1354 control_index_table
= g45_control_index_table
;
1355 datatype_table
= g45_datatype_table
;
1356 subreg_table
= g45_subreg_table
;
1357 src_index_table
= g45_src_index_table
;
1360 unreachable("unknown generation");
1365 brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1366 int num_annotations
, struct annotation
*annotation
)
1368 const struct brw_device_info
*devinfo
= p
->devinfo
;
1369 void *store
= p
->store
+ start_offset
/ 16;
1370 /* For an instruction at byte offset 16*i before compaction, this is the
1371 * number of compacted instructions minus the number of padding NOP/NENOPs
1374 int compacted_counts
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_inst
)];
1375 /* For an instruction at byte offset 8*i after compaction, this was its IP
1376 * (in 16-byte units) before compaction.
1378 int old_ip
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_compact_inst
)];
1380 if (devinfo
->gen
== 4 && !devinfo
->is_g4x
)
1384 int compacted_count
= 0;
1385 for (int src_offset
= 0; src_offset
< p
->next_insn_offset
- start_offset
;
1386 src_offset
+= sizeof(brw_inst
)) {
1387 brw_inst
*src
= store
+ src_offset
;
1388 void *dst
= store
+ offset
;
1390 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1391 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1393 brw_inst saved
= *src
;
1395 if (brw_try_compact_instruction(devinfo
, dst
, src
)) {
1399 brw_inst uncompacted
;
1400 brw_uncompact_instruction(devinfo
, &uncompacted
, dst
);
1401 if (memcmp(&saved
, &uncompacted
, sizeof(uncompacted
))) {
1402 brw_debug_compact_uncompact(devinfo
, &saved
, &uncompacted
);
1406 offset
+= sizeof(brw_compact_inst
);
1408 /* All uncompacted instructions need to be aligned on G45. */
1409 if ((offset
& sizeof(brw_compact_inst
)) != 0 && devinfo
->is_g4x
){
1410 brw_compact_inst
*align
= store
+ offset
;
1411 memset(align
, 0, sizeof(*align
));
1412 brw_compact_inst_set_opcode(align
, BRW_OPCODE_NENOP
);
1413 brw_compact_inst_set_cmpt_control(align
, true);
1414 offset
+= sizeof(brw_compact_inst
);
1416 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1417 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1419 dst
= store
+ offset
;
1422 /* If we didn't compact this intruction, we need to move it down into
1425 if (offset
!= src_offset
) {
1426 memmove(dst
, src
, sizeof(brw_inst
));
1428 offset
+= sizeof(brw_inst
);
1432 /* Fix up control flow offsets. */
1433 p
->next_insn_offset
= start_offset
+ offset
;
1434 for (offset
= 0; offset
< p
->next_insn_offset
- start_offset
;
1435 offset
= next_offset(devinfo
, store
, offset
)) {
1436 brw_inst
*insn
= store
+ offset
;
1437 int this_old_ip
= old_ip
[offset
/ sizeof(brw_compact_inst
)];
1438 int this_compacted_count
= compacted_counts
[this_old_ip
];
1440 switch (brw_inst_opcode(devinfo
, insn
)) {
1441 case BRW_OPCODE_BREAK
:
1442 case BRW_OPCODE_CONTINUE
:
1443 case BRW_OPCODE_HALT
:
1444 if (devinfo
->gen
>= 6) {
1445 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1447 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1453 case BRW_OPCODE_IFF
:
1454 case BRW_OPCODE_ELSE
:
1455 case BRW_OPCODE_ENDIF
:
1456 case BRW_OPCODE_WHILE
:
1457 if (devinfo
->gen
>= 7) {
1458 if (brw_inst_cmpt_control(devinfo
, insn
)) {
1459 brw_inst uncompacted
;
1460 brw_uncompact_instruction(devinfo
, &uncompacted
,
1461 (brw_compact_inst
*)insn
);
1463 update_uip_jip(devinfo
, &uncompacted
, this_old_ip
,
1466 bool ret
= brw_try_compact_instruction(devinfo
,
1467 (brw_compact_inst
*)insn
,
1469 assert(ret
); (void)ret
;
1471 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1473 } else if (devinfo
->gen
== 6) {
1474 assert(!brw_inst_cmpt_control(devinfo
, insn
));
1476 /* Jump Count is in units of compacted instructions on Gen6. */
1477 int jump_count_compacted
= brw_inst_gen6_jump_count(devinfo
, insn
);
1479 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1480 int target_compacted_count
= compacted_counts
[target_old_ip
];
1481 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1482 brw_inst_set_gen6_jump_count(devinfo
, insn
, jump_count_compacted
);
1484 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1489 case BRW_OPCODE_ADD
:
1490 /* Add instructions modifying the IP register use an immediate src1,
1491 * and Gens that use this cannot compact instructions with immediate
1494 if (brw_inst_cmpt_control(devinfo
, insn
))
1497 if (brw_inst_dst_reg_file(devinfo
, insn
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
1498 brw_inst_dst_da_reg_nr(devinfo
, insn
) == BRW_ARF_IP
) {
1499 assert(brw_inst_src1_reg_file(devinfo
, insn
) == BRW_IMMEDIATE_VALUE
);
1502 int jump_compacted
= brw_inst_imm_d(devinfo
, insn
) >> shift
;
1504 int target_old_ip
= this_old_ip
+ (jump_compacted
/ 2);
1505 int target_compacted_count
= compacted_counts
[target_old_ip
];
1506 jump_compacted
-= (target_compacted_count
- this_compacted_count
);
1507 brw_inst_set_imm_ud(devinfo
, insn
, jump_compacted
<< shift
);
1513 /* p->nr_insn is counting the number of uncompacted instructions still, so
1514 * divide. We do want to be sure there's a valid instruction in any
1515 * alignment padding, so that the next compression pass (for the FS 8/16
1516 * compile passes) parses correctly.
1518 if (p
->next_insn_offset
& sizeof(brw_compact_inst
)) {
1519 brw_compact_inst
*align
= store
+ offset
;
1520 memset(align
, 0, sizeof(*align
));
1521 brw_compact_inst_set_opcode(align
, BRW_OPCODE_NOP
);
1522 brw_compact_inst_set_cmpt_control(align
, true);
1523 p
->next_insn_offset
+= sizeof(brw_compact_inst
);
1525 p
->nr_insn
= p
->next_insn_offset
/ sizeof(brw_inst
);
1527 /* Update the instruction offsets for each annotation. */
1529 for (int offset
= 0, i
= 0; i
< num_annotations
; i
++) {
1530 while (start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1531 sizeof(brw_inst
) != annotation
[i
].offset
) {
1532 assert(start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1533 sizeof(brw_inst
) < annotation
[i
].offset
);
1534 offset
= next_offset(devinfo
, store
, offset
);
1537 annotation
[i
].offset
= start_offset
+ offset
;
1539 offset
= next_offset(devinfo
, store
, offset
);
1542 annotation
[num_annotations
].offset
= p
->next_insn_offset
;