2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
34 #include "brw_defines.h"
37 #include "glsl/ralloc.h"
39 /***********************************************************************
40 * Internal helper for constructing instructions
43 static void guess_execution_size(struct brw_compile
*p
,
44 struct brw_instruction
*insn
,
47 if (reg
.width
== BRW_WIDTH_8
&& p
->compressed
)
48 insn
->header
.execution_size
= BRW_EXECUTE_16
;
50 insn
->header
.execution_size
= reg
.width
; /* note - definitions are compatible */
55 * Prior to Sandybridge, the SEND instruction accepted non-MRF source
56 * registers, implicitly moving the operand to a message register.
58 * On Sandybridge, this is no longer the case. This function performs the
59 * explicit move; it should be called before emitting a SEND instruction.
62 gen6_resolve_implied_move(struct brw_compile
*p
,
66 struct intel_context
*intel
= &p
->brw
->intel
;
70 if (src
->file
== BRW_MESSAGE_REGISTER_FILE
)
73 if (src
->file
!= BRW_ARCHITECTURE_REGISTER_FILE
|| src
->nr
!= BRW_ARF_NULL
) {
74 brw_push_insn_state(p
);
75 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
76 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
77 brw_MOV(p
, retype(brw_message_reg(msg_reg_nr
), BRW_REGISTER_TYPE_UD
),
78 retype(*src
, BRW_REGISTER_TYPE_UD
));
79 brw_pop_insn_state(p
);
81 *src
= brw_message_reg(msg_reg_nr
);
85 gen7_convert_mrf_to_grf(struct brw_compile
*p
, struct brw_reg
*reg
)
87 struct intel_context
*intel
= &p
->brw
->intel
;
88 if (intel
->gen
== 7 && reg
->file
== BRW_MESSAGE_REGISTER_FILE
) {
89 reg
->file
= BRW_GENERAL_REGISTER_FILE
;
96 brw_set_dest(struct brw_compile
*p
, struct brw_instruction
*insn
,
99 if (dest
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
&&
100 dest
.file
!= BRW_MESSAGE_REGISTER_FILE
)
101 assert(dest
.nr
< 128);
103 gen7_convert_mrf_to_grf(p
, &dest
);
105 insn
->bits1
.da1
.dest_reg_file
= dest
.file
;
106 insn
->bits1
.da1
.dest_reg_type
= dest
.type
;
107 insn
->bits1
.da1
.dest_address_mode
= dest
.address_mode
;
109 if (dest
.address_mode
== BRW_ADDRESS_DIRECT
) {
110 insn
->bits1
.da1
.dest_reg_nr
= dest
.nr
;
112 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
113 insn
->bits1
.da1
.dest_subreg_nr
= dest
.subnr
;
114 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
115 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
116 insn
->bits1
.da1
.dest_horiz_stride
= dest
.hstride
;
119 insn
->bits1
.da16
.dest_subreg_nr
= dest
.subnr
/ 16;
120 insn
->bits1
.da16
.dest_writemask
= dest
.dw1
.bits
.writemask
;
121 /* even ignored in da16, still need to set as '01' */
122 insn
->bits1
.da16
.dest_horiz_stride
= 1;
126 insn
->bits1
.ia1
.dest_subreg_nr
= dest
.subnr
;
128 /* These are different sizes in align1 vs align16:
130 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
131 insn
->bits1
.ia1
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
132 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
133 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
134 insn
->bits1
.ia1
.dest_horiz_stride
= dest
.hstride
;
137 insn
->bits1
.ia16
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
138 /* even ignored in da16, still need to set as '01' */
139 insn
->bits1
.ia16
.dest_horiz_stride
= 1;
143 /* NEW: Set the execution size based on dest.width and
144 * insn->compression_control:
146 guess_execution_size(p
, insn
, dest
);
149 extern int reg_type_size
[];
152 validate_reg(struct brw_instruction
*insn
, struct brw_reg reg
)
154 int hstride_for_reg
[] = {0, 1, 2, 4};
155 int vstride_for_reg
[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
156 int width_for_reg
[] = {1, 2, 4, 8, 16};
157 int execsize_for_reg
[] = {1, 2, 4, 8, 16};
158 int width
, hstride
, vstride
, execsize
;
160 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
161 /* 3.3.6: Region Parameters. Restriction: Immediate vectors
162 * mean the destination has to be 128-bit aligned and the
163 * destination horiz stride has to be a word.
165 if (reg
.type
== BRW_REGISTER_TYPE_V
) {
166 assert(hstride_for_reg
[insn
->bits1
.da1
.dest_horiz_stride
] *
167 reg_type_size
[insn
->bits1
.da1
.dest_reg_type
] == 2);
173 if (reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
174 reg
.file
== BRW_ARF_NULL
)
177 assert(reg
.hstride
>= 0 && reg
.hstride
< Elements(hstride_for_reg
));
178 hstride
= hstride_for_reg
[reg
.hstride
];
180 if (reg
.vstride
== 0xf) {
183 assert(reg
.vstride
>= 0 && reg
.vstride
< Elements(vstride_for_reg
));
184 vstride
= vstride_for_reg
[reg
.vstride
];
187 assert(reg
.width
>= 0 && reg
.width
< Elements(width_for_reg
));
188 width
= width_for_reg
[reg
.width
];
190 assert(insn
->header
.execution_size
>= 0 &&
191 insn
->header
.execution_size
< Elements(execsize_for_reg
));
192 execsize
= execsize_for_reg
[insn
->header
.execution_size
];
194 /* Restrictions from 3.3.10: Register Region Restrictions. */
196 assert(execsize
>= width
);
199 if (execsize
== width
&& hstride
!= 0) {
200 assert(vstride
== -1 || vstride
== width
* hstride
);
204 if (execsize
== width
&& hstride
== 0) {
205 /* no restriction on vstride. */
210 assert(hstride
== 0);
214 if (execsize
== 1 && width
== 1) {
215 assert(hstride
== 0);
216 assert(vstride
== 0);
220 if (vstride
== 0 && hstride
== 0) {
224 /* 10. Check destination issues. */
228 brw_set_src0(struct brw_compile
*p
, struct brw_instruction
*insn
,
231 if (reg
.type
!= BRW_ARCHITECTURE_REGISTER_FILE
)
232 assert(reg
.nr
< 128);
234 gen7_convert_mrf_to_grf(p
, ®
);
236 validate_reg(insn
, reg
);
238 insn
->bits1
.da1
.src0_reg_file
= reg
.file
;
239 insn
->bits1
.da1
.src0_reg_type
= reg
.type
;
240 insn
->bits2
.da1
.src0_abs
= reg
.abs
;
241 insn
->bits2
.da1
.src0_negate
= reg
.negate
;
242 insn
->bits2
.da1
.src0_address_mode
= reg
.address_mode
;
244 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
245 insn
->bits3
.ud
= reg
.dw1
.ud
;
247 /* Required to set some fields in src1 as well:
249 insn
->bits1
.da1
.src1_reg_file
= 0; /* arf */
250 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
254 if (reg
.address_mode
== BRW_ADDRESS_DIRECT
) {
255 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
256 insn
->bits2
.da1
.src0_subreg_nr
= reg
.subnr
;
257 insn
->bits2
.da1
.src0_reg_nr
= reg
.nr
;
260 insn
->bits2
.da16
.src0_subreg_nr
= reg
.subnr
/ 16;
261 insn
->bits2
.da16
.src0_reg_nr
= reg
.nr
;
265 insn
->bits2
.ia1
.src0_subreg_nr
= reg
.subnr
;
267 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
268 insn
->bits2
.ia1
.src0_indirect_offset
= reg
.dw1
.bits
.indirect_offset
;
271 insn
->bits2
.ia16
.src0_subreg_nr
= reg
.dw1
.bits
.indirect_offset
;
275 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
276 if (reg
.width
== BRW_WIDTH_1
&&
277 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
278 insn
->bits2
.da1
.src0_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
279 insn
->bits2
.da1
.src0_width
= BRW_WIDTH_1
;
280 insn
->bits2
.da1
.src0_vert_stride
= BRW_VERTICAL_STRIDE_0
;
283 insn
->bits2
.da1
.src0_horiz_stride
= reg
.hstride
;
284 insn
->bits2
.da1
.src0_width
= reg
.width
;
285 insn
->bits2
.da1
.src0_vert_stride
= reg
.vstride
;
289 insn
->bits2
.da16
.src0_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
290 insn
->bits2
.da16
.src0_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
291 insn
->bits2
.da16
.src0_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
292 insn
->bits2
.da16
.src0_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
294 /* This is an oddity of the fact we're using the same
295 * descriptions for registers in align_16 as align_1:
297 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
298 insn
->bits2
.da16
.src0_vert_stride
= BRW_VERTICAL_STRIDE_4
;
300 insn
->bits2
.da16
.src0_vert_stride
= reg
.vstride
;
306 void brw_set_src1(struct brw_compile
*p
,
307 struct brw_instruction
*insn
,
310 assert(reg
.file
!= BRW_MESSAGE_REGISTER_FILE
);
312 assert(reg
.nr
< 128);
314 gen7_convert_mrf_to_grf(p
, ®
);
316 validate_reg(insn
, reg
);
318 insn
->bits1
.da1
.src1_reg_file
= reg
.file
;
319 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
320 insn
->bits3
.da1
.src1_abs
= reg
.abs
;
321 insn
->bits3
.da1
.src1_negate
= reg
.negate
;
323 /* Only src1 can be immediate in two-argument instructions.
325 assert(insn
->bits1
.da1
.src0_reg_file
!= BRW_IMMEDIATE_VALUE
);
327 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
328 insn
->bits3
.ud
= reg
.dw1
.ud
;
331 /* This is a hardware restriction, which may or may not be lifted
334 assert (reg
.address_mode
== BRW_ADDRESS_DIRECT
);
335 /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
337 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
338 insn
->bits3
.da1
.src1_subreg_nr
= reg
.subnr
;
339 insn
->bits3
.da1
.src1_reg_nr
= reg
.nr
;
342 insn
->bits3
.da16
.src1_subreg_nr
= reg
.subnr
/ 16;
343 insn
->bits3
.da16
.src1_reg_nr
= reg
.nr
;
346 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
347 if (reg
.width
== BRW_WIDTH_1
&&
348 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
349 insn
->bits3
.da1
.src1_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
350 insn
->bits3
.da1
.src1_width
= BRW_WIDTH_1
;
351 insn
->bits3
.da1
.src1_vert_stride
= BRW_VERTICAL_STRIDE_0
;
354 insn
->bits3
.da1
.src1_horiz_stride
= reg
.hstride
;
355 insn
->bits3
.da1
.src1_width
= reg
.width
;
356 insn
->bits3
.da1
.src1_vert_stride
= reg
.vstride
;
360 insn
->bits3
.da16
.src1_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
361 insn
->bits3
.da16
.src1_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
362 insn
->bits3
.da16
.src1_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
363 insn
->bits3
.da16
.src1_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
365 /* This is an oddity of the fact we're using the same
366 * descriptions for registers in align_16 as align_1:
368 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
369 insn
->bits3
.da16
.src1_vert_stride
= BRW_VERTICAL_STRIDE_4
;
371 insn
->bits3
.da16
.src1_vert_stride
= reg
.vstride
;
377 * Set the Message Descriptor and Extended Message Descriptor fields
380 * \note This zeroes out the Function Control bits, so it must be called
381 * \b before filling out any message-specific data. Callers can
382 * choose not to fill in irrelevant bits; they will be zero.
385 brw_set_message_descriptor(struct brw_compile
*p
,
386 struct brw_instruction
*inst
,
387 enum brw_message_target sfid
,
389 unsigned response_length
,
393 struct intel_context
*intel
= &p
->brw
->intel
;
395 brw_set_src1(p
, inst
, brw_imm_d(0));
397 if (intel
->gen
>= 5) {
398 inst
->bits3
.generic_gen5
.header_present
= header_present
;
399 inst
->bits3
.generic_gen5
.response_length
= response_length
;
400 inst
->bits3
.generic_gen5
.msg_length
= msg_length
;
401 inst
->bits3
.generic_gen5
.end_of_thread
= end_of_thread
;
403 if (intel
->gen
>= 6) {
404 /* On Gen6+ Message target/SFID goes in bits 27:24 of the header */
405 inst
->header
.destreg__conditionalmod
= sfid
;
407 /* Set Extended Message Descriptor (ex_desc) */
408 inst
->bits2
.send_gen5
.sfid
= sfid
;
409 inst
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
412 inst
->bits3
.generic
.response_length
= response_length
;
413 inst
->bits3
.generic
.msg_length
= msg_length
;
414 inst
->bits3
.generic
.msg_target
= sfid
;
415 inst
->bits3
.generic
.end_of_thread
= end_of_thread
;
419 static void brw_set_math_message( struct brw_compile
*p
,
420 struct brw_instruction
*insn
,
427 struct brw_context
*brw
= p
->brw
;
428 struct intel_context
*intel
= &brw
->intel
;
430 unsigned response_length
;
432 /* Infer message length from the function */
434 case BRW_MATH_FUNCTION_POW
:
435 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
436 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
437 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
445 /* Infer response length from the function */
447 case BRW_MATH_FUNCTION_SINCOS
:
448 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
456 brw_set_message_descriptor(p
, insn
, BRW_SFID_MATH
,
457 msg_length
, response_length
, false, false);
458 if (intel
->gen
== 5) {
459 insn
->bits3
.math_gen5
.function
= function
;
460 insn
->bits3
.math_gen5
.int_type
= integer_type
;
461 insn
->bits3
.math_gen5
.precision
= low_precision
;
462 insn
->bits3
.math_gen5
.saturate
= saturate
;
463 insn
->bits3
.math_gen5
.data_type
= dataType
;
464 insn
->bits3
.math_gen5
.snapshot
= 0;
466 insn
->bits3
.math
.function
= function
;
467 insn
->bits3
.math
.int_type
= integer_type
;
468 insn
->bits3
.math
.precision
= low_precision
;
469 insn
->bits3
.math
.saturate
= saturate
;
470 insn
->bits3
.math
.data_type
= dataType
;
475 static void brw_set_ff_sync_message(struct brw_compile
*p
,
476 struct brw_instruction
*insn
,
478 GLuint response_length
,
481 brw_set_message_descriptor(p
, insn
, BRW_SFID_URB
,
482 1, response_length
, true, end_of_thread
);
483 insn
->bits3
.urb_gen5
.opcode
= 1; /* FF_SYNC */
484 insn
->bits3
.urb_gen5
.offset
= 0; /* Not used by FF_SYNC */
485 insn
->bits3
.urb_gen5
.swizzle_control
= 0; /* Not used by FF_SYNC */
486 insn
->bits3
.urb_gen5
.allocate
= allocate
;
487 insn
->bits3
.urb_gen5
.used
= 0; /* Not used by FF_SYNC */
488 insn
->bits3
.urb_gen5
.complete
= 0; /* Not used by FF_SYNC */
491 static void brw_set_urb_message( struct brw_compile
*p
,
492 struct brw_instruction
*insn
,
496 GLuint response_length
,
500 GLuint swizzle_control
)
502 struct brw_context
*brw
= p
->brw
;
503 struct intel_context
*intel
= &brw
->intel
;
505 brw_set_message_descriptor(p
, insn
, BRW_SFID_URB
,
506 msg_length
, response_length
, true, end_of_thread
);
507 if (intel
->gen
== 7) {
508 insn
->bits3
.urb_gen7
.opcode
= 0; /* URB_WRITE_HWORD */
509 insn
->bits3
.urb_gen7
.offset
= offset
;
510 assert(swizzle_control
!= BRW_URB_SWIZZLE_TRANSPOSE
);
511 insn
->bits3
.urb_gen7
.swizzle_control
= swizzle_control
;
512 /* per_slot_offset = 0 makes it ignore offsets in message header */
513 insn
->bits3
.urb_gen7
.per_slot_offset
= 0;
514 insn
->bits3
.urb_gen7
.complete
= complete
;
515 } else if (intel
->gen
>= 5) {
516 insn
->bits3
.urb_gen5
.opcode
= 0; /* URB_WRITE */
517 insn
->bits3
.urb_gen5
.offset
= offset
;
518 insn
->bits3
.urb_gen5
.swizzle_control
= swizzle_control
;
519 insn
->bits3
.urb_gen5
.allocate
= allocate
;
520 insn
->bits3
.urb_gen5
.used
= used
; /* ? */
521 insn
->bits3
.urb_gen5
.complete
= complete
;
523 insn
->bits3
.urb
.opcode
= 0; /* ? */
524 insn
->bits3
.urb
.offset
= offset
;
525 insn
->bits3
.urb
.swizzle_control
= swizzle_control
;
526 insn
->bits3
.urb
.allocate
= allocate
;
527 insn
->bits3
.urb
.used
= used
; /* ? */
528 insn
->bits3
.urb
.complete
= complete
;
533 brw_set_dp_write_message(struct brw_compile
*p
,
534 struct brw_instruction
*insn
,
535 GLuint binding_table_index
,
540 GLuint last_render_target
,
541 GLuint response_length
,
542 GLuint end_of_thread
,
543 GLuint send_commit_msg
)
545 struct brw_context
*brw
= p
->brw
;
546 struct intel_context
*intel
= &brw
->intel
;
549 if (intel
->gen
>= 7) {
550 /* Use the Render Cache for RT writes; otherwise use the Data Cache */
551 if (msg_type
== GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
)
552 sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
554 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
555 } else if (intel
->gen
== 6) {
556 /* Use the render cache for all write messages. */
557 sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
559 sfid
= BRW_SFID_DATAPORT_WRITE
;
562 brw_set_message_descriptor(p
, insn
, sfid
, msg_length
, response_length
,
563 header_present
, end_of_thread
);
565 if (intel
->gen
>= 7) {
566 insn
->bits3
.gen7_dp
.binding_table_index
= binding_table_index
;
567 insn
->bits3
.gen7_dp
.msg_control
= msg_control
;
568 insn
->bits3
.gen7_dp
.last_render_target
= last_render_target
;
569 insn
->bits3
.gen7_dp
.msg_type
= msg_type
;
570 } else if (intel
->gen
== 6) {
571 insn
->bits3
.gen6_dp
.binding_table_index
= binding_table_index
;
572 insn
->bits3
.gen6_dp
.msg_control
= msg_control
;
573 insn
->bits3
.gen6_dp
.last_render_target
= last_render_target
;
574 insn
->bits3
.gen6_dp
.msg_type
= msg_type
;
575 insn
->bits3
.gen6_dp
.send_commit_msg
= send_commit_msg
;
576 } else if (intel
->gen
== 5) {
577 insn
->bits3
.dp_write_gen5
.binding_table_index
= binding_table_index
;
578 insn
->bits3
.dp_write_gen5
.msg_control
= msg_control
;
579 insn
->bits3
.dp_write_gen5
.last_render_target
= last_render_target
;
580 insn
->bits3
.dp_write_gen5
.msg_type
= msg_type
;
581 insn
->bits3
.dp_write_gen5
.send_commit_msg
= send_commit_msg
;
583 insn
->bits3
.dp_write
.binding_table_index
= binding_table_index
;
584 insn
->bits3
.dp_write
.msg_control
= msg_control
;
585 insn
->bits3
.dp_write
.last_render_target
= last_render_target
;
586 insn
->bits3
.dp_write
.msg_type
= msg_type
;
587 insn
->bits3
.dp_write
.send_commit_msg
= send_commit_msg
;
592 brw_set_dp_read_message(struct brw_compile
*p
,
593 struct brw_instruction
*insn
,
594 GLuint binding_table_index
,
599 GLuint response_length
)
601 struct brw_context
*brw
= p
->brw
;
602 struct intel_context
*intel
= &brw
->intel
;
605 if (intel
->gen
>= 7) {
606 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
607 } else if (intel
->gen
== 6) {
608 if (target_cache
== BRW_DATAPORT_READ_TARGET_RENDER_CACHE
)
609 sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
611 sfid
= GEN6_SFID_DATAPORT_SAMPLER_CACHE
;
613 sfid
= BRW_SFID_DATAPORT_READ
;
616 brw_set_message_descriptor(p
, insn
, sfid
, msg_length
, response_length
,
619 if (intel
->gen
>= 7) {
620 insn
->bits3
.gen7_dp
.binding_table_index
= binding_table_index
;
621 insn
->bits3
.gen7_dp
.msg_control
= msg_control
;
622 insn
->bits3
.gen7_dp
.last_render_target
= 0;
623 insn
->bits3
.gen7_dp
.msg_type
= msg_type
;
624 } else if (intel
->gen
== 6) {
625 insn
->bits3
.gen6_dp
.binding_table_index
= binding_table_index
;
626 insn
->bits3
.gen6_dp
.msg_control
= msg_control
;
627 insn
->bits3
.gen6_dp
.last_render_target
= 0;
628 insn
->bits3
.gen6_dp
.msg_type
= msg_type
;
629 insn
->bits3
.gen6_dp
.send_commit_msg
= 0;
630 } else if (intel
->gen
== 5) {
631 insn
->bits3
.dp_read_gen5
.binding_table_index
= binding_table_index
;
632 insn
->bits3
.dp_read_gen5
.msg_control
= msg_control
;
633 insn
->bits3
.dp_read_gen5
.msg_type
= msg_type
;
634 insn
->bits3
.dp_read_gen5
.target_cache
= target_cache
;
635 } else if (intel
->is_g4x
) {
636 insn
->bits3
.dp_read_g4x
.binding_table_index
= binding_table_index
; /*0:7*/
637 insn
->bits3
.dp_read_g4x
.msg_control
= msg_control
; /*8:10*/
638 insn
->bits3
.dp_read_g4x
.msg_type
= msg_type
; /*11:13*/
639 insn
->bits3
.dp_read_g4x
.target_cache
= target_cache
; /*14:15*/
641 insn
->bits3
.dp_read
.binding_table_index
= binding_table_index
; /*0:7*/
642 insn
->bits3
.dp_read
.msg_control
= msg_control
; /*8:11*/
643 insn
->bits3
.dp_read
.msg_type
= msg_type
; /*12:13*/
644 insn
->bits3
.dp_read
.target_cache
= target_cache
; /*14:15*/
648 static void brw_set_sampler_message(struct brw_compile
*p
,
649 struct brw_instruction
*insn
,
650 GLuint binding_table_index
,
653 GLuint response_length
,
655 GLuint header_present
,
657 GLuint return_format
)
659 struct brw_context
*brw
= p
->brw
;
660 struct intel_context
*intel
= &brw
->intel
;
662 brw_set_message_descriptor(p
, insn
, BRW_SFID_SAMPLER
, msg_length
,
663 response_length
, header_present
, false);
665 if (intel
->gen
>= 7) {
666 insn
->bits3
.sampler_gen7
.binding_table_index
= binding_table_index
;
667 insn
->bits3
.sampler_gen7
.sampler
= sampler
;
668 insn
->bits3
.sampler_gen7
.msg_type
= msg_type
;
669 insn
->bits3
.sampler_gen7
.simd_mode
= simd_mode
;
670 } else if (intel
->gen
>= 5) {
671 insn
->bits3
.sampler_gen5
.binding_table_index
= binding_table_index
;
672 insn
->bits3
.sampler_gen5
.sampler
= sampler
;
673 insn
->bits3
.sampler_gen5
.msg_type
= msg_type
;
674 insn
->bits3
.sampler_gen5
.simd_mode
= simd_mode
;
675 } else if (intel
->is_g4x
) {
676 insn
->bits3
.sampler_g4x
.binding_table_index
= binding_table_index
;
677 insn
->bits3
.sampler_g4x
.sampler
= sampler
;
678 insn
->bits3
.sampler_g4x
.msg_type
= msg_type
;
680 insn
->bits3
.sampler
.binding_table_index
= binding_table_index
;
681 insn
->bits3
.sampler
.sampler
= sampler
;
682 insn
->bits3
.sampler
.msg_type
= msg_type
;
683 insn
->bits3
.sampler
.return_format
= return_format
;
688 #define next_insn brw_next_insn
689 struct brw_instruction
*
690 brw_next_insn(struct brw_compile
*p
, GLuint opcode
)
692 struct brw_instruction
*insn
;
694 if (p
->nr_insn
+ 1 > p
->store_size
) {
696 printf("incresing the store size to %d\n", p
->store_size
<< 1);
698 p
->store
= reralloc(p
->mem_ctx
, p
->store
,
699 struct brw_instruction
, p
->store_size
);
701 assert(!"realloc eu store memeory failed");
704 insn
= &p
->store
[p
->nr_insn
++];
705 memcpy(insn
, p
->current
, sizeof(*insn
));
707 /* Reset this one-shot flag:
710 if (p
->current
->header
.destreg__conditionalmod
) {
711 p
->current
->header
.destreg__conditionalmod
= 0;
712 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
715 insn
->header
.opcode
= opcode
;
719 static struct brw_instruction
*brw_alu1( struct brw_compile
*p
,
724 struct brw_instruction
*insn
= next_insn(p
, opcode
);
725 brw_set_dest(p
, insn
, dest
);
726 brw_set_src0(p
, insn
, src
);
730 static struct brw_instruction
*brw_alu2(struct brw_compile
*p
,
734 struct brw_reg src1
)
736 struct brw_instruction
*insn
= next_insn(p
, opcode
);
737 brw_set_dest(p
, insn
, dest
);
738 brw_set_src0(p
, insn
, src0
);
739 brw_set_src1(p
, insn
, src1
);
744 /***********************************************************************
745 * Convenience routines.
748 struct brw_instruction *brw_##OP(struct brw_compile *p, \
749 struct brw_reg dest, \
750 struct brw_reg src0) \
752 return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
756 struct brw_instruction *brw_##OP(struct brw_compile *p, \
757 struct brw_reg dest, \
758 struct brw_reg src0, \
759 struct brw_reg src1) \
761 return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
764 /* Rounding operations (other than RNDD) require two instructions - the first
765 * stores a rounded value (possibly the wrong way) in the dest register, but
766 * also sets a per-channel "increment bit" in the flag register. A predicated
767 * add of 1.0 fixes dest to contain the desired result.
769 * Sandybridge and later appear to round correctly without an ADD.
772 void brw_##OP(struct brw_compile *p, \
773 struct brw_reg dest, \
774 struct brw_reg src) \
776 struct brw_instruction *rnd, *add; \
777 rnd = next_insn(p, BRW_OPCODE_##OP); \
778 brw_set_dest(p, rnd, dest); \
779 brw_set_src0(p, rnd, src); \
781 if (p->brw->intel.gen < 6) { \
782 /* turn on round-increments */ \
783 rnd->header.destreg__conditionalmod = BRW_CONDITIONAL_R; \
784 add = brw_ADD(p, dest, dest, brw_imm_f(1.0f)); \
785 add->header.predicate_control = BRW_PREDICATE_NORMAL; \
818 struct brw_instruction
*brw_ADD(struct brw_compile
*p
,
824 if (src0
.type
== BRW_REGISTER_TYPE_F
||
825 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
826 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
827 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
828 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
831 if (src1
.type
== BRW_REGISTER_TYPE_F
||
832 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
833 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
834 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
835 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
838 return brw_alu2(p
, BRW_OPCODE_ADD
, dest
, src0
, src1
);
841 struct brw_instruction
*brw_MUL(struct brw_compile
*p
,
847 if (src0
.type
== BRW_REGISTER_TYPE_D
||
848 src0
.type
== BRW_REGISTER_TYPE_UD
||
849 src1
.type
== BRW_REGISTER_TYPE_D
||
850 src1
.type
== BRW_REGISTER_TYPE_UD
) {
851 assert(dest
.type
!= BRW_REGISTER_TYPE_F
);
854 if (src0
.type
== BRW_REGISTER_TYPE_F
||
855 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
856 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
857 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
858 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
861 if (src1
.type
== BRW_REGISTER_TYPE_F
||
862 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
863 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
864 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
865 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
868 assert(src0
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
869 src0
.nr
!= BRW_ARF_ACCUMULATOR
);
870 assert(src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
871 src1
.nr
!= BRW_ARF_ACCUMULATOR
);
873 return brw_alu2(p
, BRW_OPCODE_MUL
, dest
, src0
, src1
);
877 void brw_NOP(struct brw_compile
*p
)
879 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_NOP
);
880 brw_set_dest(p
, insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
881 brw_set_src0(p
, insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
882 brw_set_src1(p
, insn
, brw_imm_ud(0x0));
889 /***********************************************************************
890 * Comparisons, if/else/endif
893 struct brw_instruction
*brw_JMPI(struct brw_compile
*p
,
898 struct brw_instruction
*insn
= brw_alu2(p
, BRW_OPCODE_JMPI
, dest
, src0
, src1
);
900 insn
->header
.execution_size
= 1;
901 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
902 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
904 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
910 push_if_stack(struct brw_compile
*p
, struct brw_instruction
*inst
)
912 p
->if_stack
[p
->if_stack_depth
] = inst
- p
->store
;
915 if (p
->if_stack_array_size
<= p
->if_stack_depth
) {
916 p
->if_stack_array_size
*= 2;
917 p
->if_stack
= reralloc(p
->mem_ctx
, p
->if_stack
, int,
918 p
->if_stack_array_size
);
922 static struct brw_instruction
*
923 pop_if_stack(struct brw_compile
*p
)
926 return &p
->store
[p
->if_stack
[p
->if_stack_depth
]];
930 push_loop_stack(struct brw_compile
*p
, struct brw_instruction
*inst
)
932 if (p
->loop_stack_array_size
< p
->loop_stack_depth
) {
933 p
->loop_stack_array_size
*= 2;
934 p
->loop_stack
= reralloc(p
->mem_ctx
, p
->loop_stack
, int,
935 p
->loop_stack_array_size
);
936 p
->if_depth_in_loop
= reralloc(p
->mem_ctx
, p
->if_depth_in_loop
, int,
937 p
->loop_stack_array_size
);
940 p
->loop_stack
[p
->loop_stack_depth
] = inst
- p
->store
;
941 p
->loop_stack_depth
++;
942 p
->if_depth_in_loop
[p
->loop_stack_depth
] = 0;
945 static struct brw_instruction
*
946 get_inner_do_insn(struct brw_compile
*p
)
948 return &p
->store
[p
->loop_stack
[p
->loop_stack_depth
- 1]];
951 /* EU takes the value from the flag register and pushes it onto some
952 * sort of a stack (presumably merging with any flag value already on
953 * the stack). Within an if block, the flags at the top of the stack
954 * control execution on each channel of the unit, eg. on each of the
955 * 16 pixel values in our wm programs.
957 * When the matching 'else' instruction is reached (presumably by
958 * countdown of the instruction count patched in by our ELSE/ENDIF
959 * functions), the relevent flags are inverted.
961 * When the matching 'endif' instruction is reached, the flags are
962 * popped off. If the stack is now empty, normal execution resumes.
964 struct brw_instruction
*
965 brw_IF(struct brw_compile
*p
, GLuint execute_size
)
967 struct intel_context
*intel
= &p
->brw
->intel
;
968 struct brw_instruction
*insn
;
970 insn
= next_insn(p
, BRW_OPCODE_IF
);
972 /* Override the defaults for this instruction:
974 if (intel
->gen
< 6) {
975 brw_set_dest(p
, insn
, brw_ip_reg());
976 brw_set_src0(p
, insn
, brw_ip_reg());
977 brw_set_src1(p
, insn
, brw_imm_d(0x0));
978 } else if (intel
->gen
== 6) {
979 brw_set_dest(p
, insn
, brw_imm_w(0));
980 insn
->bits1
.branch_gen6
.jump_count
= 0;
981 brw_set_src0(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
982 brw_set_src1(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
984 brw_set_dest(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
985 brw_set_src0(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
986 brw_set_src1(p
, insn
, brw_imm_ud(0));
987 insn
->bits3
.break_cont
.jip
= 0;
988 insn
->bits3
.break_cont
.uip
= 0;
991 insn
->header
.execution_size
= execute_size
;
992 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
993 insn
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
994 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
995 if (!p
->single_program_flow
)
996 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
998 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1000 push_if_stack(p
, insn
);
1001 p
->if_depth_in_loop
[p
->loop_stack_depth
]++;
1005 /* This function is only used for gen6-style IF instructions with an
1006 * embedded comparison (conditional modifier). It is not used on gen7.
1008 struct brw_instruction
*
1009 gen6_IF(struct brw_compile
*p
, uint32_t conditional
,
1010 struct brw_reg src0
, struct brw_reg src1
)
1012 struct brw_instruction
*insn
;
1014 insn
= next_insn(p
, BRW_OPCODE_IF
);
1016 brw_set_dest(p
, insn
, brw_imm_w(0));
1017 if (p
->compressed
) {
1018 insn
->header
.execution_size
= BRW_EXECUTE_16
;
1020 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1022 insn
->bits1
.branch_gen6
.jump_count
= 0;
1023 brw_set_src0(p
, insn
, src0
);
1024 brw_set_src1(p
, insn
, src1
);
1026 assert(insn
->header
.compression_control
== BRW_COMPRESSION_NONE
);
1027 assert(insn
->header
.predicate_control
== BRW_PREDICATE_NONE
);
1028 insn
->header
.destreg__conditionalmod
= conditional
;
1030 if (!p
->single_program_flow
)
1031 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
1033 push_if_stack(p
, insn
);
1038 * In single-program-flow (SPF) mode, convert IF and ELSE into ADDs.
1041 convert_IF_ELSE_to_ADD(struct brw_compile
*p
,
1042 struct brw_instruction
*if_inst
,
1043 struct brw_instruction
*else_inst
)
1045 /* The next instruction (where the ENDIF would be, if it existed) */
1046 struct brw_instruction
*next_inst
= &p
->store
[p
->nr_insn
];
1048 assert(p
->single_program_flow
);
1049 assert(if_inst
!= NULL
&& if_inst
->header
.opcode
== BRW_OPCODE_IF
);
1050 assert(else_inst
== NULL
|| else_inst
->header
.opcode
== BRW_OPCODE_ELSE
);
1051 assert(if_inst
->header
.execution_size
== BRW_EXECUTE_1
);
1053 /* Convert IF to an ADD instruction that moves the instruction pointer
1054 * to the first instruction of the ELSE block. If there is no ELSE
1055 * block, point to where ENDIF would be. Reverse the predicate.
1057 * There's no need to execute an ENDIF since we don't need to do any
1058 * stack operations, and if we're currently executing, we just want to
1059 * continue normally.
1061 if_inst
->header
.opcode
= BRW_OPCODE_ADD
;
1062 if_inst
->header
.predicate_inverse
= 1;
1064 if (else_inst
!= NULL
) {
1065 /* Convert ELSE to an ADD instruction that points where the ENDIF
1068 else_inst
->header
.opcode
= BRW_OPCODE_ADD
;
1070 if_inst
->bits3
.ud
= (else_inst
- if_inst
+ 1) * 16;
1071 else_inst
->bits3
.ud
= (next_inst
- else_inst
) * 16;
1073 if_inst
->bits3
.ud
= (next_inst
- if_inst
) * 16;
1078 * Patch IF and ELSE instructions with appropriate jump targets.
1081 patch_IF_ELSE(struct brw_compile
*p
,
1082 struct brw_instruction
*if_inst
,
1083 struct brw_instruction
*else_inst
,
1084 struct brw_instruction
*endif_inst
)
1086 struct intel_context
*intel
= &p
->brw
->intel
;
1088 /* We shouldn't be patching IF and ELSE instructions in single program flow
1089 * mode when gen < 6, because in single program flow mode on those
1090 * platforms, we convert flow control instructions to conditional ADDs that
1091 * operate on IP (see brw_ENDIF).
1093 * However, on Gen6, writing to IP doesn't work in single program flow mode
1094 * (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
1095 * not be updated by non-flow control instructions."). And on later
1096 * platforms, there is no significant benefit to converting control flow
1097 * instructions to conditional ADDs. So we do patch IF and ELSE
1098 * instructions in single program flow mode on those platforms.
1101 assert(!p
->single_program_flow
);
1103 assert(if_inst
!= NULL
&& if_inst
->header
.opcode
== BRW_OPCODE_IF
);
1104 assert(endif_inst
!= NULL
);
1105 assert(else_inst
== NULL
|| else_inst
->header
.opcode
== BRW_OPCODE_ELSE
);
1108 /* Jump count is for 64bit data chunk each, so one 128bit instruction
1109 * requires 2 chunks.
1111 if (intel
->gen
>= 5)
1114 assert(endif_inst
->header
.opcode
== BRW_OPCODE_ENDIF
);
1115 endif_inst
->header
.execution_size
= if_inst
->header
.execution_size
;
1117 if (else_inst
== NULL
) {
1118 /* Patch IF -> ENDIF */
1119 if (intel
->gen
< 6) {
1120 /* Turn it into an IFF, which means no mask stack operations for
1121 * all-false and jumping past the ENDIF.
1123 if_inst
->header
.opcode
= BRW_OPCODE_IFF
;
1124 if_inst
->bits3
.if_else
.jump_count
= br
* (endif_inst
- if_inst
+ 1);
1125 if_inst
->bits3
.if_else
.pop_count
= 0;
1126 if_inst
->bits3
.if_else
.pad0
= 0;
1127 } else if (intel
->gen
== 6) {
1128 /* As of gen6, there is no IFF and IF must point to the ENDIF. */
1129 if_inst
->bits1
.branch_gen6
.jump_count
= br
* (endif_inst
- if_inst
);
1131 if_inst
->bits3
.break_cont
.uip
= br
* (endif_inst
- if_inst
);
1132 if_inst
->bits3
.break_cont
.jip
= br
* (endif_inst
- if_inst
);
1135 else_inst
->header
.execution_size
= if_inst
->header
.execution_size
;
1137 /* Patch IF -> ELSE */
1138 if (intel
->gen
< 6) {
1139 if_inst
->bits3
.if_else
.jump_count
= br
* (else_inst
- if_inst
);
1140 if_inst
->bits3
.if_else
.pop_count
= 0;
1141 if_inst
->bits3
.if_else
.pad0
= 0;
1142 } else if (intel
->gen
== 6) {
1143 if_inst
->bits1
.branch_gen6
.jump_count
= br
* (else_inst
- if_inst
+ 1);
1146 /* Patch ELSE -> ENDIF */
1147 if (intel
->gen
< 6) {
1148 /* BRW_OPCODE_ELSE pre-gen6 should point just past the
1151 else_inst
->bits3
.if_else
.jump_count
= br
*(endif_inst
- else_inst
+ 1);
1152 else_inst
->bits3
.if_else
.pop_count
= 1;
1153 else_inst
->bits3
.if_else
.pad0
= 0;
1154 } else if (intel
->gen
== 6) {
1155 /* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */
1156 else_inst
->bits1
.branch_gen6
.jump_count
= br
*(endif_inst
- else_inst
);
1158 /* The IF instruction's JIP should point just past the ELSE */
1159 if_inst
->bits3
.break_cont
.jip
= br
* (else_inst
- if_inst
+ 1);
1160 /* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
1161 if_inst
->bits3
.break_cont
.uip
= br
* (endif_inst
- if_inst
);
1162 else_inst
->bits3
.break_cont
.jip
= br
* (endif_inst
- else_inst
);
1168 brw_ELSE(struct brw_compile
*p
)
1170 struct intel_context
*intel
= &p
->brw
->intel
;
1171 struct brw_instruction
*insn
;
1173 insn
= next_insn(p
, BRW_OPCODE_ELSE
);
1175 if (intel
->gen
< 6) {
1176 brw_set_dest(p
, insn
, brw_ip_reg());
1177 brw_set_src0(p
, insn
, brw_ip_reg());
1178 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1179 } else if (intel
->gen
== 6) {
1180 brw_set_dest(p
, insn
, brw_imm_w(0));
1181 insn
->bits1
.branch_gen6
.jump_count
= 0;
1182 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1183 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1185 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1186 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1187 brw_set_src1(p
, insn
, brw_imm_ud(0));
1188 insn
->bits3
.break_cont
.jip
= 0;
1189 insn
->bits3
.break_cont
.uip
= 0;
1192 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1193 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
1194 if (!p
->single_program_flow
)
1195 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
1197 push_if_stack(p
, insn
);
1201 brw_ENDIF(struct brw_compile
*p
)
1203 struct intel_context
*intel
= &p
->brw
->intel
;
1204 struct brw_instruction
*insn
= NULL
;
1205 struct brw_instruction
*else_inst
= NULL
;
1206 struct brw_instruction
*if_inst
= NULL
;
1207 struct brw_instruction
*tmp
;
1208 bool emit_endif
= true;
1210 /* In single program flow mode, we can express IF and ELSE instructions
1211 * equivalently as ADD instructions that operate on IP. On platforms prior
1212 * to Gen6, flow control instructions cause an implied thread switch, so
1213 * this is a significant savings.
1215 * However, on Gen6, writing to IP doesn't work in single program flow mode
1216 * (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
1217 * not be updated by non-flow control instructions."). And on later
1218 * platforms, there is no significant benefit to converting control flow
1219 * instructions to conditional ADDs. So we only do this trick on Gen4 and
1222 if (intel
->gen
< 6 && p
->single_program_flow
)
1226 * A single next_insn() may change the base adress of instruction store
1227 * memory(p->store), so call it first before referencing the instruction
1228 * store pointer from an index
1231 insn
= next_insn(p
, BRW_OPCODE_ENDIF
);
1233 /* Pop the IF and (optional) ELSE instructions from the stack */
1234 p
->if_depth_in_loop
[p
->loop_stack_depth
]--;
1235 tmp
= pop_if_stack(p
);
1236 if (tmp
->header
.opcode
== BRW_OPCODE_ELSE
) {
1238 tmp
= pop_if_stack(p
);
1243 /* ENDIF is useless; don't bother emitting it. */
1244 convert_IF_ELSE_to_ADD(p
, if_inst
, else_inst
);
1248 if (intel
->gen
< 6) {
1249 brw_set_dest(p
, insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
1250 brw_set_src0(p
, insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
1251 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1252 } else if (intel
->gen
== 6) {
1253 brw_set_dest(p
, insn
, brw_imm_w(0));
1254 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1255 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1257 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1258 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1259 brw_set_src1(p
, insn
, brw_imm_ud(0));
1262 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1263 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
1264 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
1266 /* Also pop item off the stack in the endif instruction: */
1267 if (intel
->gen
< 6) {
1268 insn
->bits3
.if_else
.jump_count
= 0;
1269 insn
->bits3
.if_else
.pop_count
= 1;
1270 insn
->bits3
.if_else
.pad0
= 0;
1271 } else if (intel
->gen
== 6) {
1272 insn
->bits1
.branch_gen6
.jump_count
= 2;
1274 insn
->bits3
.break_cont
.jip
= 2;
1276 patch_IF_ELSE(p
, if_inst
, else_inst
, insn
);
1279 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
)
1281 struct intel_context
*intel
= &p
->brw
->intel
;
1282 struct brw_instruction
*insn
;
1284 insn
= next_insn(p
, BRW_OPCODE_BREAK
);
1285 if (intel
->gen
>= 6) {
1286 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1287 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1288 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1290 brw_set_dest(p
, insn
, brw_ip_reg());
1291 brw_set_src0(p
, insn
, brw_ip_reg());
1292 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1293 insn
->bits3
.if_else
.pad0
= 0;
1294 insn
->bits3
.if_else
.pop_count
= p
->if_depth_in_loop
[p
->loop_stack_depth
];
1296 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1297 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1302 struct brw_instruction
*gen6_CONT(struct brw_compile
*p
)
1304 struct brw_instruction
*insn
;
1306 insn
= next_insn(p
, BRW_OPCODE_CONTINUE
);
1307 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1308 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1309 brw_set_dest(p
, insn
, brw_ip_reg());
1310 brw_set_src0(p
, insn
, brw_ip_reg());
1311 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1313 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1314 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1318 struct brw_instruction
*brw_CONT(struct brw_compile
*p
)
1320 struct brw_instruction
*insn
;
1321 insn
= next_insn(p
, BRW_OPCODE_CONTINUE
);
1322 brw_set_dest(p
, insn
, brw_ip_reg());
1323 brw_set_src0(p
, insn
, brw_ip_reg());
1324 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1325 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1326 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1327 /* insn->header.mask_control = BRW_MASK_DISABLE; */
1328 insn
->bits3
.if_else
.pad0
= 0;
1329 insn
->bits3
.if_else
.pop_count
= p
->if_depth_in_loop
[p
->loop_stack_depth
];
1335 * The DO/WHILE is just an unterminated loop -- break or continue are
1336 * used for control within the loop. We have a few ways they can be
1339 * For uniform control flow, the WHILE is just a jump, so ADD ip, ip,
1340 * jip and no DO instruction.
1342 * For non-uniform control flow pre-gen6, there's a DO instruction to
1343 * push the mask, and a WHILE to jump back, and BREAK to get out and
1346 * For gen6, there's no more mask stack, so no need for DO. WHILE
1347 * just points back to the first instruction of the loop.
1349 struct brw_instruction
*brw_DO(struct brw_compile
*p
, GLuint execute_size
)
1351 struct intel_context
*intel
= &p
->brw
->intel
;
1353 if (intel
->gen
>= 6 || p
->single_program_flow
) {
1354 push_loop_stack(p
, &p
->store
[p
->nr_insn
]);
1355 return &p
->store
[p
->nr_insn
];
1357 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_DO
);
1359 push_loop_stack(p
, insn
);
1361 /* Override the defaults for this instruction:
1363 brw_set_dest(p
, insn
, brw_null_reg());
1364 brw_set_src0(p
, insn
, brw_null_reg());
1365 brw_set_src1(p
, insn
, brw_null_reg());
1367 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1368 insn
->header
.execution_size
= execute_size
;
1369 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1370 /* insn->header.mask_control = BRW_MASK_ENABLE; */
1371 /* insn->header.mask_control = BRW_MASK_DISABLE; */
1378 * For pre-gen6, we patch BREAK/CONT instructions to point at the WHILE
1381 * For gen6+, see brw_set_uip_jip(), which doesn't care so much about the loop
1382 * nesting, since it can always just point to the end of the block/current loop.
1385 brw_patch_break_cont(struct brw_compile
*p
, struct brw_instruction
*while_inst
)
1387 struct intel_context
*intel
= &p
->brw
->intel
;
1388 struct brw_instruction
*do_inst
= get_inner_do_insn(p
);
1389 struct brw_instruction
*inst
;
1390 int br
= (intel
->gen
== 5) ? 2 : 1;
1392 for (inst
= while_inst
- 1; inst
!= do_inst
; inst
--) {
1393 /* If the jump count is != 0, that means that this instruction has already
1394 * been patched because it's part of a loop inside of the one we're
1397 if (inst
->header
.opcode
== BRW_OPCODE_BREAK
&&
1398 inst
->bits3
.if_else
.jump_count
== 0) {
1399 inst
->bits3
.if_else
.jump_count
= br
* ((while_inst
- inst
) + 1);
1400 } else if (inst
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
1401 inst
->bits3
.if_else
.jump_count
== 0) {
1402 inst
->bits3
.if_else
.jump_count
= br
* (while_inst
- inst
);
1407 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
)
1409 struct intel_context
*intel
= &p
->brw
->intel
;
1410 struct brw_instruction
*insn
, *do_insn
;
1413 if (intel
->gen
>= 5)
1416 if (intel
->gen
>= 7) {
1417 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
1418 do_insn
= get_inner_do_insn(p
);
1420 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1421 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1422 brw_set_src1(p
, insn
, brw_imm_ud(0));
1423 insn
->bits3
.break_cont
.jip
= br
* (do_insn
- insn
);
1425 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1426 } else if (intel
->gen
== 6) {
1427 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
1428 do_insn
= get_inner_do_insn(p
);
1430 brw_set_dest(p
, insn
, brw_imm_w(0));
1431 insn
->bits1
.branch_gen6
.jump_count
= br
* (do_insn
- insn
);
1432 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1433 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1435 insn
->header
.execution_size
= BRW_EXECUTE_8
;
1437 if (p
->single_program_flow
) {
1438 insn
= next_insn(p
, BRW_OPCODE_ADD
);
1439 do_insn
= get_inner_do_insn(p
);
1441 brw_set_dest(p
, insn
, brw_ip_reg());
1442 brw_set_src0(p
, insn
, brw_ip_reg());
1443 brw_set_src1(p
, insn
, brw_imm_d((do_insn
- insn
) * 16));
1444 insn
->header
.execution_size
= BRW_EXECUTE_1
;
1446 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
1447 do_insn
= get_inner_do_insn(p
);
1449 assert(do_insn
->header
.opcode
== BRW_OPCODE_DO
);
1451 brw_set_dest(p
, insn
, brw_ip_reg());
1452 brw_set_src0(p
, insn
, brw_ip_reg());
1453 brw_set_src1(p
, insn
, brw_imm_d(0));
1455 insn
->header
.execution_size
= do_insn
->header
.execution_size
;
1456 insn
->bits3
.if_else
.jump_count
= br
* (do_insn
- insn
+ 1);
1457 insn
->bits3
.if_else
.pop_count
= 0;
1458 insn
->bits3
.if_else
.pad0
= 0;
1460 brw_patch_break_cont(p
, insn
);
1463 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1464 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1466 p
->loop_stack_depth
--;
1474 void brw_land_fwd_jump(struct brw_compile
*p
, int jmp_insn_idx
)
1476 struct intel_context
*intel
= &p
->brw
->intel
;
1477 struct brw_instruction
*jmp_insn
= &p
->store
[jmp_insn_idx
];
1480 if (intel
->gen
>= 5)
1483 assert(jmp_insn
->header
.opcode
== BRW_OPCODE_JMPI
);
1484 assert(jmp_insn
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
);
1486 jmp_insn
->bits3
.ud
= jmpi
* (p
->nr_insn
- jmp_insn_idx
- 1);
1491 /* To integrate with the above, it makes sense that the comparison
1492 * instruction should populate the flag register. It might be simpler
1493 * just to use the flag reg for most WM tasks?
1495 void brw_CMP(struct brw_compile
*p
,
1496 struct brw_reg dest
,
1498 struct brw_reg src0
,
1499 struct brw_reg src1
)
1501 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_CMP
);
1503 insn
->header
.destreg__conditionalmod
= conditional
;
1504 brw_set_dest(p
, insn
, dest
);
1505 brw_set_src0(p
, insn
, src0
);
1506 brw_set_src1(p
, insn
, src1
);
1508 /* guess_execution_size(insn, src0); */
1511 /* Make it so that future instructions will use the computed flag
1512 * value until brw_set_predicate_control_flag_value() is called
1515 if (dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
1517 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
1518 p
->flag_value
= 0xff;
1522 /* Issue 'wait' instruction for n1, host could program MMIO
1523 to wake up thread. */
1524 void brw_WAIT (struct brw_compile
*p
)
1526 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_WAIT
);
1527 struct brw_reg src
= brw_notification_1_reg();
1529 brw_set_dest(p
, insn
, src
);
1530 brw_set_src0(p
, insn
, src
);
1531 brw_set_src1(p
, insn
, brw_null_reg());
1532 insn
->header
.execution_size
= 0; /* must */
1533 insn
->header
.predicate_control
= 0;
1534 insn
->header
.compression_control
= 0;
1538 /***********************************************************************
1539 * Helpers for the various SEND message types:
1542 /** Extended math function, float[8].
1544 void brw_math( struct brw_compile
*p
,
1545 struct brw_reg dest
,
1553 struct intel_context
*intel
= &p
->brw
->intel
;
1555 if (intel
->gen
>= 6) {
1556 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
1558 assert(dest
.file
== BRW_GENERAL_REGISTER_FILE
);
1559 assert(src
.file
== BRW_GENERAL_REGISTER_FILE
);
1561 assert(dest
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1562 if (intel
->gen
== 6)
1563 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1565 /* Source modifiers are ignored for extended math instructions on Gen6. */
1566 if (intel
->gen
== 6) {
1567 assert(!src
.negate
);
1571 if (function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
||
1572 function
== BRW_MATH_FUNCTION_INT_DIV_REMAINDER
||
1573 function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
) {
1574 assert(src
.type
!= BRW_REGISTER_TYPE_F
);
1576 assert(src
.type
== BRW_REGISTER_TYPE_F
);
1579 /* Math is the same ISA format as other opcodes, except that CondModifier
1580 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1582 insn
->header
.destreg__conditionalmod
= function
;
1583 insn
->header
.saturate
= saturate
;
1585 brw_set_dest(p
, insn
, dest
);
1586 brw_set_src0(p
, insn
, src
);
1587 brw_set_src1(p
, insn
, brw_null_reg());
1589 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1591 /* Example code doesn't set predicate_control for send
1594 insn
->header
.predicate_control
= 0;
1595 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1597 brw_set_dest(p
, insn
, dest
);
1598 brw_set_src0(p
, insn
, src
);
1599 brw_set_math_message(p
,
1602 src
.type
== BRW_REGISTER_TYPE_D
,
1609 /** Extended math function, float[8].
1611 void brw_math2(struct brw_compile
*p
,
1612 struct brw_reg dest
,
1614 struct brw_reg src0
,
1615 struct brw_reg src1
)
1617 struct intel_context
*intel
= &p
->brw
->intel
;
1618 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
1620 assert(intel
->gen
>= 6);
1624 assert(dest
.file
== BRW_GENERAL_REGISTER_FILE
);
1625 assert(src0
.file
== BRW_GENERAL_REGISTER_FILE
);
1626 assert(src1
.file
== BRW_GENERAL_REGISTER_FILE
);
1628 assert(dest
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1629 if (intel
->gen
== 6) {
1630 assert(src0
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1631 assert(src1
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1634 if (function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
||
1635 function
== BRW_MATH_FUNCTION_INT_DIV_REMAINDER
||
1636 function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
) {
1637 assert(src0
.type
!= BRW_REGISTER_TYPE_F
);
1638 assert(src1
.type
!= BRW_REGISTER_TYPE_F
);
1640 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
1641 assert(src1
.type
== BRW_REGISTER_TYPE_F
);
1644 /* Source modifiers are ignored for extended math instructions on Gen6. */
1645 if (intel
->gen
== 6) {
1646 assert(!src0
.negate
);
1648 assert(!src1
.negate
);
1652 /* Math is the same ISA format as other opcodes, except that CondModifier
1653 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1655 insn
->header
.destreg__conditionalmod
= function
;
1657 brw_set_dest(p
, insn
, dest
);
1658 brw_set_src0(p
, insn
, src0
);
1659 brw_set_src1(p
, insn
, src1
);
1663 * Extended math function, float[16].
1664 * Use 2 send instructions.
1666 void brw_math_16( struct brw_compile
*p
,
1667 struct brw_reg dest
,
1674 struct intel_context
*intel
= &p
->brw
->intel
;
1675 struct brw_instruction
*insn
;
1677 if (intel
->gen
>= 6) {
1678 insn
= next_insn(p
, BRW_OPCODE_MATH
);
1680 /* Math is the same ISA format as other opcodes, except that CondModifier
1681 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1683 insn
->header
.destreg__conditionalmod
= function
;
1684 insn
->header
.saturate
= saturate
;
1686 /* Source modifiers are ignored for extended math instructions. */
1687 assert(!src
.negate
);
1690 brw_set_dest(p
, insn
, dest
);
1691 brw_set_src0(p
, insn
, src
);
1692 brw_set_src1(p
, insn
, brw_null_reg());
1696 /* First instruction:
1698 brw_push_insn_state(p
);
1699 brw_set_predicate_control_flag_value(p
, 0xff);
1700 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1702 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1703 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1705 brw_set_dest(p
, insn
, dest
);
1706 brw_set_src0(p
, insn
, src
);
1707 brw_set_math_message(p
,
1710 BRW_MATH_INTEGER_UNSIGNED
,
1713 BRW_MATH_DATA_VECTOR
);
1715 /* Second instruction:
1717 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1718 insn
->header
.compression_control
= BRW_COMPRESSION_2NDHALF
;
1719 insn
->header
.destreg__conditionalmod
= msg_reg_nr
+1;
1721 brw_set_dest(p
, insn
, offset(dest
,1));
1722 brw_set_src0(p
, insn
, src
);
1723 brw_set_math_message(p
,
1726 BRW_MATH_INTEGER_UNSIGNED
,
1729 BRW_MATH_DATA_VECTOR
);
1731 brw_pop_insn_state(p
);
1736 * Write a block of OWORDs (half a GRF each) from the scratch buffer,
1737 * using a constant offset per channel.
1739 * The offset must be aligned to oword size (16 bytes). Used for
1740 * register spilling.
1742 void brw_oword_block_write_scratch(struct brw_compile
*p
,
1747 struct intel_context
*intel
= &p
->brw
->intel
;
1748 uint32_t msg_control
, msg_type
;
1751 if (intel
->gen
>= 6)
1754 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
1756 if (num_regs
== 1) {
1757 msg_control
= BRW_DATAPORT_OWORD_BLOCK_2_OWORDS
;
1760 msg_control
= BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
;
1764 /* Set up the message header. This is g0, with g0.2 filled with
1765 * the offset. We don't want to leave our offset around in g0 or
1766 * it'll screw up texture samples, so set it up inside the message
1770 brw_push_insn_state(p
);
1771 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1772 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1774 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1776 /* set message header global offset field (reg 0, element 2) */
1778 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
1780 2), BRW_REGISTER_TYPE_UD
),
1781 brw_imm_ud(offset
));
1783 brw_pop_insn_state(p
);
1787 struct brw_reg dest
;
1788 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1789 int send_commit_msg
;
1790 struct brw_reg src_header
= retype(brw_vec8_grf(0, 0),
1791 BRW_REGISTER_TYPE_UW
);
1793 if (insn
->header
.compression_control
!= BRW_COMPRESSION_NONE
) {
1794 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1795 src_header
= vec16(src_header
);
1797 assert(insn
->header
.predicate_control
== BRW_PREDICATE_NONE
);
1798 insn
->header
.destreg__conditionalmod
= mrf
.nr
;
1800 /* Until gen6, writes followed by reads from the same location
1801 * are not guaranteed to be ordered unless write_commit is set.
1802 * If set, then a no-op write is issued to the destination
1803 * register to set a dependency, and a read from the destination
1804 * can be used to ensure the ordering.
1806 * For gen6, only writes between different threads need ordering
1807 * protection. Our use of DP writes is all about register
1808 * spilling within a thread.
1810 if (intel
->gen
>= 6) {
1811 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
1812 send_commit_msg
= 0;
1815 send_commit_msg
= 1;
1818 brw_set_dest(p
, insn
, dest
);
1819 if (intel
->gen
>= 6) {
1820 brw_set_src0(p
, insn
, mrf
);
1822 brw_set_src0(p
, insn
, brw_null_reg());
1825 if (intel
->gen
>= 6)
1826 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
;
1828 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
;
1830 brw_set_dp_write_message(p
,
1832 255, /* binding table index (255=stateless) */
1836 true, /* header_present */
1837 0, /* not a render target */
1838 send_commit_msg
, /* response_length */
1846 * Read a block of owords (half a GRF each) from the scratch buffer
1847 * using a constant index per channel.
1849 * Offset must be aligned to oword size (16 bytes). Used for register
1853 brw_oword_block_read_scratch(struct brw_compile
*p
,
1854 struct brw_reg dest
,
1859 struct intel_context
*intel
= &p
->brw
->intel
;
1860 uint32_t msg_control
;
1863 if (intel
->gen
>= 6)
1866 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
1867 dest
= retype(dest
, BRW_REGISTER_TYPE_UW
);
1869 if (num_regs
== 1) {
1870 msg_control
= BRW_DATAPORT_OWORD_BLOCK_2_OWORDS
;
1873 msg_control
= BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
;
1878 brw_push_insn_state(p
);
1879 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1880 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1882 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1884 /* set message header global offset field (reg 0, element 2) */
1886 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
1888 2), BRW_REGISTER_TYPE_UD
),
1889 brw_imm_ud(offset
));
1891 brw_pop_insn_state(p
);
1895 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1897 assert(insn
->header
.predicate_control
== 0);
1898 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1899 insn
->header
.destreg__conditionalmod
= mrf
.nr
;
1901 brw_set_dest(p
, insn
, dest
); /* UW? */
1902 if (intel
->gen
>= 6) {
1903 brw_set_src0(p
, insn
, mrf
);
1905 brw_set_src0(p
, insn
, brw_null_reg());
1908 brw_set_dp_read_message(p
,
1910 255, /* binding table index (255=stateless) */
1912 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1913 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
1920 * Read a float[4] vector from the data port Data Cache (const buffer).
1921 * Location (in buffer) should be a multiple of 16.
1922 * Used for fetching shader constants.
1924 void brw_oword_block_read(struct brw_compile
*p
,
1925 struct brw_reg dest
,
1928 uint32_t bind_table_index
)
1930 struct intel_context
*intel
= &p
->brw
->intel
;
1932 /* On newer hardware, offset is in units of owords. */
1933 if (intel
->gen
>= 6)
1936 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
1938 brw_push_insn_state(p
);
1939 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1940 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1941 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1943 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1945 /* set message header global offset field (reg 0, element 2) */
1947 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
1949 2), BRW_REGISTER_TYPE_UD
),
1950 brw_imm_ud(offset
));
1952 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1953 insn
->header
.destreg__conditionalmod
= mrf
.nr
;
1955 /* cast dest to a uword[8] vector */
1956 dest
= retype(vec8(dest
), BRW_REGISTER_TYPE_UW
);
1958 brw_set_dest(p
, insn
, dest
);
1959 if (intel
->gen
>= 6) {
1960 brw_set_src0(p
, insn
, mrf
);
1962 brw_set_src0(p
, insn
, brw_null_reg());
1965 brw_set_dp_read_message(p
,
1968 BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW
,
1969 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
,
1970 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
1972 1); /* response_length (1 reg, 2 owords!) */
1974 brw_pop_insn_state(p
);
1978 * Read a set of dwords from the data port Data Cache (const buffer).
1980 * Location (in buffer) appears as UD offsets in the register after
1981 * the provided mrf header reg.
1983 void brw_dword_scattered_read(struct brw_compile
*p
,
1984 struct brw_reg dest
,
1986 uint32_t bind_table_index
)
1988 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
1990 brw_push_insn_state(p
);
1991 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1992 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1993 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1994 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1995 brw_pop_insn_state(p
);
1997 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1998 insn
->header
.destreg__conditionalmod
= mrf
.nr
;
2000 /* cast dest to a uword[8] vector */
2001 dest
= retype(vec8(dest
), BRW_REGISTER_TYPE_UW
);
2003 brw_set_dest(p
, insn
, dest
);
2004 brw_set_src0(p
, insn
, brw_null_reg());
2006 brw_set_dp_read_message(p
,
2009 BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS
,
2010 BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
,
2011 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
2013 1); /* response_length */
2019 * Read float[4] constant(s) from VS constant buffer.
2020 * For relative addressing, two float[4] constants will be read into 'dest'.
2021 * Otherwise, one float[4] constant will be read into the lower half of 'dest'.
2023 void brw_dp_READ_4_vs(struct brw_compile
*p
,
2024 struct brw_reg dest
,
2026 GLuint bind_table_index
)
2028 struct intel_context
*intel
= &p
->brw
->intel
;
2029 struct brw_instruction
*insn
;
2030 GLuint msg_reg_nr
= 1;
2032 if (intel
->gen
>= 6)
2035 /* Setup MRF[1] with location/offset into const buffer */
2036 brw_push_insn_state(p
);
2037 brw_set_access_mode(p
, BRW_ALIGN_1
);
2038 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2039 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2040 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2041 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, msg_reg_nr
, 2),
2042 BRW_REGISTER_TYPE_UD
),
2043 brw_imm_ud(location
));
2044 brw_pop_insn_state(p
);
2046 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2048 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
2049 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
2050 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
2051 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
2053 brw_set_dest(p
, insn
, dest
);
2054 if (intel
->gen
>= 6) {
2055 brw_set_src0(p
, insn
, brw_message_reg(msg_reg_nr
));
2057 brw_set_src0(p
, insn
, brw_null_reg());
2060 brw_set_dp_read_message(p
,
2064 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
2065 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
2067 1); /* response_length (1 Oword) */
2071 * Read a float[4] constant per vertex from VS constant buffer, with
2072 * relative addressing.
2074 void brw_dp_READ_4_vs_relative(struct brw_compile
*p
,
2075 struct brw_reg dest
,
2076 struct brw_reg addr_reg
,
2078 GLuint bind_table_index
)
2080 struct intel_context
*intel
= &p
->brw
->intel
;
2081 struct brw_reg src
= brw_vec8_grf(0, 0);
2084 /* Setup MRF[1] with offset into const buffer */
2085 brw_push_insn_state(p
);
2086 brw_set_access_mode(p
, BRW_ALIGN_1
);
2087 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2088 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2089 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2091 /* M1.0 is block offset 0, M1.4 is block offset 1, all other
2094 brw_ADD(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_D
),
2095 addr_reg
, brw_imm_d(offset
));
2096 brw_pop_insn_state(p
);
2098 gen6_resolve_implied_move(p
, &src
, 0);
2099 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
2101 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
2102 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
2103 insn
->header
.destreg__conditionalmod
= 0;
2104 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
2106 brw_set_dest(p
, insn
, dest
);
2107 brw_set_src0(p
, insn
, src
);
2109 if (intel
->gen
>= 6)
2110 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
2111 else if (intel
->gen
== 5 || intel
->is_g4x
)
2112 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
2114 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
2116 brw_set_dp_read_message(p
,
2119 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
2121 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
2123 1); /* response_length */
2128 void brw_fb_WRITE(struct brw_compile
*p
,
2131 struct brw_reg src0
,
2132 GLuint binding_table_index
,
2134 GLuint response_length
,
2136 bool header_present
)
2138 struct intel_context
*intel
= &p
->brw
->intel
;
2139 struct brw_instruction
*insn
;
2140 GLuint msg_control
, msg_type
;
2141 struct brw_reg dest
;
2143 if (dispatch_width
== 16)
2144 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
2146 dest
= retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
2148 if (intel
->gen
>= 6 && binding_table_index
== 0) {
2149 insn
= next_insn(p
, BRW_OPCODE_SENDC
);
2151 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2153 /* The execution mask is ignored for render target writes. */
2154 insn
->header
.predicate_control
= 0;
2155 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
2157 if (intel
->gen
>= 6) {
2158 /* headerless version, just submit color payload */
2159 src0
= brw_message_reg(msg_reg_nr
);
2161 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
2163 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
2165 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
2168 if (dispatch_width
== 16)
2169 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
2171 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
2173 brw_set_dest(p
, insn
, dest
);
2174 brw_set_src0(p
, insn
, src0
);
2175 brw_set_dp_write_message(p
,
2177 binding_table_index
,
2182 1, /* last render target write */
2185 0 /* send_commit_msg */);
2190 * Texture sample instruction.
2191 * Note: the msg_type plus msg_length values determine exactly what kind
2192 * of sampling operation is performed. See volume 4, page 161 of docs.
2194 void brw_SAMPLE(struct brw_compile
*p
,
2195 struct brw_reg dest
,
2197 struct brw_reg src0
,
2198 GLuint binding_table_index
,
2202 GLuint response_length
,
2204 GLuint header_present
,
2206 GLuint return_format
)
2208 struct intel_context
*intel
= &p
->brw
->intel
;
2209 bool need_stall
= 0;
2211 if (writemask
== 0) {
2212 /*printf("%s: zero writemask??\n", __FUNCTION__); */
2216 /* Hardware doesn't do destination dependency checking on send
2217 * instructions properly. Add a workaround which generates the
2218 * dependency by other means. In practice it seems like this bug
2219 * only crops up for texture samples, and only where registers are
2220 * written by the send and then written again later without being
2221 * read in between. Luckily for us, we already track that
2222 * information and use it to modify the writemask for the
2223 * instruction, so that is a guide for whether a workaround is
2226 if (writemask
!= WRITEMASK_XYZW
) {
2227 GLuint dst_offset
= 0;
2228 GLuint i
, newmask
= 0, len
= 0;
2230 for (i
= 0; i
< 4; i
++) {
2231 if (writemask
& (1<<i
))
2235 for (; i
< 4; i
++) {
2236 if (!(writemask
& (1<<i
)))
2242 if (newmask
!= writemask
) {
2244 /* printf("need stall %x %x\n", newmask , writemask); */
2247 bool dispatch_16
= false;
2249 struct brw_reg m1
= brw_message_reg(msg_reg_nr
);
2251 guess_execution_size(p
, p
->current
, dest
);
2252 if (p
->current
->header
.execution_size
== BRW_EXECUTE_16
)
2255 newmask
= ~newmask
& WRITEMASK_XYZW
;
2257 brw_push_insn_state(p
);
2259 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2260 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2262 brw_MOV(p
, retype(m1
, BRW_REGISTER_TYPE_UD
),
2263 retype(brw_vec8_grf(0,0), BRW_REGISTER_TYPE_UD
));
2264 brw_MOV(p
, get_element_ud(m1
, 2), brw_imm_ud(newmask
<< 12));
2266 brw_pop_insn_state(p
);
2268 src0
= retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
);
2269 dest
= offset(dest
, dst_offset
);
2271 /* For 16-wide dispatch, masked channels are skipped in the
2272 * response. For 8-wide, masked channels still take up slots,
2273 * and are just not written to.
2276 response_length
= len
* 2;
2281 struct brw_instruction
*insn
;
2283 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2285 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2286 insn
->header
.predicate_control
= 0; /* XXX */
2287 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
2289 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
2291 brw_set_dest(p
, insn
, dest
);
2292 brw_set_src0(p
, insn
, src0
);
2293 brw_set_sampler_message(p
, insn
,
2294 binding_table_index
,
2305 struct brw_reg reg
= vec8(offset(dest
, response_length
-1));
2307 /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 }
2309 brw_push_insn_state(p
);
2310 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
2311 brw_MOV(p
, retype(reg
, BRW_REGISTER_TYPE_UD
),
2312 retype(reg
, BRW_REGISTER_TYPE_UD
));
2313 brw_pop_insn_state(p
);
2318 /* All these variables are pretty confusing - we might be better off
2319 * using bitmasks and macros for this, in the old style. Or perhaps
2320 * just having the caller instantiate the fields in dword3 itself.
2322 void brw_urb_WRITE(struct brw_compile
*p
,
2323 struct brw_reg dest
,
2325 struct brw_reg src0
,
2329 GLuint response_length
,
2331 bool writes_complete
,
2335 struct intel_context
*intel
= &p
->brw
->intel
;
2336 struct brw_instruction
*insn
;
2338 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2340 if (intel
->gen
== 7) {
2341 /* Enable Channel Masks in the URB_WRITE_HWORD message header */
2342 brw_push_insn_state(p
);
2343 brw_set_access_mode(p
, BRW_ALIGN_1
);
2344 brw_OR(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, msg_reg_nr
, 5),
2345 BRW_REGISTER_TYPE_UD
),
2346 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
2347 brw_imm_ud(0xff00));
2348 brw_pop_insn_state(p
);
2351 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2353 assert(msg_length
< BRW_MAX_MRF
);
2355 brw_set_dest(p
, insn
, dest
);
2356 brw_set_src0(p
, insn
, src0
);
2357 brw_set_src1(p
, insn
, brw_imm_d(0));
2360 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
2362 brw_set_urb_message(p
,
2375 brw_find_next_block_end(struct brw_compile
*p
, int start
)
2379 for (ip
= start
+ 1; ip
< p
->nr_insn
; ip
++) {
2380 struct brw_instruction
*insn
= &p
->store
[ip
];
2382 switch (insn
->header
.opcode
) {
2383 case BRW_OPCODE_ENDIF
:
2384 case BRW_OPCODE_ELSE
:
2385 case BRW_OPCODE_WHILE
:
2389 assert(!"not reached");
2393 /* There is no DO instruction on gen6, so to find the end of the loop
2394 * we have to see if the loop is jumping back before our start
2398 brw_find_loop_end(struct brw_compile
*p
, int start
)
2400 struct intel_context
*intel
= &p
->brw
->intel
;
2404 for (ip
= start
+ 1; ip
< p
->nr_insn
; ip
++) {
2405 struct brw_instruction
*insn
= &p
->store
[ip
];
2407 if (insn
->header
.opcode
== BRW_OPCODE_WHILE
) {
2408 int jip
= intel
->gen
== 6 ? insn
->bits1
.branch_gen6
.jump_count
2409 : insn
->bits3
.break_cont
.jip
;
2410 if (ip
+ jip
/ br
<= start
)
2414 assert(!"not reached");
2418 /* After program generation, go back and update the UIP and JIP of
2419 * BREAK and CONT instructions to their correct locations.
2422 brw_set_uip_jip(struct brw_compile
*p
)
2424 struct intel_context
*intel
= &p
->brw
->intel
;
2431 for (ip
= 0; ip
< p
->nr_insn
; ip
++) {
2432 struct brw_instruction
*insn
= &p
->store
[ip
];
2434 switch (insn
->header
.opcode
) {
2435 case BRW_OPCODE_BREAK
:
2436 insn
->bits3
.break_cont
.jip
= br
* (brw_find_next_block_end(p
, ip
) - ip
);
2437 /* Gen7 UIP points to WHILE; Gen6 points just after it */
2438 insn
->bits3
.break_cont
.uip
=
2439 br
* (brw_find_loop_end(p
, ip
) - ip
+ (intel
->gen
== 6 ? 1 : 0));
2441 case BRW_OPCODE_CONTINUE
:
2442 insn
->bits3
.break_cont
.jip
= br
* (brw_find_next_block_end(p
, ip
) - ip
);
2443 insn
->bits3
.break_cont
.uip
= br
* (brw_find_loop_end(p
, ip
) - ip
);
2445 assert(insn
->bits3
.break_cont
.uip
!= 0);
2446 assert(insn
->bits3
.break_cont
.jip
!= 0);
2452 void brw_ff_sync(struct brw_compile
*p
,
2453 struct brw_reg dest
,
2455 struct brw_reg src0
,
2457 GLuint response_length
,
2460 struct intel_context
*intel
= &p
->brw
->intel
;
2461 struct brw_instruction
*insn
;
2463 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2465 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2466 brw_set_dest(p
, insn
, dest
);
2467 brw_set_src0(p
, insn
, src0
);
2468 brw_set_src1(p
, insn
, brw_imm_d(0));
2471 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
2473 brw_set_ff_sync_message(p
,
2481 * Emit the SEND instruction necessary to generate stream output data on Gen6
2482 * (for transform feedback).
2484 * If send_commit_msg is true, this is the last piece of stream output data
2485 * from this thread, so send the data as a committed write. According to the
2486 * Sandy Bridge PRM (volume 2 part 1, section 4.5.1):
2488 * "Prior to End of Thread with a URB_WRITE, the kernel must ensure all
2489 * writes are complete by sending the final write as a committed write."
2492 brw_svb_write(struct brw_compile
*p
,
2493 struct brw_reg dest
,
2495 struct brw_reg src0
,
2496 GLuint binding_table_index
,
2497 bool send_commit_msg
)
2499 struct brw_instruction
*insn
;
2501 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2503 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2504 brw_set_dest(p
, insn
, dest
);
2505 brw_set_src0(p
, insn
, src0
);
2506 brw_set_src1(p
, insn
, brw_imm_d(0));
2507 brw_set_dp_write_message(p
, insn
,
2508 binding_table_index
,
2509 0, /* msg_control: ignored */
2510 GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
,
2512 true, /* header_present */
2513 0, /* last_render_target: ignored */
2514 send_commit_msg
, /* response_length */
2515 0, /* end_of_thread */
2516 send_commit_msg
); /* send_commit_msg */