2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
34 #include "brw_defines.h"
40 /***********************************************************************
41 * Internal helper for constructing instructions
44 static void guess_execution_size( struct brw_instruction
*insn
,
47 if (reg
.width
== BRW_WIDTH_8
&&
48 insn
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
)
49 insn
->header
.execution_size
= BRW_EXECUTE_16
;
51 insn
->header
.execution_size
= reg
.width
; /* note - definitions are compatible */
55 static void brw_set_dest( struct brw_instruction
*insn
,
58 if (dest
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
&&
59 dest
.file
!= BRW_MESSAGE_REGISTER_FILE
)
60 assert(dest
.nr
< 128);
62 insn
->bits1
.da1
.dest_reg_file
= dest
.file
;
63 insn
->bits1
.da1
.dest_reg_type
= dest
.type
;
64 insn
->bits1
.da1
.dest_address_mode
= dest
.address_mode
;
66 if (dest
.address_mode
== BRW_ADDRESS_DIRECT
) {
67 insn
->bits1
.da1
.dest_reg_nr
= dest
.nr
;
69 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
70 insn
->bits1
.da1
.dest_subreg_nr
= dest
.subnr
;
71 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
72 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
73 insn
->bits1
.da1
.dest_horiz_stride
= dest
.hstride
;
76 insn
->bits1
.da16
.dest_subreg_nr
= dest
.subnr
/ 16;
77 insn
->bits1
.da16
.dest_writemask
= dest
.dw1
.bits
.writemask
;
78 /* even ignored in da16, still need to set as '01' */
79 insn
->bits1
.da16
.dest_horiz_stride
= 1;
83 insn
->bits1
.ia1
.dest_subreg_nr
= dest
.subnr
;
85 /* These are different sizes in align1 vs align16:
87 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
88 insn
->bits1
.ia1
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
89 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
90 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
91 insn
->bits1
.ia1
.dest_horiz_stride
= dest
.hstride
;
94 insn
->bits1
.ia16
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
95 /* even ignored in da16, still need to set as '01' */
96 insn
->bits1
.ia16
.dest_horiz_stride
= 1;
100 /* NEW: Set the execution size based on dest.width and
101 * insn->compression_control:
103 guess_execution_size(insn
, dest
);
106 extern int reg_type_size
[];
109 validate_reg(struct brw_instruction
*insn
, struct brw_reg reg
)
111 int hstride_for_reg
[] = {0, 1, 2, 4};
112 int vstride_for_reg
[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
113 int width_for_reg
[] = {1, 2, 4, 8, 16};
114 int execsize_for_reg
[] = {1, 2, 4, 8, 16};
115 int width
, hstride
, vstride
, execsize
;
117 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
118 /* 3.3.6: Region Parameters. Restriction: Immediate vectors
119 * mean the destination has to be 128-bit aligned and the
120 * destination horiz stride has to be a word.
122 if (reg
.type
== BRW_REGISTER_TYPE_V
) {
123 assert(hstride_for_reg
[insn
->bits1
.da1
.dest_horiz_stride
] *
124 reg_type_size
[insn
->bits1
.da1
.dest_reg_type
] == 2);
130 if (reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
131 reg
.file
== BRW_ARF_NULL
)
134 assert(reg
.hstride
>= 0 && reg
.hstride
< Elements(hstride_for_reg
));
135 hstride
= hstride_for_reg
[reg
.hstride
];
137 if (reg
.vstride
== 0xf) {
140 assert(reg
.vstride
>= 0 && reg
.vstride
< Elements(vstride_for_reg
));
141 vstride
= vstride_for_reg
[reg
.vstride
];
144 assert(reg
.width
>= 0 && reg
.width
< Elements(width_for_reg
));
145 width
= width_for_reg
[reg
.width
];
147 assert(insn
->header
.execution_size
>= 0 &&
148 insn
->header
.execution_size
< Elements(execsize_for_reg
));
149 execsize
= execsize_for_reg
[insn
->header
.execution_size
];
151 /* Restrictions from 3.3.10: Register Region Restrictions. */
153 assert(execsize
>= width
);
156 if (execsize
== width
&& hstride
!= 0) {
157 assert(vstride
== -1 || vstride
== width
* hstride
);
161 if (execsize
== width
&& hstride
== 0) {
162 /* no restriction on vstride. */
167 assert(hstride
== 0);
171 if (execsize
== 1 && width
== 1) {
172 assert(hstride
== 0);
173 assert(vstride
== 0);
177 if (vstride
== 0 && hstride
== 0) {
181 /* 10. Check destination issues. */
184 static void brw_set_src0( struct brw_instruction
*insn
,
187 if (reg
.type
!= BRW_ARCHITECTURE_REGISTER_FILE
)
188 assert(reg
.nr
< 128);
190 validate_reg(insn
, reg
);
192 insn
->bits1
.da1
.src0_reg_file
= reg
.file
;
193 insn
->bits1
.da1
.src0_reg_type
= reg
.type
;
194 insn
->bits2
.da1
.src0_abs
= reg
.abs
;
195 insn
->bits2
.da1
.src0_negate
= reg
.negate
;
196 insn
->bits2
.da1
.src0_address_mode
= reg
.address_mode
;
198 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
199 insn
->bits3
.ud
= reg
.dw1
.ud
;
201 /* Required to set some fields in src1 as well:
203 insn
->bits1
.da1
.src1_reg_file
= 0; /* arf */
204 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
208 if (reg
.address_mode
== BRW_ADDRESS_DIRECT
) {
209 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
210 insn
->bits2
.da1
.src0_subreg_nr
= reg
.subnr
;
211 insn
->bits2
.da1
.src0_reg_nr
= reg
.nr
;
214 insn
->bits2
.da16
.src0_subreg_nr
= reg
.subnr
/ 16;
215 insn
->bits2
.da16
.src0_reg_nr
= reg
.nr
;
219 insn
->bits2
.ia1
.src0_subreg_nr
= reg
.subnr
;
221 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
222 insn
->bits2
.ia1
.src0_indirect_offset
= reg
.dw1
.bits
.indirect_offset
;
225 insn
->bits2
.ia16
.src0_subreg_nr
= reg
.dw1
.bits
.indirect_offset
;
229 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
230 if (reg
.width
== BRW_WIDTH_1
&&
231 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
232 insn
->bits2
.da1
.src0_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
233 insn
->bits2
.da1
.src0_width
= BRW_WIDTH_1
;
234 insn
->bits2
.da1
.src0_vert_stride
= BRW_VERTICAL_STRIDE_0
;
237 insn
->bits2
.da1
.src0_horiz_stride
= reg
.hstride
;
238 insn
->bits2
.da1
.src0_width
= reg
.width
;
239 insn
->bits2
.da1
.src0_vert_stride
= reg
.vstride
;
243 insn
->bits2
.da16
.src0_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
244 insn
->bits2
.da16
.src0_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
245 insn
->bits2
.da16
.src0_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
246 insn
->bits2
.da16
.src0_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
248 /* This is an oddity of the fact we're using the same
249 * descriptions for registers in align_16 as align_1:
251 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
252 insn
->bits2
.da16
.src0_vert_stride
= BRW_VERTICAL_STRIDE_4
;
254 insn
->bits2
.da16
.src0_vert_stride
= reg
.vstride
;
260 void brw_set_src1( struct brw_instruction
*insn
,
263 assert(reg
.file
!= BRW_MESSAGE_REGISTER_FILE
);
265 assert(reg
.nr
< 128);
267 validate_reg(insn
, reg
);
269 insn
->bits1
.da1
.src1_reg_file
= reg
.file
;
270 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
271 insn
->bits3
.da1
.src1_abs
= reg
.abs
;
272 insn
->bits3
.da1
.src1_negate
= reg
.negate
;
274 /* Only src1 can be immediate in two-argument instructions.
276 assert(insn
->bits1
.da1
.src0_reg_file
!= BRW_IMMEDIATE_VALUE
);
278 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
279 insn
->bits3
.ud
= reg
.dw1
.ud
;
282 /* This is a hardware restriction, which may or may not be lifted
285 assert (reg
.address_mode
== BRW_ADDRESS_DIRECT
);
286 /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
288 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
289 insn
->bits3
.da1
.src1_subreg_nr
= reg
.subnr
;
290 insn
->bits3
.da1
.src1_reg_nr
= reg
.nr
;
293 insn
->bits3
.da16
.src1_subreg_nr
= reg
.subnr
/ 16;
294 insn
->bits3
.da16
.src1_reg_nr
= reg
.nr
;
297 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
298 if (reg
.width
== BRW_WIDTH_1
&&
299 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
300 insn
->bits3
.da1
.src1_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
301 insn
->bits3
.da1
.src1_width
= BRW_WIDTH_1
;
302 insn
->bits3
.da1
.src1_vert_stride
= BRW_VERTICAL_STRIDE_0
;
305 insn
->bits3
.da1
.src1_horiz_stride
= reg
.hstride
;
306 insn
->bits3
.da1
.src1_width
= reg
.width
;
307 insn
->bits3
.da1
.src1_vert_stride
= reg
.vstride
;
311 insn
->bits3
.da16
.src1_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
312 insn
->bits3
.da16
.src1_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
313 insn
->bits3
.da16
.src1_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
314 insn
->bits3
.da16
.src1_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
316 /* This is an oddity of the fact we're using the same
317 * descriptions for registers in align_16 as align_1:
319 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
320 insn
->bits3
.da16
.src1_vert_stride
= BRW_VERTICAL_STRIDE_4
;
322 insn
->bits3
.da16
.src1_vert_stride
= reg
.vstride
;
329 static void brw_set_math_message( struct brw_context
*brw
,
330 struct brw_instruction
*insn
,
332 GLuint response_length
,
335 GLboolean low_precision
,
339 struct intel_context
*intel
= &brw
->intel
;
340 brw_set_src1(insn
, brw_imm_d(0));
342 if (intel
->gen
== 5) {
343 insn
->bits3
.math_gen5
.function
= function
;
344 insn
->bits3
.math_gen5
.int_type
= integer_type
;
345 insn
->bits3
.math_gen5
.precision
= low_precision
;
346 insn
->bits3
.math_gen5
.saturate
= saturate
;
347 insn
->bits3
.math_gen5
.data_type
= dataType
;
348 insn
->bits3
.math_gen5
.snapshot
= 0;
349 insn
->bits3
.math_gen5
.header_present
= 0;
350 insn
->bits3
.math_gen5
.response_length
= response_length
;
351 insn
->bits3
.math_gen5
.msg_length
= msg_length
;
352 insn
->bits3
.math_gen5
.end_of_thread
= 0;
353 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_MATH
;
354 insn
->bits2
.send_gen5
.end_of_thread
= 0;
356 insn
->bits3
.math
.function
= function
;
357 insn
->bits3
.math
.int_type
= integer_type
;
358 insn
->bits3
.math
.precision
= low_precision
;
359 insn
->bits3
.math
.saturate
= saturate
;
360 insn
->bits3
.math
.data_type
= dataType
;
361 insn
->bits3
.math
.response_length
= response_length
;
362 insn
->bits3
.math
.msg_length
= msg_length
;
363 insn
->bits3
.math
.msg_target
= BRW_MESSAGE_TARGET_MATH
;
364 insn
->bits3
.math
.end_of_thread
= 0;
369 static void brw_set_ff_sync_message(struct brw_context
*brw
,
370 struct brw_instruction
*insn
,
372 GLuint response_length
,
373 GLboolean end_of_thread
)
375 struct intel_context
*intel
= &brw
->intel
;
376 brw_set_src1(insn
, brw_imm_d(0));
378 insn
->bits3
.urb_gen5
.opcode
= 1; /* FF_SYNC */
379 insn
->bits3
.urb_gen5
.offset
= 0; /* Not used by FF_SYNC */
380 insn
->bits3
.urb_gen5
.swizzle_control
= 0; /* Not used by FF_SYNC */
381 insn
->bits3
.urb_gen5
.allocate
= allocate
;
382 insn
->bits3
.urb_gen5
.used
= 0; /* Not used by FF_SYNC */
383 insn
->bits3
.urb_gen5
.complete
= 0; /* Not used by FF_SYNC */
384 insn
->bits3
.urb_gen5
.header_present
= 1;
385 insn
->bits3
.urb_gen5
.response_length
= response_length
; /* may be 1 or 0 */
386 insn
->bits3
.urb_gen5
.msg_length
= 1;
387 insn
->bits3
.urb_gen5
.end_of_thread
= end_of_thread
;
388 if (intel
->gen
>= 6) {
389 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_URB
;
391 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_URB
;
392 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
396 static void brw_set_urb_message( struct brw_context
*brw
,
397 struct brw_instruction
*insn
,
401 GLuint response_length
,
402 GLboolean end_of_thread
,
405 GLuint swizzle_control
)
407 struct intel_context
*intel
= &brw
->intel
;
408 brw_set_src1(insn
, brw_imm_d(0));
410 if (intel
->gen
>= 5) {
411 insn
->bits3
.urb_gen5
.opcode
= 0; /* ? */
412 insn
->bits3
.urb_gen5
.offset
= offset
;
413 insn
->bits3
.urb_gen5
.swizzle_control
= swizzle_control
;
414 insn
->bits3
.urb_gen5
.allocate
= allocate
;
415 insn
->bits3
.urb_gen5
.used
= used
; /* ? */
416 insn
->bits3
.urb_gen5
.complete
= complete
;
417 insn
->bits3
.urb_gen5
.header_present
= 1;
418 insn
->bits3
.urb_gen5
.response_length
= response_length
;
419 insn
->bits3
.urb_gen5
.msg_length
= msg_length
;
420 insn
->bits3
.urb_gen5
.end_of_thread
= end_of_thread
;
421 if (intel
->gen
>= 6) {
422 /* For SNB, the SFID bits moved to the condmod bits, and
423 * EOT stayed in bits3 above. Does the EOT bit setting
424 * below on Ironlake even do anything?
426 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_URB
;
428 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_URB
;
429 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
432 insn
->bits3
.urb
.opcode
= 0; /* ? */
433 insn
->bits3
.urb
.offset
= offset
;
434 insn
->bits3
.urb
.swizzle_control
= swizzle_control
;
435 insn
->bits3
.urb
.allocate
= allocate
;
436 insn
->bits3
.urb
.used
= used
; /* ? */
437 insn
->bits3
.urb
.complete
= complete
;
438 insn
->bits3
.urb
.response_length
= response_length
;
439 insn
->bits3
.urb
.msg_length
= msg_length
;
440 insn
->bits3
.urb
.msg_target
= BRW_MESSAGE_TARGET_URB
;
441 insn
->bits3
.urb
.end_of_thread
= end_of_thread
;
445 static void brw_set_dp_write_message( struct brw_context
*brw
,
446 struct brw_instruction
*insn
,
447 GLuint binding_table_index
,
451 GLboolean header_present
,
452 GLuint pixel_scoreboard_clear
,
453 GLuint response_length
,
454 GLuint end_of_thread
,
455 GLuint send_commit_msg
)
457 struct intel_context
*intel
= &brw
->intel
;
458 brw_set_src1(insn
, brw_imm_ud(0));
460 if (intel
->gen
>= 6) {
461 insn
->bits3
.dp_render_cache
.binding_table_index
= binding_table_index
;
462 insn
->bits3
.dp_render_cache
.msg_control
= msg_control
;
463 insn
->bits3
.dp_render_cache
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
464 insn
->bits3
.dp_render_cache
.msg_type
= msg_type
;
465 insn
->bits3
.dp_render_cache
.send_commit_msg
= send_commit_msg
;
466 insn
->bits3
.dp_render_cache
.header_present
= header_present
;
467 insn
->bits3
.dp_render_cache
.response_length
= response_length
;
468 insn
->bits3
.dp_render_cache
.msg_length
= msg_length
;
469 insn
->bits3
.dp_render_cache
.end_of_thread
= end_of_thread
;
470 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
471 /* XXX really need below? */
472 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
473 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
474 } else if (intel
->gen
== 5) {
475 insn
->bits3
.dp_write_gen5
.binding_table_index
= binding_table_index
;
476 insn
->bits3
.dp_write_gen5
.msg_control
= msg_control
;
477 insn
->bits3
.dp_write_gen5
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
478 insn
->bits3
.dp_write_gen5
.msg_type
= msg_type
;
479 insn
->bits3
.dp_write_gen5
.send_commit_msg
= send_commit_msg
;
480 insn
->bits3
.dp_write_gen5
.header_present
= header_present
;
481 insn
->bits3
.dp_write_gen5
.response_length
= response_length
;
482 insn
->bits3
.dp_write_gen5
.msg_length
= msg_length
;
483 insn
->bits3
.dp_write_gen5
.end_of_thread
= end_of_thread
;
484 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
485 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
487 insn
->bits3
.dp_write
.binding_table_index
= binding_table_index
;
488 insn
->bits3
.dp_write
.msg_control
= msg_control
;
489 insn
->bits3
.dp_write
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
490 insn
->bits3
.dp_write
.msg_type
= msg_type
;
491 insn
->bits3
.dp_write
.send_commit_msg
= send_commit_msg
;
492 insn
->bits3
.dp_write
.response_length
= response_length
;
493 insn
->bits3
.dp_write
.msg_length
= msg_length
;
494 insn
->bits3
.dp_write
.msg_target
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
495 insn
->bits3
.dp_write
.end_of_thread
= end_of_thread
;
499 static void brw_set_dp_read_message( struct brw_context
*brw
,
500 struct brw_instruction
*insn
,
501 GLuint binding_table_index
,
506 GLuint response_length
,
507 GLuint end_of_thread
)
509 struct intel_context
*intel
= &brw
->intel
;
510 brw_set_src1(insn
, brw_imm_d(0));
512 if (intel
->gen
== 5) {
513 insn
->bits3
.dp_read_gen5
.binding_table_index
= binding_table_index
;
514 insn
->bits3
.dp_read_gen5
.msg_control
= msg_control
;
515 insn
->bits3
.dp_read_gen5
.msg_type
= msg_type
;
516 insn
->bits3
.dp_read_gen5
.target_cache
= target_cache
;
517 insn
->bits3
.dp_read_gen5
.header_present
= 1;
518 insn
->bits3
.dp_read_gen5
.response_length
= response_length
;
519 insn
->bits3
.dp_read_gen5
.msg_length
= msg_length
;
520 insn
->bits3
.dp_read_gen5
.pad1
= 0;
521 insn
->bits3
.dp_read_gen5
.end_of_thread
= end_of_thread
;
522 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_READ
;
523 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
525 insn
->bits3
.dp_read
.binding_table_index
= binding_table_index
; /*0:7*/
526 insn
->bits3
.dp_read
.msg_control
= msg_control
; /*8:11*/
527 insn
->bits3
.dp_read
.msg_type
= msg_type
; /*12:13*/
528 insn
->bits3
.dp_read
.target_cache
= target_cache
; /*14:15*/
529 insn
->bits3
.dp_read
.response_length
= response_length
; /*16:19*/
530 insn
->bits3
.dp_read
.msg_length
= msg_length
; /*20:23*/
531 insn
->bits3
.dp_read
.msg_target
= BRW_MESSAGE_TARGET_DATAPORT_READ
; /*24:27*/
532 insn
->bits3
.dp_read
.pad1
= 0; /*28:30*/
533 insn
->bits3
.dp_read
.end_of_thread
= end_of_thread
; /*31*/
537 static void brw_set_sampler_message(struct brw_context
*brw
,
538 struct brw_instruction
*insn
,
539 GLuint binding_table_index
,
542 GLuint response_length
,
545 GLuint header_present
,
548 struct intel_context
*intel
= &brw
->intel
;
550 brw_set_src1(insn
, brw_imm_d(0));
552 if (intel
->gen
>= 5) {
553 insn
->bits3
.sampler_gen5
.binding_table_index
= binding_table_index
;
554 insn
->bits3
.sampler_gen5
.sampler
= sampler
;
555 insn
->bits3
.sampler_gen5
.msg_type
= msg_type
;
556 insn
->bits3
.sampler_gen5
.simd_mode
= simd_mode
;
557 insn
->bits3
.sampler_gen5
.header_present
= header_present
;
558 insn
->bits3
.sampler_gen5
.response_length
= response_length
;
559 insn
->bits3
.sampler_gen5
.msg_length
= msg_length
;
560 insn
->bits3
.sampler_gen5
.end_of_thread
= eot
;
562 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_SAMPLER
;
564 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_SAMPLER
;
565 insn
->bits2
.send_gen5
.end_of_thread
= eot
;
567 } else if (intel
->is_g4x
) {
568 insn
->bits3
.sampler_g4x
.binding_table_index
= binding_table_index
;
569 insn
->bits3
.sampler_g4x
.sampler
= sampler
;
570 insn
->bits3
.sampler_g4x
.msg_type
= msg_type
;
571 insn
->bits3
.sampler_g4x
.response_length
= response_length
;
572 insn
->bits3
.sampler_g4x
.msg_length
= msg_length
;
573 insn
->bits3
.sampler_g4x
.end_of_thread
= eot
;
574 insn
->bits3
.sampler_g4x
.msg_target
= BRW_MESSAGE_TARGET_SAMPLER
;
576 insn
->bits3
.sampler
.binding_table_index
= binding_table_index
;
577 insn
->bits3
.sampler
.sampler
= sampler
;
578 insn
->bits3
.sampler
.msg_type
= msg_type
;
579 insn
->bits3
.sampler
.return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
580 insn
->bits3
.sampler
.response_length
= response_length
;
581 insn
->bits3
.sampler
.msg_length
= msg_length
;
582 insn
->bits3
.sampler
.end_of_thread
= eot
;
583 insn
->bits3
.sampler
.msg_target
= BRW_MESSAGE_TARGET_SAMPLER
;
589 static struct brw_instruction
*next_insn( struct brw_compile
*p
,
592 struct brw_instruction
*insn
;
594 assert(p
->nr_insn
+ 1 < BRW_EU_MAX_INSN
);
596 insn
= &p
->store
[p
->nr_insn
++];
597 memcpy(insn
, p
->current
, sizeof(*insn
));
599 /* Reset this one-shot flag:
602 if (p
->current
->header
.destreg__conditionalmod
) {
603 p
->current
->header
.destreg__conditionalmod
= 0;
604 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
607 insn
->header
.opcode
= opcode
;
612 static struct brw_instruction
*brw_alu1( struct brw_compile
*p
,
617 struct brw_instruction
*insn
= next_insn(p
, opcode
);
618 brw_set_dest(insn
, dest
);
619 brw_set_src0(insn
, src
);
623 static struct brw_instruction
*brw_alu2(struct brw_compile
*p
,
627 struct brw_reg src1
)
629 struct brw_instruction
*insn
= next_insn(p
, opcode
);
630 brw_set_dest(insn
, dest
);
631 brw_set_src0(insn
, src0
);
632 brw_set_src1(insn
, src1
);
637 /***********************************************************************
638 * Convenience routines.
641 struct brw_instruction *brw_##OP(struct brw_compile *p, \
642 struct brw_reg dest, \
643 struct brw_reg src0) \
645 return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
649 struct brw_instruction *brw_##OP(struct brw_compile *p, \
650 struct brw_reg dest, \
651 struct brw_reg src0, \
652 struct brw_reg src1) \
654 return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
682 struct brw_instruction
*brw_ADD(struct brw_compile
*p
,
688 if (src0
.type
== BRW_REGISTER_TYPE_F
||
689 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
690 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
691 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
692 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
695 if (src1
.type
== BRW_REGISTER_TYPE_F
||
696 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
697 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
698 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
699 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
702 return brw_alu2(p
, BRW_OPCODE_ADD
, dest
, src0
, src1
);
705 struct brw_instruction
*brw_MUL(struct brw_compile
*p
,
711 if (src0
.type
== BRW_REGISTER_TYPE_D
||
712 src0
.type
== BRW_REGISTER_TYPE_UD
||
713 src1
.type
== BRW_REGISTER_TYPE_D
||
714 src1
.type
== BRW_REGISTER_TYPE_UD
) {
715 assert(dest
.type
!= BRW_REGISTER_TYPE_F
);
718 if (src0
.type
== BRW_REGISTER_TYPE_F
||
719 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
720 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
721 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
722 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
725 if (src1
.type
== BRW_REGISTER_TYPE_F
||
726 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
727 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
728 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
729 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
732 assert(src0
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
733 src0
.nr
!= BRW_ARF_ACCUMULATOR
);
734 assert(src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
735 src1
.nr
!= BRW_ARF_ACCUMULATOR
);
737 return brw_alu2(p
, BRW_OPCODE_MUL
, dest
, src0
, src1
);
741 void brw_NOP(struct brw_compile
*p
)
743 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_NOP
);
744 brw_set_dest(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
745 brw_set_src0(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
746 brw_set_src1(insn
, brw_imm_ud(0x0));
753 /***********************************************************************
754 * Comparisons, if/else/endif
757 struct brw_instruction
*brw_JMPI(struct brw_compile
*p
,
762 struct brw_instruction
*insn
= brw_alu2(p
, BRW_OPCODE_JMPI
, dest
, src0
, src1
);
764 insn
->header
.execution_size
= 1;
765 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
766 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
768 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
773 /* EU takes the value from the flag register and pushes it onto some
774 * sort of a stack (presumably merging with any flag value already on
775 * the stack). Within an if block, the flags at the top of the stack
776 * control execution on each channel of the unit, eg. on each of the
777 * 16 pixel values in our wm programs.
779 * When the matching 'else' instruction is reached (presumably by
780 * countdown of the instruction count patched in by our ELSE/ENDIF
781 * functions), the relevent flags are inverted.
783 * When the matching 'endif' instruction is reached, the flags are
784 * popped off. If the stack is now empty, normal execution resumes.
786 * No attempt is made to deal with stack overflow (14 elements?).
788 struct brw_instruction
*brw_IF(struct brw_compile
*p
, GLuint execute_size
)
790 struct brw_instruction
*insn
;
792 if (p
->single_program_flow
) {
793 assert(execute_size
== BRW_EXECUTE_1
);
795 insn
= next_insn(p
, BRW_OPCODE_ADD
);
796 insn
->header
.predicate_inverse
= 1;
798 insn
= next_insn(p
, BRW_OPCODE_IF
);
801 /* Override the defaults for this instruction:
803 brw_set_dest(insn
, brw_ip_reg());
804 brw_set_src0(insn
, brw_ip_reg());
805 brw_set_src1(insn
, brw_imm_d(0x0));
807 insn
->header
.execution_size
= execute_size
;
808 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
809 insn
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
810 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
811 if (!p
->single_program_flow
)
812 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
814 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
820 struct brw_instruction
*brw_ELSE(struct brw_compile
*p
,
821 struct brw_instruction
*if_insn
)
823 struct intel_context
*intel
= &p
->brw
->intel
;
824 struct brw_instruction
*insn
;
827 /* jump count is for 64bit data chunk each, so one 128bit
828 instruction requires 2 chunks. */
832 if (p
->single_program_flow
) {
833 insn
= next_insn(p
, BRW_OPCODE_ADD
);
835 insn
= next_insn(p
, BRW_OPCODE_ELSE
);
838 brw_set_dest(insn
, brw_ip_reg());
839 brw_set_src0(insn
, brw_ip_reg());
840 brw_set_src1(insn
, brw_imm_d(0x0));
842 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
843 insn
->header
.execution_size
= if_insn
->header
.execution_size
;
844 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
845 if (!p
->single_program_flow
)
846 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
848 /* Patch the if instruction to point at this instruction.
850 if (p
->single_program_flow
) {
851 assert(if_insn
->header
.opcode
== BRW_OPCODE_ADD
);
853 if_insn
->bits3
.ud
= (insn
- if_insn
+ 1) * 16;
855 assert(if_insn
->header
.opcode
== BRW_OPCODE_IF
);
857 if_insn
->bits3
.if_else
.jump_count
= br
* (insn
- if_insn
);
858 if_insn
->bits3
.if_else
.pop_count
= 0;
859 if_insn
->bits3
.if_else
.pad0
= 0;
865 void brw_ENDIF(struct brw_compile
*p
,
866 struct brw_instruction
*patch_insn
)
868 struct intel_context
*intel
= &p
->brw
->intel
;
874 if (p
->single_program_flow
) {
875 /* In single program flow mode, there's no need to execute an ENDIF,
876 * since we don't need to do any stack operations, and if we're executing
877 * currently, we want to just continue executing.
879 struct brw_instruction
*next
= &p
->store
[p
->nr_insn
];
881 assert(patch_insn
->header
.opcode
== BRW_OPCODE_ADD
);
883 patch_insn
->bits3
.ud
= (next
- patch_insn
) * 16;
885 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_ENDIF
);
887 brw_set_dest(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
888 brw_set_src0(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
889 brw_set_src1(insn
, brw_imm_d(0x0));
891 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
892 insn
->header
.execution_size
= patch_insn
->header
.execution_size
;
893 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
894 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
896 assert(patch_insn
->bits3
.if_else
.jump_count
== 0);
898 /* Patch the if or else instructions to point at this or the next
899 * instruction respectively.
901 if (patch_insn
->header
.opcode
== BRW_OPCODE_IF
) {
902 /* Automagically turn it into an IFF:
904 patch_insn
->header
.opcode
= BRW_OPCODE_IFF
;
905 patch_insn
->bits3
.if_else
.jump_count
= br
* (insn
- patch_insn
+ 1);
906 patch_insn
->bits3
.if_else
.pop_count
= 0;
907 patch_insn
->bits3
.if_else
.pad0
= 0;
908 } else if (patch_insn
->header
.opcode
== BRW_OPCODE_ELSE
) {
909 patch_insn
->bits3
.if_else
.jump_count
= br
* (insn
- patch_insn
+ 1);
910 patch_insn
->bits3
.if_else
.pop_count
= 1;
911 patch_insn
->bits3
.if_else
.pad0
= 0;
916 /* Also pop item off the stack in the endif instruction:
918 insn
->bits3
.if_else
.jump_count
= 0;
919 insn
->bits3
.if_else
.pop_count
= 1;
920 insn
->bits3
.if_else
.pad0
= 0;
924 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
, int pop_count
)
926 struct brw_instruction
*insn
;
927 insn
= next_insn(p
, BRW_OPCODE_BREAK
);
928 brw_set_dest(insn
, brw_ip_reg());
929 brw_set_src0(insn
, brw_ip_reg());
930 brw_set_src1(insn
, brw_imm_d(0x0));
931 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
932 insn
->header
.execution_size
= BRW_EXECUTE_8
;
933 /* insn->header.mask_control = BRW_MASK_DISABLE; */
934 insn
->bits3
.if_else
.pad0
= 0;
935 insn
->bits3
.if_else
.pop_count
= pop_count
;
939 struct brw_instruction
*brw_CONT(struct brw_compile
*p
, int pop_count
)
941 struct brw_instruction
*insn
;
942 insn
= next_insn(p
, BRW_OPCODE_CONTINUE
);
943 brw_set_dest(insn
, brw_ip_reg());
944 brw_set_src0(insn
, brw_ip_reg());
945 brw_set_src1(insn
, brw_imm_d(0x0));
946 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
947 insn
->header
.execution_size
= BRW_EXECUTE_8
;
948 /* insn->header.mask_control = BRW_MASK_DISABLE; */
949 insn
->bits3
.if_else
.pad0
= 0;
950 insn
->bits3
.if_else
.pop_count
= pop_count
;
956 struct brw_instruction
*brw_DO(struct brw_compile
*p
, GLuint execute_size
)
958 if (p
->single_program_flow
) {
959 return &p
->store
[p
->nr_insn
];
961 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_DO
);
963 /* Override the defaults for this instruction:
965 brw_set_dest(insn
, brw_null_reg());
966 brw_set_src0(insn
, brw_null_reg());
967 brw_set_src1(insn
, brw_null_reg());
969 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
970 insn
->header
.execution_size
= execute_size
;
971 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
972 /* insn->header.mask_control = BRW_MASK_ENABLE; */
973 /* insn->header.mask_control = BRW_MASK_DISABLE; */
981 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
,
982 struct brw_instruction
*do_insn
)
984 struct intel_context
*intel
= &p
->brw
->intel
;
985 struct brw_instruction
*insn
;
991 if (p
->single_program_flow
)
992 insn
= next_insn(p
, BRW_OPCODE_ADD
);
994 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
996 brw_set_dest(insn
, brw_ip_reg());
997 brw_set_src0(insn
, brw_ip_reg());
998 brw_set_src1(insn
, brw_imm_d(0x0));
1000 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1002 if (p
->single_program_flow
) {
1003 insn
->header
.execution_size
= BRW_EXECUTE_1
;
1005 insn
->bits3
.d
= (do_insn
- insn
) * 16;
1007 insn
->header
.execution_size
= do_insn
->header
.execution_size
;
1009 assert(do_insn
->header
.opcode
== BRW_OPCODE_DO
);
1010 insn
->bits3
.if_else
.jump_count
= br
* (do_insn
- insn
+ 1);
1011 insn
->bits3
.if_else
.pop_count
= 0;
1012 insn
->bits3
.if_else
.pad0
= 0;
1015 /* insn->header.mask_control = BRW_MASK_ENABLE; */
1017 /* insn->header.mask_control = BRW_MASK_DISABLE; */
1018 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1025 void brw_land_fwd_jump(struct brw_compile
*p
,
1026 struct brw_instruction
*jmp_insn
)
1028 struct intel_context
*intel
= &p
->brw
->intel
;
1029 struct brw_instruction
*landing
= &p
->store
[p
->nr_insn
];
1032 if (intel
->gen
>= 5)
1035 assert(jmp_insn
->header
.opcode
== BRW_OPCODE_JMPI
);
1036 assert(jmp_insn
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
);
1038 jmp_insn
->bits3
.ud
= jmpi
* ((landing
- jmp_insn
) - 1);
1043 /* To integrate with the above, it makes sense that the comparison
1044 * instruction should populate the flag register. It might be simpler
1045 * just to use the flag reg for most WM tasks?
1047 void brw_CMP(struct brw_compile
*p
,
1048 struct brw_reg dest
,
1050 struct brw_reg src0
,
1051 struct brw_reg src1
)
1053 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_CMP
);
1055 insn
->header
.destreg__conditionalmod
= conditional
;
1056 brw_set_dest(insn
, dest
);
1057 brw_set_src0(insn
, src0
);
1058 brw_set_src1(insn
, src1
);
1060 /* guess_execution_size(insn, src0); */
1063 /* Make it so that future instructions will use the computed flag
1064 * value until brw_set_predicate_control_flag_value() is called
1067 if (dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
1069 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
1070 p
->flag_value
= 0xff;
1074 /* Issue 'wait' instruction for n1, host could program MMIO
1075 to wake up thread. */
1076 void brw_WAIT (struct brw_compile
*p
)
1078 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_WAIT
);
1079 struct brw_reg src
= brw_notification_1_reg();
1081 brw_set_dest(insn
, src
);
1082 brw_set_src0(insn
, src
);
1083 brw_set_src1(insn
, brw_null_reg());
1084 insn
->header
.execution_size
= 0; /* must */
1085 insn
->header
.predicate_control
= 0;
1086 insn
->header
.compression_control
= 0;
1090 /***********************************************************************
1091 * Helpers for the various SEND message types:
1094 /** Extended math function, float[8].
1096 void brw_math( struct brw_compile
*p
,
1097 struct brw_reg dest
,
1105 struct intel_context
*intel
= &p
->brw
->intel
;
1107 if (intel
->gen
>= 6) {
1108 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
1110 /* Math is the same ISA format as other opcodes, except that CondModifier
1111 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1113 insn
->header
.destreg__conditionalmod
= function
;
1115 brw_set_dest(insn
, dest
);
1116 brw_set_src0(insn
, src
);
1117 brw_set_src1(insn
, brw_null_reg());
1119 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1120 GLuint msg_length
= (function
== BRW_MATH_FUNCTION_POW
) ? 2 : 1;
1121 GLuint response_length
= (function
== BRW_MATH_FUNCTION_SINCOS
) ? 2 : 1;
1122 /* Example code doesn't set predicate_control for send
1125 insn
->header
.predicate_control
= 0;
1126 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1128 brw_set_dest(insn
, dest
);
1129 brw_set_src0(insn
, src
);
1130 brw_set_math_message(p
->brw
,
1132 msg_length
, response_length
,
1134 BRW_MATH_INTEGER_UNSIGNED
,
1141 /** Extended math function, float[8].
1143 void brw_math2(struct brw_compile
*p
,
1144 struct brw_reg dest
,
1146 struct brw_reg src0
,
1147 struct brw_reg src1
)
1149 struct intel_context
*intel
= &p
->brw
->intel
;
1150 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
1152 assert(intel
->gen
>= 6);
1154 /* Math is the same ISA format as other opcodes, except that CondModifier
1155 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1157 insn
->header
.destreg__conditionalmod
= function
;
1159 brw_set_dest(insn
, dest
);
1160 brw_set_src0(insn
, src0
);
1161 brw_set_src1(insn
, src1
);
1165 * Extended math function, float[16].
1166 * Use 2 send instructions.
1168 void brw_math_16( struct brw_compile
*p
,
1169 struct brw_reg dest
,
1176 struct intel_context
*intel
= &p
->brw
->intel
;
1177 struct brw_instruction
*insn
;
1178 GLuint msg_length
= (function
== BRW_MATH_FUNCTION_POW
) ? 2 : 1;
1179 GLuint response_length
= (function
== BRW_MATH_FUNCTION_SINCOS
) ? 2 : 1;
1181 if (intel
->gen
>= 6) {
1182 insn
= next_insn(p
, BRW_OPCODE_MATH
);
1184 /* Math is the same ISA format as other opcodes, except that CondModifier
1185 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1187 insn
->header
.destreg__conditionalmod
= function
;
1189 brw_set_dest(insn
, dest
);
1190 brw_set_src0(insn
, src
);
1191 brw_set_src1(insn
, brw_null_reg());
1195 /* First instruction:
1197 brw_push_insn_state(p
);
1198 brw_set_predicate_control_flag_value(p
, 0xff);
1199 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1201 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1202 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1204 brw_set_dest(insn
, dest
);
1205 brw_set_src0(insn
, src
);
1206 brw_set_math_message(p
->brw
,
1208 msg_length
, response_length
,
1210 BRW_MATH_INTEGER_UNSIGNED
,
1213 BRW_MATH_DATA_VECTOR
);
1215 /* Second instruction:
1217 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1218 insn
->header
.compression_control
= BRW_COMPRESSION_2NDHALF
;
1219 insn
->header
.destreg__conditionalmod
= msg_reg_nr
+1;
1221 brw_set_dest(insn
, offset(dest
,1));
1222 brw_set_src0(insn
, src
);
1223 brw_set_math_message(p
->brw
,
1225 msg_length
, response_length
,
1227 BRW_MATH_INTEGER_UNSIGNED
,
1230 BRW_MATH_DATA_VECTOR
);
1232 brw_pop_insn_state(p
);
1237 * Write block of 16 dwords/floats to the data port Render Cache scratch buffer.
1238 * Scratch offset should be a multiple of 64.
1239 * Used for register spilling.
1241 void brw_dp_WRITE_16( struct brw_compile
*p
,
1243 GLuint scratch_offset
)
1245 struct intel_context
*intel
= &p
->brw
->intel
;
1246 GLuint msg_reg_nr
= 1;
1248 brw_push_insn_state(p
);
1249 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1250 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1252 /* set message header global offset field (reg 0, element 2) */
1254 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D
),
1255 brw_imm_d(scratch_offset
));
1257 brw_pop_insn_state(p
);
1261 GLuint msg_length
= 3;
1262 struct brw_reg dest
;
1263 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1264 int send_commit_msg
;
1266 insn
->header
.predicate_control
= 0; /* XXX */
1267 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1268 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1270 /* Until gen6, writes followed by reads from the same location
1271 * are not guaranteed to be ordered unless write_commit is set.
1272 * If set, then a no-op write is issued to the destination
1273 * register to set a dependency, and a read from the destination
1274 * can be used to ensure the ordering.
1276 * For gen6, only writes between different threads need ordering
1277 * protection. Our use of DP writes is all about register
1278 * spilling within a thread.
1280 if (intel
->gen
>= 6) {
1281 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
1282 send_commit_msg
= 0;
1284 dest
= brw_uw16_grf(0, 0);
1285 send_commit_msg
= 1;
1288 brw_set_dest(insn
, dest
);
1289 brw_set_src0(insn
, src
);
1291 brw_set_dp_write_message(p
->brw
,
1293 255, /* binding table index (255=stateless) */
1294 BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
, /* msg_control */
1295 BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
, /* msg_type */
1297 GL_TRUE
, /* header_present */
1298 0, /* pixel scoreboard */
1299 send_commit_msg
, /* response_length */
1307 * Read block of 16 dwords/floats from the data port Render Cache scratch buffer.
1308 * Scratch offset should be a multiple of 64.
1309 * Used for register spilling.
1311 void brw_dp_READ_16( struct brw_compile
*p
,
1312 struct brw_reg dest
,
1313 GLuint scratch_offset
)
1315 GLuint msg_reg_nr
= 1;
1317 brw_push_insn_state(p
);
1318 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1319 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1321 /* set message header global offset field (reg 0, element 2) */
1323 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D
),
1324 brw_imm_d(scratch_offset
));
1326 brw_pop_insn_state(p
);
1330 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1332 insn
->header
.predicate_control
= 0; /* XXX */
1333 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1334 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1336 brw_set_dest(insn
, dest
); /* UW? */
1337 brw_set_src0(insn
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1339 brw_set_dp_read_message(p
->brw
,
1341 255, /* binding table index (255=stateless) */
1342 BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
,
1343 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1344 1, /* target cache (render/scratch) */
1346 2, /* response_length */
1353 * Read a float[4] vector from the data port Data Cache (const buffer).
1354 * Location (in buffer) should be a multiple of 16.
1355 * Used for fetching shader constants.
1356 * If relAddr is true, we'll do an indirect fetch using the address register.
1358 void brw_dp_READ_4( struct brw_compile
*p
,
1359 struct brw_reg dest
,
1362 GLuint bind_table_index
)
1364 /* XXX: relAddr not implemented */
1365 GLuint msg_reg_nr
= 1;
1368 brw_push_insn_state(p
);
1369 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1370 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1371 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1373 /* Setup MRF[1] with location/offset into const buffer */
1374 b
= brw_message_reg(msg_reg_nr
);
1375 b
= retype(b
, BRW_REGISTER_TYPE_UD
);
1376 /* XXX I think we're setting all the dwords of MRF[1] to 'location'.
1377 * when the docs say only dword[2] should be set. Hmmm. But it works.
1379 brw_MOV(p
, b
, brw_imm_ud(location
));
1380 brw_pop_insn_state(p
);
1384 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1386 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1387 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1388 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1389 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1391 /* cast dest to a uword[8] vector */
1392 dest
= retype(vec8(dest
), BRW_REGISTER_TYPE_UW
);
1394 brw_set_dest(insn
, dest
);
1395 brw_set_src0(insn
, brw_null_reg());
1397 brw_set_dp_read_message(p
->brw
,
1400 0, /* msg_control (0 means 1 Oword) */
1401 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1402 0, /* source cache = data cache */
1404 1, /* response_length (1 Oword) */
1411 * Read float[4] constant(s) from VS constant buffer.
1412 * For relative addressing, two float[4] constants will be read into 'dest'.
1413 * Otherwise, one float[4] constant will be read into the lower half of 'dest'.
1415 void brw_dp_READ_4_vs(struct brw_compile
*p
,
1416 struct brw_reg dest
,
1418 GLuint bind_table_index
)
1420 struct brw_instruction
*insn
;
1421 GLuint msg_reg_nr
= 1;
1425 printf("vs const read msg, location %u, msg_reg_nr %d\n",
1426 location, msg_reg_nr);
1429 /* Setup MRF[1] with location/offset into const buffer */
1430 brw_push_insn_state(p
);
1431 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1432 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1433 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1435 /* XXX I think we're setting all the dwords of MRF[1] to 'location'.
1436 * when the docs say only dword[2] should be set. Hmmm. But it works.
1438 b
= brw_message_reg(msg_reg_nr
);
1439 b
= retype(b
, BRW_REGISTER_TYPE_UD
);
1440 /*b = get_element_ud(b, 2);*/
1441 brw_MOV(p
, b
, brw_imm_ud(location
));
1443 brw_pop_insn_state(p
);
1445 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1447 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1448 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1449 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1450 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1452 brw_set_dest(insn
, dest
);
1453 brw_set_src0(insn
, brw_null_reg());
1455 brw_set_dp_read_message(p
->brw
,
1459 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1460 0, /* source cache = data cache */
1462 1, /* response_length (1 Oword) */
1467 * Read a float[4] constant per vertex from VS constant buffer, with
1468 * relative addressing.
1470 void brw_dp_READ_4_vs_relative(struct brw_compile
*p
,
1471 struct brw_reg dest
,
1472 struct brw_reg addr_reg
,
1474 GLuint bind_table_index
)
1476 struct intel_context
*intel
= &p
->brw
->intel
;
1479 /* Setup MRF[1] with offset into const buffer */
1480 brw_push_insn_state(p
);
1481 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1482 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1483 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1485 /* M1.0 is block offset 0, M1.4 is block offset 1, all other
1488 brw_ADD(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
),
1489 addr_reg
, brw_imm_d(offset
));
1490 brw_pop_insn_state(p
);
1492 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1494 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1495 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1496 insn
->header
.destreg__conditionalmod
= 0;
1497 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1499 brw_set_dest(insn
, dest
);
1500 brw_set_src0(insn
, brw_vec8_grf(0, 0));
1502 if (intel
->gen
== 6)
1503 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1504 else if (intel
->gen
== 5 || intel
->is_g4x
)
1505 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1507 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1509 brw_set_dp_read_message(p
->brw
,
1512 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1514 0, /* source cache = data cache */
1516 1, /* response_length */
1522 void brw_fb_WRITE(struct brw_compile
*p
,
1524 struct brw_reg dest
,
1526 struct brw_reg src0
,
1527 GLuint binding_table_index
,
1529 GLuint response_length
,
1532 struct intel_context
*intel
= &p
->brw
->intel
;
1533 struct brw_instruction
*insn
;
1534 GLuint msg_control
, msg_type
;
1535 GLboolean header_present
= GL_TRUE
;
1537 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1538 insn
->header
.predicate_control
= 0; /* XXX */
1539 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1541 if (intel
->gen
>= 6) {
1542 if (msg_length
== 4)
1543 header_present
= GL_FALSE
;
1545 /* headerless version, just submit color payload */
1546 src0
= brw_message_reg(msg_reg_nr
);
1548 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6
;
1550 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1552 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
1555 if (dispatch_width
== 16)
1556 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
1558 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
1560 brw_set_dest(insn
, dest
);
1561 brw_set_src0(insn
, src0
);
1562 brw_set_dp_write_message(p
->brw
,
1564 binding_table_index
,
1569 1, /* pixel scoreboard */
1572 0 /* send_commit_msg */);
1577 * Texture sample instruction.
1578 * Note: the msg_type plus msg_length values determine exactly what kind
1579 * of sampling operation is performed. See volume 4, page 161 of docs.
1581 void brw_SAMPLE(struct brw_compile
*p
,
1582 struct brw_reg dest
,
1584 struct brw_reg src0
,
1585 GLuint binding_table_index
,
1589 GLuint response_length
,
1592 GLuint header_present
,
1595 struct intel_context
*intel
= &p
->brw
->intel
;
1596 GLboolean need_stall
= 0;
1598 if (writemask
== 0) {
1599 /*printf("%s: zero writemask??\n", __FUNCTION__); */
1603 /* Hardware doesn't do destination dependency checking on send
1604 * instructions properly. Add a workaround which generates the
1605 * dependency by other means. In practice it seems like this bug
1606 * only crops up for texture samples, and only where registers are
1607 * written by the send and then written again later without being
1608 * read in between. Luckily for us, we already track that
1609 * information and use it to modify the writemask for the
1610 * instruction, so that is a guide for whether a workaround is
1613 if (writemask
!= WRITEMASK_XYZW
) {
1614 GLuint dst_offset
= 0;
1615 GLuint i
, newmask
= 0, len
= 0;
1617 for (i
= 0; i
< 4; i
++) {
1618 if (writemask
& (1<<i
))
1622 for (; i
< 4; i
++) {
1623 if (!(writemask
& (1<<i
)))
1629 if (newmask
!= writemask
) {
1631 /* printf("need stall %x %x\n", newmask , writemask); */
1634 GLboolean dispatch_16
= GL_FALSE
;
1636 struct brw_reg m1
= brw_message_reg(msg_reg_nr
);
1638 guess_execution_size(p
->current
, dest
);
1639 if (p
->current
->header
.execution_size
== BRW_EXECUTE_16
)
1640 dispatch_16
= GL_TRUE
;
1642 newmask
= ~newmask
& WRITEMASK_XYZW
;
1644 brw_push_insn_state(p
);
1646 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1647 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1649 brw_MOV(p
, m1
, brw_vec8_grf(0,0));
1650 brw_MOV(p
, get_element_ud(m1
, 2), brw_imm_ud(newmask
<< 12));
1652 brw_pop_insn_state(p
);
1654 src0
= retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
);
1655 dest
= offset(dest
, dst_offset
);
1657 /* For 16-wide dispatch, masked channels are skipped in the
1658 * response. For 8-wide, masked channels still take up slots,
1659 * and are just not written to.
1662 response_length
= len
* 2;
1667 struct brw_instruction
*insn
;
1669 /* Sandybridge doesn't have the implied move for SENDs,
1670 * and the first message register index comes from src0.
1672 if (intel
->gen
>= 6) {
1673 brw_push_insn_state(p
);
1674 brw_set_mask_control( p
, BRW_MASK_DISABLE
);
1675 /* m1 contains header? */
1676 brw_MOV(p
, brw_message_reg(msg_reg_nr
), src0
);
1677 brw_pop_insn_state(p
);
1678 src0
= brw_message_reg(msg_reg_nr
);
1681 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1682 insn
->header
.predicate_control
= 0; /* XXX */
1683 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1685 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1687 brw_set_dest(insn
, dest
);
1688 brw_set_src0(insn
, src0
);
1689 brw_set_sampler_message(p
->brw
, insn
,
1690 binding_table_index
,
1701 struct brw_reg reg
= vec8(offset(dest
, response_length
-1));
1703 /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 }
1705 brw_push_insn_state(p
);
1706 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1707 brw_MOV(p
, reg
, reg
);
1708 brw_pop_insn_state(p
);
1713 /* All these variables are pretty confusing - we might be better off
1714 * using bitmasks and macros for this, in the old style. Or perhaps
1715 * just having the caller instantiate the fields in dword3 itself.
1717 void brw_urb_WRITE(struct brw_compile
*p
,
1718 struct brw_reg dest
,
1720 struct brw_reg src0
,
1724 GLuint response_length
,
1726 GLboolean writes_complete
,
1730 struct intel_context
*intel
= &p
->brw
->intel
;
1731 struct brw_instruction
*insn
;
1733 /* Sandybridge doesn't have the implied move for SENDs,
1734 * and the first message register index comes from src0.
1736 if (intel
->gen
>= 6) {
1737 brw_push_insn_state(p
);
1738 brw_set_mask_control( p
, BRW_MASK_DISABLE
);
1739 brw_MOV(p
, brw_message_reg(msg_reg_nr
), src0
);
1740 brw_pop_insn_state(p
);
1741 src0
= brw_message_reg(msg_reg_nr
);
1744 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1746 assert(msg_length
< BRW_MAX_MRF
);
1748 brw_set_dest(insn
, dest
);
1749 brw_set_src0(insn
, src0
);
1750 brw_set_src1(insn
, brw_imm_d(0));
1753 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1755 brw_set_urb_message(p
->brw
,
1767 void brw_ff_sync(struct brw_compile
*p
,
1768 struct brw_reg dest
,
1770 struct brw_reg src0
,
1772 GLuint response_length
,
1775 struct intel_context
*intel
= &p
->brw
->intel
;
1776 struct brw_instruction
*insn
;
1778 /* Sandybridge doesn't have the implied move for SENDs,
1779 * and the first message register index comes from src0.
1781 if (intel
->gen
>= 6) {
1782 brw_push_insn_state(p
);
1783 brw_set_mask_control( p
, BRW_MASK_DISABLE
);
1784 brw_MOV(p
, brw_message_reg(msg_reg_nr
), src0
);
1785 brw_pop_insn_state(p
);
1786 src0
= brw_message_reg(msg_reg_nr
);
1789 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1790 brw_set_dest(insn
, dest
);
1791 brw_set_src0(insn
, src0
);
1792 brw_set_src1(insn
, brw_imm_d(0));
1795 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1797 brw_set_ff_sync_message(p
->brw
,