src/mesa/drivers/dri/i965/brw_fallback.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "main/glheader.h"
  29 #include "main/context.h"
  30 #include "main/enums.h"
  31 #include "main/imports.h"
  32 #include "main/macros.h"
  33 #include "main/mtypes.h"
  34
  35 #include "swrast_setup/swrast_setup.h"
  36 #include "swrast/swrast.h"
  37 #include "tnl/tnl.h"
  38 #include "brw_context.h"
  39 #include "intel_chipset.h"
  40 #include "intel_fbo.h"
  41 #include "intel_regions.h"
  42
  43 #include "glapi/glapi.h"
  44
  45 #define FILE_DEBUG_FLAG DEBUG_FALLBACKS
  46
  47 static GLboolean do_check_fallback(struct brw_context *brw)
  48 {
  49    struct intel_context *intel = &brw->intel;
  50    GLcontext *ctx = &brw->intel.ctx;
  51    GLuint i;
  52
  53    if (brw->intel.no_rast) {
  54       DBG("FALLBACK: rasterization disabled\n");
  55       return GL_TRUE;
  56    }
  57
  58    /* _NEW_RENDERMODE
  59     */
  60    if (ctx->RenderMode != GL_RENDER) {
  61       DBG("FALLBACK: render mode\n");
  62       return GL_TRUE;
  63    }
  64
  65    /* _NEW_TEXTURE:
  66     */
  67    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
  68       struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
  69       if (texUnit->_ReallyEnabled) {
  70          struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current);
  71          struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel];
  72          if (texImage->Border) {
  73             DBG("FALLBACK: texture border\n");
  74             return GL_TRUE;
  75          }
  76       }
  77    }
  78
  79    /* _NEW_STENCIL
  80     */
  81    if (ctx->Stencil._Enabled &&
  82        (ctx->DrawBuffer->Name == 0 && !brw->intel.hw_stencil)) {
  83       DBG("FALLBACK: stencil\n");
  84       return GL_TRUE;
  85    }
  86
  87    /* _NEW_BUFFERS */
  88    if (IS_965(intel->intelScreen->deviceID) &&
  89        !IS_G4X(intel->intelScreen->deviceID)) {
  90       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  91          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  92          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
  93
  94          /* The original gen4 hardware couldn't set up WM surfaces pointing
  95           * at an offset within a tile, which can happen when rendering to
  96           * anything but the base level of a texture or the +X face/0 depth.
  97           * This was fixed with the 4 Series hardware.
  98           *
  99           * For these original chips, you would have to make the depth and
 100           * color destination surfaces include information on the texture
 101           * type, LOD, face, and various limits to use them as a destination.
 102           * I would have done this, but there's also a nasty requirement that
 103           * the depth and the color surfaces all be of the same LOD, which
 104           * may be a worse requirement than this alignment.  (Also, we may
 105           * want to just demote the texture to untiled, instead).
 106           */
 107          if (irb->region && irb->region->tiling != I915_TILING_NONE &&
 108              (irb->region->draw_offset & 4095)) {
 109             DBG("FALLBACK: non-tile-aligned destination for tiled FBO\n");
 110             return GL_TRUE;
 111          }
 112       }
 113    }
 114
 115    return GL_FALSE;
 116 }
 117
 118 static void check_fallback(struct brw_context *brw)
 119 {
 120    brw->intel.Fallback = do_check_fallback(brw);
 121 }
 122
 123 const struct brw_tracked_state brw_check_fallback = {
 124    .dirty = {
 125       .mesa = _NEW_BUFFERS | _NEW_RENDERMODE | _NEW_TEXTURE | _NEW_STENCIL,
 126       .brw  = 0,
 127       .cache = 0
 128    },
 129    .prepare = check_fallback
 130 };
 131
 132
 133
 134
 135 /**
 136  * Called by the INTEL_FALLBACK() macro.
 137  * NOTE: this is a no-op for the i965 driver.  The brw->intel.Fallback
 138  * field is treated as a boolean, not a bitmask.  It's only set in a
 139  * couple of places.
 140  */
 141 void intelFallback( struct intel_context *intel, GLuint bit, GLboolean mode )
 142 {
 143 }
 144
 145
 146